CN102067640B - Channel interleaving method and channel interleaver - Google Patents
Channel interleaving method and channel interleaver Download PDFInfo
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- CN102067640B CN102067640B CN200980000381.0A CN200980000381A CN102067640B CN 102067640 B CN102067640 B CN 102067640B CN 200980000381 A CN200980000381 A CN 200980000381A CN 102067640 B CN102067640 B CN 102067640B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Abstract
Disclosed are a channel interleaving method and a channel interleaver, the method comprises: receiving N first check sub-blocks and N second check sub-blocks from an encoder, wherein N is an integer and N>=1; respectively partitioning each one of the first and second check sub-blocks into multiple data units, and each data unit contains M bits with different reliability levels, M=2 and M is an integer which could divide the integer of the bits number of a modulation symbol; it is supposed that the descending order of different reliability levels is R0>=R1>=...Ri>=...RM-1, i=0, 1, ..., M-1, for respective bits within each data unit in every first check sub-blocks, interchanging its position in that data unit such that the position of the bit with reliability level of Ri within the interchanged data unit corresponds to the position of the bit with reliability level of RM-1-i within the corresponding data unit in the corresponding second check sub-block.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of channel interleaving method and channel interleaver.
Background technology
Channel interleaver average sudden channel error effectively.In IEEE 802.16e standard, used one to can be used for the channel interleaver of CTC (Convolutional Turbo Code is called for short CTC) coding.Fig. 1 shows the schematic diagram that carries out CTC channel interleaving according to IEEE 802.16e standard.According to the channel interleaver of this standard, mainly by following process, process CTC coded data is interweaved:
1, bitslicing
Particularly, the bit sequence of female bit rate is divided into 6 sub-block A, B, Y
1, W
1, Y
2and W
2, wherein, sub-block A and sub-block B represent information bit, i.e. payload data, sub-block Y
1with sub-block W
1represent the check bit sequence that first convolution coder in CTC encoder generates, sub-block Y
2with sub-block W
2represent the check bit sequence that second convolution coder in CTC encoder generates.
2, in sub-block, interweave
Particularly, use the identical algorithm that interweaves in above-mentioned 6 sub-blocks, to interweave independently respectively.IEEE 802.16e standard adopts the algorithm that interweaves shown in following formula (1):
Wherein, the parameter of the algorithm that interweaves in sub-block shown in m and J represent respectively, these parameters can be determined according to the relevant parameter table providing in IEEE 802.16e, not repeat one by one here.T
krepresent temporary OPADD.If T
k>=N, abandons this T
k.Here information bit/2 in N=encoding block, k=0,1,2 ..., N-1.In IEEE 802.16e, described the concrete steps of utilizing the above-mentioned algorithm that interweaves to interweave in each sub-block, at this, also repeated no more.
3, bit in groups
Particularly, after interweaving in above-mentioned sub-block, sub-block A and sub-block B piece are directly shone upon, at sub-block Y
1with sub-block Y
2carry out interweaving between sub-block, and at sub-block W
1with sub-block W
2carry out interweaving between sub-block.Concrete interleaving process as shown in Figure 1.
Below listed some relevant lists of references, incorporated them into by reference in this, as done in this manual detailed description.
The IEEE P802.16e/D12 of in October, 2005 issue: " Draft IEEE Standardfor Local and Metropolitan area Networks-Part 16:Air Interfacefor Fixed and Mobile Broadband Wireless Access Systems-Amendment for Physical and Medium Access Control Layers forCombined Fixed and Mobile Operation in Licensed Bands ".
Summary of the invention
The invention provides a kind of channel interleaving method and channel interleaver, wherein take full advantage of the symmetry of the output bit of channel encoder, with more effectively by burst error discretization.
According to a first aspect of the invention, provide a kind of channel interleaving method.This channel interleaving method can comprise: receive N the first verification sub-block and N the second verification sub-block from encoder, wherein, N is more than or equal to 1 integer, the first checking data that described the first verification sub-block comprises payload data, the second checking data that described the second verification sub-block comprises payload data; Each the first verification sub-block and corresponding the second verification sub-block are divided into respectively to multiple data cells, wherein, each data cell comprises M bit, a described M bit has different reliability steps, M>=2 and M are the integer that can divide exactly a bit number in modulation symbol, and suppose that described different reliability step uses respectively R from high to low
0, R
1..., R
i..., R
m-1represent R
0>=R
1>=...>=R
i>=...,>=R
m-1, i=0,1 ..., M-1; And the position in this data cell exchanges to the each bit in the each data cell in each the first verification sub-block, making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in corresponding the second verification sub-block, be R
m-1-ithe position of bit.
According to a second aspect of the invention, provide a kind of channel interleaver.This channel interleaver can comprise receiver module and sub-block Nepit location swap module.
Described receiver module is for receiving N the first verification sub-block and N the second verification sub-block from encoder, wherein, N is more than or equal to 1 integer, the first checking data that described the first verification sub-block comprises payload data, the second checking data that described the second verification sub-block comprises payload data.
Described sub-block Nepit location swap module is for being divided into respectively multiple data cells by each the first verification sub-block and corresponding the second verification sub-block, wherein, each data cell comprises M bit, a described M bit has different reliability steps, M>=2 and M are the integer that can divide exactly a bit number in modulation symbol, and suppose that described different reliability step is expressed as R from high to low
0, R
1..., R
i..., R
m-1,, R
0>=R
1>=...>=R
i>=...,>=R
m-1, i=0,1 ..., M-1; And the position in this data cell exchanges for the each bit in each data cell of each the first verification sub-block, making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in corresponding the second verification sub-block, be R
m-1-ithe position of bit.
Accompanying drawing explanation
Below with reference to the accompanying drawings illustrate embodiments of the invention, can understand more easily above and other objects, features and advantages of the present invention.Parts in accompanying drawing are not proportional draftings, and just for principle of the present invention is shown.In the accompanying drawings, same or similar technical characterictic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 is the schematic diagram that a kind of channel interleaving method of prior art is shown;
Fig. 2 illustrates the planisphere of 16QAM (quadrature amplitude modulation);
Fig. 3 illustrates the planisphere of 64QAM (quadrature amplitude modulation);
Fig. 4 is the flow chart that channel interleaving method according to an embodiment of the invention is shown;
Fig. 5 is the schematic diagram illustrating according to the channel interleaving sequence for 16QAM and 64QAM of some embodiments of the present invention to Fig. 8;
Fig. 9 is the flow chart that channel interleaving method according to an embodiment of the invention is shown;
Figure 10 and Figure 11 are respectively the schematic diagrames illustrating according to the channel interleaving sequence for 16QAM and 64QAM of some embodiments of the present invention;
Figure 12 is the flow chart that channel interleaving method according to an embodiment of the invention is shown;
Figure 13 and Figure 14 are illustrated in respectively in the situation of using CTC encoders, according to the schematic diagram of the channel interleaving sequence for 16QAM and 64QAM of some embodiments of the present invention; And
Figure 15 and Figure 16 are the schematic block diagram illustrating respectively according to the structure of the channel interleaver of some embodiments of the present invention.
Embodiment
Embodiments of the invention are described with reference to the accompanying drawings.The element of describing in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with element and feature shown in one or more other accompanying drawing or execution mode.It should be noted that for purposes of clarity, in accompanying drawing and explanation, omitted expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and processing.
For example, in some modulation system (the bit mapping modulation system with different reliably protectings, comprises star 8QAM, high-order QAM etc.), in each modulation symbol, the reliability of each bit is different.Fig. 2 and Fig. 3 exemplarily show respectively the planisphere of these two kinds of modulation systems of 16QAM and 64QAM.As shown in Figure 2, in 16QAM, each modulation symbol comprises 4 bit: i
1g
1i
2g
2.Under this planisphere, 4 bits can be divided into two kinds of reliability steps, wherein, and i
1, g
1for high reliability bit; i
2, g
2for low reliability bits.As shown in Figure 3, in 64QAM, each modulation symbol comprises 6 bit: i
1q
1i
2q
2i
3g
3.Under this planisphere, 6 bits can be divided into 3 kinds of reliability steps, wherein, and i
1, g
1for high reliability bit, i
2, g
2for middle reliability bits, i
3, g
3for low reliability bits.
As previously mentioned, adopting channel interleaver is for the unexpected error of average channel more effectively, thereby obtains good diversity gain.When considering frequency domain mapping, adjacent bit should be arranged on discrete subcarrier, to make full use of frequency diversity gain; And when considering symbol constellation mapping, adjacent bit should be arranged on bits different in symbol, to make full use of planisphere diversity gain.
According to the channel interleaving method of the embodiment of the present invention and channel interleaver, take full advantage of the symmetry of the output bit of encoder.
Fig. 4 exemplarily shows the flow chart of channel interleaving method according to an embodiment of the invention.Fig. 5 is the schematic diagram exemplarily showing according to an embodiment of the invention for the channel interleaving sequence of 16QAM or 64QAM to Fig. 8.Described channel interleaving method is described with reference to the accompanying drawings.
As shown in Figure 4, in step 401, receive the first verification sub-block and the second verification sub-block from encoder.
In an embodiment of the present invention, described encoder can comprise N verification maker, and N is integer, and N >=1.Be that described encoder can be exported N the first verification sub-block Y
1..., Y
j..., Y
nwith N the second verification sub-block W
1..., W
j..., W
n,, 1≤j≤N, wherein Y
jand W
jthe output of j verification maker.For example, the example of utilizing general Turbo code encoder has been shown in Fig. 5 or Fig. 6, general Turbo code encoder comprises a verification maker, output the first verification sub-block Y
1with the second verification sub-block W
1.And for example, the example of utilizing CTC encoders has been shown in Fig. 7 or Fig. 8, CTC encoders comprises two verification makers, exports respectively the first verification sub-block Y
1with the second verification sub-block W
1and the first verification sub-block Y
2with the second verification sub-block W
2.
The checking data that these verification sub-blocks comprise payload data.
Described encoder can be general Turbo code encoder, can also be CTC encoders, or other output bit has symmetric channel encoder.For example, in the example that Fig. 5 and Fig. 6 provide, the output sequence of general Turbo code encoder is interweaved, and in the example that Fig. 7 and Fig. 8 provide, the output sequence to CTC encoders interweaves.Should be understood that these are only exemplary, should not be considered as the present invention to be limited to this.
In step 403, each the first verification sub-block and corresponding the second verification sub-block are divided into respectively to multiple data cells.
Wherein, each data cell comprises the M bit with different reliability steps.Here, the length M of each data cell is the integer that can divide exactly a bit number in modulation symbol, and M >=2.For example, in the example for 16QAM shown in Fig. 5 and Fig. 7, M is the half of modulation symbol length 4, i.e. M=2.And for example, in the example for 64QAM shown in Fig. 6 and Fig. 8, M is the half of modulation symbol length 6, i.e. M=3.
Suppose that the different reliability step of the M bit in each data cell uses respectively R from high to low
0, R
1..., R
i..., R
m-1represent R
0>=R
1>=...>=R
i>=...,>=R
m-1, i=0,1 ..., M-1.For example, in the example for 16QAM shown in Fig. 5 and Fig. 7, each data cell comprises two bits, and one is high reliability bit, and another is low reliability bits.And for example, in the example for 64QAM shown in Fig. 6 and Fig. 8, each data cell comprises three bits, and one is high reliability bit, and one is medium reliability bits, and remaining one be low reliability bits.
In step 405, to each the first verification sub-block Y
j(or each the second verification sub-block W
j) in each data cell in the position of each bit in this data cell exchange, making reliability step in this data cell after exchange is R
ithe position of bit corresponding to corresponding the second verification sub-block W
j(or corresponding the first verification sub-block Y
j) in corresponding data unit in reliability step be R
m-1-ithe position of bit.
For example, in the example for 16QAM shown in Fig. 5 and Fig. 7, the high reliability bit of each data cell of sub-block Y1 or sub-block W1 and low reliability bits transposition.And for example, in the example for 64QAM shown in Fig. 6 and Fig. 8, the high reliability bit in each data cell of sub-block Y1 or sub-block W1 and low reliability bits transposition, and medium reliability bits invariant position.
After above-mentioned interleaving process, can make high reliability bit in verification sequence and the distribution discretization of low reliability bits, thereby improve the ability of anti-sudden channel error.
Fig. 9 exemplarily shows the flow chart of channel interleaving method according to another embodiment of the present invention.Figure 10 and Figure 11 are respectively the schematic diagrames exemplarily showing according to an embodiment of the invention for the channel interleaving sequence of 16QAM and 64QAM.
Be with difference embodiment illustrated in fig. 4, the embodiment shown in Fig. 9 comprises the step 902 that interweaves in a sub-block.In step 902, respectively received each sub-block is carried out interweaving in sub-block independently.In described sub-block, interweave and can adopt any applicable algorithm that interweaves to carry out, for example, can adopt the algorithm that interweaves in IEEE 802.16e or other standards.Here repeat no more.Other steps 901,903 with 905 to the step 401 shown in Fig. 4,403 similar with 405, also repeat no more here.
In channel interleaving schematic diagram shown in Figure 10 and Figure 11, comprised in sub-block and having interweaved respectively, identical with shown in Fig. 5 and Fig. 6 of other sequence variation.
In certain embodiments, can also carry out channel interleaving to the payload sub-block receiving.Payload sub-block comprises payload data.For example, the payload sub-block A of general Turbo code encoder output has been shown in Fig. 5, Fig. 6, Figure 10 and Figure 11, in the example shown in Figure 10 and Figure 11, payload sub-block A has been made to interleaving treatment in sub-block (method and step 902 are similar).
Two payload sub-block A and the B of CTC encoders output and for example, have been shown in Fig. 7 or Fig. 8.In the example shown, two payload sub-block A and B have also been carried out to the position bit in sub-block and exchanged (method and step 903 and 905 similar).In this sub-block, location swap comprises the following steps: the first payload sub-block A and the second payload sub-block B are divided into respectively to multiple data cells, and each data cell comprises M bit (being similar to step 403 or 903); Equally, the different reliability step of supposing the M bit in each data cell is used respectively R from high to low
0, R
1..., R
i..., R
m-1represent R
0>=R
1>=...>=R
i>=...,>=R
m-1, i=0,1 ..., M-1, the position to the each bit in the each data cell in payload sub-block B in this data cell exchanges (being similar to step 405 or 905), and making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in payload sub-block A, be R
m-1-ithe position of bit.
In another example, after payload sub-block A and B are divided into respectively to multiple data cells, position to the each bit in the each data cell in payload sub-block A (rather than sub-block B) in this data cell exchanges, and making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in payload sub-block B, be R
m-1-ithe position of bit.
In the example of Fig. 4-6 and Fig. 9-11, the bit position exchange in sub-block is at each the first verification sub-block Y
i(i=1 ..., N) in carry out.Those of ordinary skill in the art should be understood that the bit position exchange in sub-block can also be at each the second verification sub-block W
i(i=1 ..., N) in carry out, as shown in Fig. 7, Fig. 8, Figure 13 and Figure 14.
In the embodiment of Fig. 9, the concept of data cell is identical with aforementioned each embodiment, and the length M of each data cell is the integer that can divide exactly a bit number in modulation symbol, and M >=2.For example, in the example for 16QAM shown in Fig. 5, Fig. 7, Figure 10, M is the half of modulation symbol length 4, i.e. M=2.And for example, in the example for 64QAM shown in Fig. 6, Fig. 8, Figure 12, M is the half of modulation symbol length 6, i.e. M=3.
In addition, the quantity of payload sub-block is also not limited to 1 or 2, but changes according to different encoders.For example, according to the different structure of encoder, can export N the first verification sub-block and N the second verification sub-block, N is integer, and N >=1.
In certain embodiments, can by received payload partition, be only data cell (being similar to step 403 or 903) and carry out sub-block Nepit location swap (being similar to step 405 or 905), and verification sub-block not carried out to any processing.For example, the in the situation that of N=2, can be only received two payload sub-block A and B be divided into data cell and the bit position of carrying out in sub-block exchanges, and verification sub-block Y1, Y2, W1 and W2 not be carried out to any processing.
Figure 12 exemplarily shows the flow chart of channel interleaving method according to another embodiment of the present invention.
Be with Fig. 4 or difference embodiment illustrated in fig. 9, the embodiment shown in Figure 12 comprises the sub-interblock step 1207 that interweaves.In step 1207, take the group of data cell as unit sequence at two verification sub-block Y
1and Y
2between carry out interweaving between sub-block, and correspondingly take the group of data cell as unit sequence at two verification sub-block W
1and W
2between carry out interweaving between sub-block.The group of described data cell comprises X the data cell of (or discontinuous) continuously, and X is integer and X >=1.
Sub-block W
1and W
2between interleaving mode and sub-block Y
1and Y
2between interleaving mode should there is symmetry.For example, in one example, after interweaving between sub-block, verification sub-block Y
2every group of data cell follow closely at verification sub-block Y
1corresponding data sheet tuple after, and correspondingly, verification sub-block W
2every group of data cell follow closely at verification sub-block W
1corresponding data sheet tuple after.In another example, after interweaving between sub-block, verification sub-block Y
1every group of data cell follow closely at verification sub-block Y
2corresponding data sheet tuple after; And correspondingly, verification sub-block W
1every group of data cell follow closely at verification sub-block W
2corresponding data sheet tuple after.Certainly, the mode interweaving is not limited to the above-mentioned method of enumerating, and those of ordinary skill in the art can instruction according to the present invention modify to it and change, and within these all should be covered by protection scope of the present invention.
In another example, can also adopt identical method, take the group of described data cell as unit sequence, between payload sub-block A and payload sub-block B, carry out interweaving between sub-block, repeat no more here.
In the example depicted in fig. 12, in sub-block, interweave step 1202 between receiving step 1201 and step 1203.Should be appreciated that, this is only exemplary, the invention is not restricted to this.In another example, the step 1202 also can interweave between sub-block (not shown) after step 1207 that interweaves in sub-block.In another example, sub-block Nepit location swap step 1203 also can be positioned at (not shown) after the step 1207 that interweaves between sub-block.In other words, the method flow in embodiments of the invention is not limited to shown or described step and/or order.Those of ordinary skill in the art can instruction according to the present invention modifies, adds, deletes these steps and/or change its order, and within these all should be covered by protection scope of the present invention.
Figure 13 and Figure 14 exemplarily show respectively using CTC encoders in the situation that, according to an embodiment of the invention for the channel interleaving sequence of 16QAM and 64QAM.
As shown in figure 13, in the situation that using 16QAM modulation, first, receive payload sub-block A and B, the first verification sub-block Y from encoder
1and Y
2and the second verification sub-block W
1and W
2.Alternatively, can be respectively at each sub-block A, B, Y
1, Y
2, W
1and W
2inside carry out independently interweaving in sub-block (with step 902 and 1202 similar, not repeating them here).Then, by each sub-block A, B, Y
1, Y
2, W
1and W
2be divided into respectively multiple data cells.In the example depicted in fig. 13, each data cell comprises 2 bits.Certainly, those of ordinary skill in the art can select to comprise the data cell of other bit numbers.
Then, to sub-block A, sub-block W
1and sub-block W
2carry out sub-block Nepit location swap (with step 405,905,1205 similar, not repeating them here), make sub-block A, sub-block W
1and sub-block W
2in each data cell in the position and corresponding sub-block B, sub-block Y of low reliability bits (high reliability bit)
1and sub-block Y
2in corresponding data cell in the position of high reliability bit (low reliability bits) corresponding.In another example, alternatively, can be to sub-block B, sub-block Y
1and sub-block Y
2carry out sub-block Nepit location swap, make sub-block B, sub-block Y
1and sub-block Y
2in each data cell in the position and corresponding sub-block A, sub-block W of low reliability bits (high reliability bit)
1and sub-block W
2in corresponding data cell in the position of high reliability bit (low reliability bits) corresponding.
Finally, take the group of data cell as unit sequence between sub-block A and B, at sub-block W
1with W
2between and at sub-block Y
1with Y
2between carry out interweaving between sub-block.The group of described data cell comprises X data cell (X >=1).In the example depicted in fig. 13, X=1.
In the example depicted in fig. 13, after interweaving between sub-block, every group of data cell of sub-block B follows closely after the corresponding data sheet tuple of sub-block A.In another example, after interweaving between sub-block, every group of data cell of sub-block A can follow closely after the corresponding data sheet tuple of sub-block B.
In the example depicted in fig. 13, after interweaving between sub-block, verification sub-block Y
2every group of data cell follow closely at verification sub-block Y
1corresponding data sheet tuple after, and correspondingly, verification sub-block W
2every group of data cell follow closely at verification sub-block W
1corresponding data sheet tuple after.And in another example, after interweaving between sub-block, verification sub-block Y
1every group of data cell can follow closely at verification sub-block Y
2corresponding data sheet tuple after; And correspondingly, verification sub-block W
1every group of data cell can follow closely at verification sub-block W
2corresponding data sheet tuple after.
Sub-block W
1and W
2between interleaving mode and sub-block Y
1and Y
2between interleaving mode should there is symmetry.In the example depicted in fig. 13, after interweaving between above-mentioned sub-block, if Y
1in certain bit in modulation, time be high reliability bit, W
1the bit of middle corresponding position is low reliability bits when modulation; If Y
1in certain bit in modulation, time be low reliability bits, W
1the bit of middle corresponding position is high reliability bit when modulation.
Certainly, the mode interweaving between sub-block is not limited to the above-mentioned method of enumerating, and those of ordinary skill in the art can instruction according to the present invention modify to it and change, and within these all should be covered by protection scope of the present invention.
As shown in figure 14, in the situation that using 64QAM modulation, first, receive payload sub-block A and B, the first verification sub-block Y from encoder
1and Y
2and the second verification sub-block W
1and W
2.Alternatively, can be respectively at each sub-block A, B, Y
1, Y
2, W
1and W
2inside carry out independently interweaving in sub-block (with step 902 and 1202 similar, not repeating them here).Then, by each sub-block A, B, Y
1, Y
2, W
1and W
2be divided into respectively multiple data cells.In the example depicted in fig. 14, each data cell comprises 3 bits.Certainly, those of ordinary skill in the art can select to comprise the data cell of other bit numbers.
Then, to sub-block A, sub-block W
1and sub-block W
2carry out sub-block Nepit location swap (with step 405,905,1205 similar, not repeating them here), make sub-block A, sub-block W
1and sub-block W
2in each data cell in the position and corresponding sub-block B, sub-block Y of low reliability bits (high reliability bit)
1and sub-block Y
2in corresponding data cell in the position of high reliability bit (low reliability bits) corresponding.In another example, alternatively, can be to sub-block B, sub-block Y
1and sub-block Y
2carry out sub-block Nepit location swap, make sub-block B, sub-block Y
1and sub-block Y
2in each data cell in the position and corresponding sub-block A, sub-block W of low reliability bits (high reliability bit)
1and sub-block W
2in corresponding data cell in the position of high reliability bit (low reliability bits) corresponding.
Finally, take the group of data cell as unit sequence between sub-block A and B, at sub-block W
1with W
2between and at sub-block Y
1with Y
2between carry out interweaving between sub-block.The group of described data cell comprises X data cell (X >=1).In the example depicted in fig. 14, X=1.
In the example depicted in fig. 14, after interweaving between sub-block, every group of data cell of sub-block B follows closely after the corresponding data sheet tuple of sub-block A.In another example, after interweaving between sub-block, every group of data cell of sub-block A can follow closely after the corresponding data sheet tuple of sub-block B.
In the example depicted in fig. 14, after interweaving between sub-block, verification sub-block Y
2every group of data cell follow closely at verification sub-block Y
1corresponding data sheet tuple after, and correspondingly, verification sub-block W
2every group of data cell follow closely at verification sub-block W
1corresponding data sheet tuple after.And in another example, after interweaving between sub-block, verification sub-block Y
1every group of data cell can follow closely at verification sub-block Y
2corresponding data sheet tuple after; And correspondingly, verification sub-block W
1every group of data cell can follow closely at verification sub-block W
2corresponding data sheet tuple after.
As mentioned above, sub-block W
1and W
2between interleaving mode and sub-block Y
1and Y
2between interleaving mode should there is symmetry.In the example depicted in fig. 14, after interweaving between sub-block, if Y
1in certain bit in modulation, time be high reliability bit, W
1the bit of middle corresponding position is low reliability bits when modulation; If Y
1in certain bit in modulation, time be medium reliability bits, W
1the bit of middle corresponding position is medium reliability bits when modulation; If Y
1in certain bit in modulation, time be low reliability bits, W
1the bit of middle corresponding position is low reliability bits when modulation.
Certainly, the mode interweaving between sub-block is not limited to the above-mentioned method of enumerating, and those of ordinary skill in the art can instruction according to the present invention modify to it and change, and within these all should be covered by protection scope of the present invention.
Figure 15 shows channel interleaver 1500 according to an embodiment of the invention.This channel interleaver 1500 comprises receiver module 1501 and sub-block Nepit location swap module 1502.Wherein, receiver module 1501 is arranged to N the first verification sub-block and N the second verification sub-block that receive from encoder, wherein, N is more than or equal to 1 integer, the first checking data that described the first verification sub-block comprises payload data, the second checking data that described the second verification sub-block comprises payload data.
Sub-block Nepit location swap module 1502 is arranged to each the first verification sub-block receiving and corresponding the second verification sub-block is divided into respectively to multiple data cells.Wherein, each data cell comprises the M bit with different reliability steps.The different reliability step of supposing described M bit is expressed as R from high to low
0, R
1..., R
i..., R
m-1, R
0>=R
1>=...>=R
i>=...,>=R
m-1, i=0,1 ..., M-1.Sub-block Nepit location swap module 1502 is also arranged to the position in this data cell to the each bit in the each data cell in each the first verification sub-block and exchanges, and making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in corresponding the second verification sub-block, be R
m-1-ithe position of bit.
Alternatively, receiver module 1501 also can be arranged to N the payload sub-block receiving through encoder encodes.And when N equals 2 (for example, in the situation that using CTC encoders), if 2 payload sub-blocks that receive are respectively payload sub-block A and payload sub-block B, described sub-block Nepit location swap module 1502 also has different reliability step R for described payload sub-block A and B are divided into respectively to comprise respectively
0, R
1..., R
i..., R
m-1multiple data cells of M bit, and the position in this data cell exchanges to the each bit in the each data cell in payload sub-block A or B, making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in payload sub-block B or A, be R
m-1-ithe position of bit.
Alternatively, channel interleaver 1500 also comprises interleaving block 1503 between sub-block.When N equals 2 (for example, in the situation that using CTC encoders), to establish 2 received the first verification sub-blocks and with Y1 and Y2, represent respectively, 2 the second verification sub-blocks that receive represent with W1 and W2 respectively.Between sub-block, interleaving block 1503 can be arranged to take one or more data cells as unit sequence and carry out interweaving between sub-block between two verification sub-block Y1 and Y2, and take one or more data cells as unit sequence, between two verification sub-block W1 and W2, carries out interweaving between sub-block symmetrically.Alternatively, between sub-block, interleaving block 1503 also can be used for take one or more data cells as unit sequence between sub-block, interweaving carrying out between payload sub-block A and B.
Figure 16 shows channel interleaver 1600 according to another embodiment of the present invention.As shown in figure 16, channel interleaver 1600 comprises interleaving block 1603 between receiver module 1601, sub-block Nepit location swap module 1602 and sub-block.These modules are identical with the respective modules function shown in Figure 15.Channel interleaver 1600 also comprises interleaving block 1604 in sub-block.In this sub-block, interleaving block 1604 carries out interweaving in sub-block for each sub-block of each verification sub-block to received and/or payload sub-block.
In Figure 16, in sub-block, interleaving block 1604 is arranged between receiver module 1601 and sub-block Nepit location swap module 1602.In another example, interleaving block 1604 also can be arranged at other positions in sub-block, for example, between sub-block after interleaving block 1603 (not shown).In another example, sub-block Nepit location swap module 1602 can be positioned between sub-block after interleaving block 1603 (not shown).In other words, the device in above-described embodiment is not limited to shown or described structure.Those of ordinary skill in the art can instruction according to the present invention modify, add and/or delete these structures, and within these all should be covered by protection scope of the present invention.
In with reference to Figure 15 and 16 described embodiment, N, M, R
0, R
1..., R
i..., R
m-1etc. interweaving between parameter and data cell, sub-block, in sub-block, interweave, the concept such as bit position exchange is all identical with the corresponding concepts in preceding method embodiment, no longer repeat here.
Utilization is according to the channel interleaving method of the embodiment of the present invention or channel interleaver, can make high reliability bit in verification sequence and/or payload sequence and the distribution discretization of low reliability bits, thereby improves the ability of anti-sudden channel error.
According to the channel interleaving method of the embodiment of the present invention or channel interleaver, can be applicable to have the bit mapping modulation system of different reliably protectings, for example 8 rank Star-QAMs or high-order orthogonal amplitude modulation(PAM) etc.Wherein, described high-order orthogonal amplitude modulation(PAM) is preferably the modulation systems such as 2K rank quadrature amplitude modulation, and wherein K is preferably more than or equals 4 integer.Those of ordinary skill in the art should be understood that the modulation system exemplifying at this is exemplary, and the present invention is not limited thereto.
According to the channel interleaving method of the embodiment of the present invention or channel interleaver, can be applicable to export bit and there is symmetric channel encoder, for example general Turbo code encoder, CTC encoders or other encoders.Those of ordinary skill in the art should be understood that the encoder exemplifying at this is exemplary, and the present invention is not limited thereto.
In this manual, the statements such as " first ", " second " and " N " are for described feature is distinguished on word, clearly to describe the present invention.Therefore, should not be regarded as and there is any determinate implication.For example, " the first verification sub-block " do not refer in particular to " the Y shown in accompanying drawing
1" or " Y
2" sub-block, in other statement, it also can represent " the W shown in accompanying drawing
1" or " W
2" sub-block etc." the first payload sub-block " do not refer in particular to " A " sub-block shown in accompanying drawing, and in other statement, it also can represent " B " sub-block shown in accompanying drawing.
In said apparatus, each building block or module can be configured by the mode of software, hardware or its combination.Configure spendable concrete means or mode and be well known to those skilled in the art, do not repeat them here.
Easily understand, the equipment of the embodiment that comprises the invention described above or system also should be considered to fall within the scope of protection of the present invention.
The present invention also proposes a kind of program product that stores the instruction code that machine readable gets.When described instruction code is read and carried out by machine, can carry out above-mentioned according to the channel interleaving method of the embodiment of the present invention.
Correspondingly, for carrying the storage medium of the above-mentioned program product that stores the instruction code that machine readable gets, be also included within of the present invention open.Described storage medium includes but not limited to floppy disk, CD, magneto optical disk, storage card, memory stick etc.
In the above in the description of the specific embodiment of the invention, for a kind of execution mode, describe and/or the feature that illustrates can be used in same or similar mode in one or more other execution mode, combined with the feature in other execution mode, or substitute the feature in other execution mode.
Should emphasize, term " comprises/comprises " existence that refers to feature, key element, step or assembly while using herein, but does not get rid of the existence of one or more further feature, key element, step or assembly or add.
In addition, the time sequencing of describing during method of the present invention is not limited to is to specifications carried out, also can be according to other time sequencing ground, carry out concurrently or independently.The execution sequence of the method for therefore, describing in this specification is not construed as limiting technical scope of the present invention.
Although the present invention is disclosed by the description to specific embodiments of the invention above, but, should be appreciated that, those skilled in the art can design various modifications of the present invention, improvement or equivalent in the spirit and scope of claims.These modifications, improvement or equivalent also should be believed to comprise in protection scope of the present invention.
Claims (16)
1. a channel interleaving method, comprising:
Reception is from N the first verification sub-block Y of encoder
1..., Y
j..., Y
nwith N the second verification sub-block W
1..., W
j..., W
n, wherein, described encoder comprises N verification maker, N is more than or equal to 1 integer, 1≤j≤N, the first verification sub-block Y
jwith the second verification sub-block W
jthe output of j verification maker, the checking data that described the first verification sub-block and the second verification sub-block comprise payload data;
Each the first verification sub-block and corresponding the second verification sub-block are divided into respectively to multiple data cells, wherein, each data cell comprises M bit, a described M bit has different reliability steps, M>=2 and M are the integer that can divide exactly a bit number in modulation symbol, and suppose that described different reliability step uses respectively R from high to low
0, R
1..., R
i..., R
m-1represent R
0>=R
1>=...>=R
i>=...,>=R
m-1, i=0,1 ..., M-1; And
To each the first verification sub-block Y
jin each data cell in the position of each bit in this data cell exchange, making reliability step in this data cell after exchange is R
ithe position of bit corresponding to corresponding the second verification sub-block W
jin corresponding data unit in reliability step be R
m-1-ithe position of bit.
2. channel interleaving method as claimed in claim 1, also comprises:
Reception is from N payload sub-block of described encoder, and described N payload sub-block comprises respectively described payload data.
3. channel interleaving method as claimed in claim 2, wherein, when N equals 2, establishes 2 received payload sub-blocks and is respectively the first payload sub-block and the second payload sub-block, and described method also comprises:
Described the first payload sub-block and described the second payload sub-block are divided into respectively to multiple data cells, and wherein, each data cell comprises M bit, and a described M bit has different reliability step R
0, R
1..., R
i..., R
m-1, and
Position to the each bit in the each data cell in described the first payload sub-block in this data cell exchanges, and making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in the second payload sub-block, be R
m-1-ithe position of bit.
4. channel interleaving method as claimed in claim 1, wherein, when N equals 2, establishes 2 received the first verification sub-blocks and uses respectively Y
1and Y
2represent, 2 the second verification sub-blocks that receive are used respectively W
1and W
2represent, described method also comprises:
Take the group of data cell as unit sequence at two the first verification sub-block Y
1and Y
2between carry out interweaving between sub-block, wherein, every group comprises X data cell, X is more than or equal to 1 integer; And
Take the group of data cell as unit sequence at two the second verification sub-block W
1and W
2between carry out interweaving between sub-block, wherein, every group comprises X data cell.
5. the channel interleaving method as described in claim 3 or 4, also comprises:
Take the group of data cell as unit sequence, between described the first payload sub-block and described the second payload sub-block, carry out interweaving between sub-block, wherein, every group comprises X data cell, and X is more than or equal to 1 integer.
6. the channel interleaving method as described in claim 1 or 2 or 3, wherein, described encoder is general Turbo code encoder or CTC encoders.
7. the channel interleaving method as described in claim 1 or 2 or 3; wherein; described channel interleaving method is applied to the bit mapping modulation system with different reliably protectings, and the bit mapping modulation system of described different reliably protectings comprises 8 rank Star-QAMs or 2
krank quadrature amplitude modulation, K is more than or equal to 4 positive integer.
8. channel interleaving method as claimed in claim 1 or 2, wherein, after receiving described N the first verification sub-block, described N the second verification sub-block and/or described N payload sub-block, also comprises:
In each sub-block in described N the first verification sub-block, described N the second verification sub-block and/or described N payload sub-block, carry out interweaving in sub-block respectively.
9. a channel interleaver, comprising:
Receiver module, for receiving N the first verification sub-block Y from encoder
1..., Y
j..., Y
nwith N the second verification sub-block W
1..., W
j..., W
n, wherein, described encoder comprises N verification maker, N is more than or equal to 1 integer, 1≤j≤N, the first verification sub-block Y
jwith the second verification sub-block W
jthe output of j verification maker, the checking data that described the first verification sub-block and described the second verification sub-block comprise payload data; And
Sub-block Nepit location swap module, for:
Each the first verification sub-block and corresponding the second verification sub-block are divided into respectively to multiple data cells, wherein, each data cell comprises M bit, a described M bit has different reliability steps, M>=2 and M are the integer that can divide exactly a bit number in modulation symbol, and suppose that described different reliability step is expressed as R from high to low
0, R
1..., R
i..., R
m-1, R
0>=R
1>=...>=R
i>=...,>=R
m-1, i=0,1 ..., M-1; And
To each the first verification sub-block Y
jin each data cell in the position of each bit in this data cell exchange, making reliability step in this data cell after exchange is R
ithe position of bit corresponding to corresponding the second verification sub-block W
jin corresponding data unit in reliability step be R
m-1-ithe position of bit.
10. channel interleaver as claimed in claim 9, wherein, described receiver module is also for receiving N the payload sub-block from described encoder, and described N payload sub-block comprises respectively described payload data.
11. channel interleavers as claimed in claim 10, wherein, when N equals 2, establish 2 received payload sub-blocks and are respectively the first payload sub-block and the second payload sub-block, described sub-block Nepit location swap module also for:
Described the first payload sub-block and described the second payload sub-block are divided into respectively to multiple data cells, and wherein, each data cell comprises M bit, and a described M bit has described different reliability step R
0, R
1..., R
i..., R
m-1, and
Position to the each bit in the each data cell in described the first payload sub-block in this data cell exchanges, and making reliability step in this data cell after exchange is R
ithe position of bit corresponding to the reliability step in the corresponding data unit in described the second payload sub-block, be R
m-1-ithe position of bit.
12. channel interleavers as claimed in claim 9, wherein, described channel interleaver also comprises interleaving block between sub-block, when N equals 2, establishes 2 received the first verification sub-blocks and uses respectively Y
1and Y
2represent, 2 the second verification sub-blocks that receive are used respectively W
1and W
2represent, between described sub-block, interleaving block is used for:
Take the group of data cell as unit sequence at two the first verification sub-block Y
1and Y
2between carry out interweaving between sub-block, wherein, every group comprises X data cell, X is more than or equal to 1 integer; And
Take the group of data cell as unit sequence at two the second verification sub-block W
1and W
2between carry out interweaving between sub-block, wherein, every group comprises X data cell.
13. channel interleavers as described in claim 11 or 12, wherein, between described sub-block interleaving block also for:
Take the group of data cell as unit sequence, between described the first payload sub-block and described the second payload sub-block, carry out interweaving between sub-block, wherein, every group comprises X data cell, and X is more than or equal to 1 integer.
14. channel interleavers as described in claim 9 or 10, also comprise interleaving block in sub-block, wherein, in described sub-block, interleaving block is used for: the each sub-block to received described N the first verification sub-block, described N the second verification sub-block and/or described N payload sub-block carries out interweaving in sub-block.
15. channel interleavers as described in claim 9 or 10 or 11, wherein, described encoder is general Turbo code encoder or CTC encoders.
16. channel interleavers as described in claim 9 or 10 or 11, wherein, described channel interleaver is applied to the bit mapping modulation system with different reliably protectings, and the bit mapping modulation system of described different reliably protectings comprises 8 rank Star-QAMs or 2
krank quadrature amplitude modulation, wherein K is more than or equal to 4 integer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2009/070937 WO2010105445A1 (en) | 2009-03-20 | 2009-03-20 | Channel interleaving method and channel interleaver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102067640A CN102067640A (en) | 2011-05-18 |
| CN102067640B true CN102067640B (en) | 2014-04-30 |
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| WO (1) | WO2010105445A1 (en) |
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| CN102468914B (en) * | 2010-11-16 | 2015-01-21 | 华为技术有限公司 | Pre-coding method and device |
| CN104811266B (en) * | 2014-01-29 | 2018-01-23 | 上海数字电视国家工程研究中心有限公司 | Bit Interleave, de-interweaving method and corresponding emitter, receiver |
| CN104868970B (en) * | 2014-02-20 | 2019-11-26 | 上海数字电视国家工程研究中心有限公司 | The intertexture mapping method and deinterleaving de-mapping method of LDPC code word |
| CN104901773A (en) * | 2014-03-06 | 2015-09-09 | 上海数字电视国家工程研究中心有限公司 | Interleaving and mapping method and de-interleaving and de-mapping method for LDPC (Low Density Parity Check) code words |
| CN104901772A (en) * | 2014-03-06 | 2015-09-09 | 上海数字电视国家工程研究中心有限公司 | Interleaving and mapping method and de-interleaving and de-mapping method for LDPC code word |
| CN104901774B (en) * | 2014-03-06 | 2019-12-13 | 上海数字电视国家工程研究中心有限公司 | interleaving mapping method and de-interleaving de-mapping method of LDPC code words |
| CN104935397A (en) * | 2014-03-20 | 2015-09-23 | 上海数字电视国家工程研究中心有限公司 | Interleaved mapping method and de-interleaving de-mapping method for LDPC codeword |
| CN105376023A (en) * | 2014-08-29 | 2016-03-02 | 上海数字电视国家工程研究中心有限公司 | Interleaving and mapping method and de-interleaving and de-mapping method of LDPC code word |
| CN109412747A (en) * | 2017-08-15 | 2019-03-01 | 株式会社Ntt都科摩 | A kind of rate-matched deinterleaving method and device for polarization code |
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- 2009-03-20 WO PCT/CN2009/070937 patent/WO2010105445A1/en active Application Filing
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| WO2010105445A1 (en) | 2010-09-23 |
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