WO2010100674A1 - イコライザ回路およびそれを用いた試験装置 - Google Patents
イコライザ回路およびそれを用いた試験装置 Download PDFInfo
- Publication number
- WO2010100674A1 WO2010100674A1 PCT/JP2009/000988 JP2009000988W WO2010100674A1 WO 2010100674 A1 WO2010100674 A1 WO 2010100674A1 JP 2009000988 W JP2009000988 W JP 2009000988W WO 2010100674 A1 WO2010100674 A1 WO 2010100674A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- unit
- function
- waveform
- equalizer circuit
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03343—Arrangements at the transmitter end
Definitions
- the present invention relates to an equalizer circuit.
- Propagation loss When a single-ended or differential electrical signal is transmitted from a transmitting device (transmitter) to a receiving device (receiver) via a transmission line, waveform distortion due to transmission line loss (propagation loss) occurs. Propagation loss becomes more prominent as the length of the propagation line (propagation length) becomes longer, and generally acts on a signal as a low-pass filter approximately. Therefore, for example, when a rectangular wave signal is transmitted from the transmitter, a distorted waveform is observed at the receiving end of the receiver.
- the transmitter may be provided with an equalizer circuit that corrects the transmission waveform (also referred to as pre-emphasis or pre-distortion) so as to cancel waveform distortion due to propagation loss.
- an equalizer circuit that corrects the transmission waveform (also referred to as pre-emphasis or pre-distortion) so as to cancel waveform distortion due to propagation loss.
- pre-emphasis processing such as extracting a high frequency component of an original signal to be transmitted to generate an emphasis component and superimposing it on the original signal is performed.
- a discrete time equalizer that adds an emphasis component for each UI is effective.
- the equalizer can be implemented with a simple circuit if the UI of the bit string is constant.
- An automatic test apparatus for testing a semiconductor device includes a unit called a timing controller, and the timing of an edge of a signal applied to a device under test (DUT), that is, a UI, is set in real time.
- the function to change arbitrarily every time is realized.
- RTTC Real Time Timing Control
- the ATE may have a jitter injection function as disclosed in Patent Document 1, for example.
- the jitter injection function applies a signal including known jitter from the ATE to the DUT, and determines whether the DUT can receive the signal correctly. Jitter injection can also be realized by dynamically changing the delay applied to the edge of the signal in the same way as RTTC.
- the present invention has been made in such a situation, and one of exemplary purposes of an aspect thereof is to provide an equalizer corresponding to a UI that changes in real time.
- An embodiment of the present invention receives amplitude data A [N] indicating the amplitude level of an Nth signal (N is a non-negative integer) to be transmitted through a transmission line and timing data T [N] indicating a signal period.
- the present invention relates to an equalizer circuit for waveform shaping.
- the equalizer circuit adds M (M is a natural number) calculation units and the output data D 1 [N] to D M [N] of the M calculation units and amplitude data A [N] to equalize the amplitude.
- a first adder that generates data D [N].
- the output data D j [N] given by is calculated.
- the transmitter includes a pattern generator that generates amplitude data A [N] and timing data T [N], the above-described equalizer circuit, and amplitude data D [N] that is equalized by the equalizer circuit, and timing data T [N].
- a waveform shaping unit that performs retiming, and a driver that converts output data of the waveform shaping unit into a multilevel signal. According to this aspect, it is possible to perform preferable equalization even for waveform distortion of a transmission line having a time constant longer than the UI of transmission data, so that a complicated reception equalizer such as a decision feedback equalizer is unnecessary on the reception side. There is an advantage.
- the test apparatus includes a pattern generator that generates amplitude data A [N] and timing data T [N], a timing generator that receives timing data T [N], and generates an edge at a timing corresponding to the value.
- the above-described equalizer circuit, the waveform shaping unit that retimes the amplitude data D [N] equalized by the equalizer circuit at the edge generated by the timing generator, and the output data of the waveform shaping unit is converted into a multi-value signal And a driver.
- the RTTC function, the jitter injection function and equalizing can be made compatible, or the equalizing amount can be intentionally changed to improve the performance of the DUT. Can be inspected.
- FIG. 3A and 3B show the structure of the equalizer circuit which concerns on embodiment. It is an example of the time chart which shows the operation
- movement of the equalizer circuit of FIG. 3A and 3B are simulation waveform diagrams showing an output waveform when an ideal step waveform signal is propagated to a certain transmission line, and a waveform to be output from the equalizer circuit, respectively. It is a figure which shows a mode that a continuous data sequence is decomposed
- FIGS. 14A and 14B are block diagrams showing configurations of equalizer circuits according to sixth and seventh modifications, respectively.
- DESCRIPTION OF SYMBOLS 100 ... Interface circuit, 102 ... Transmission line, 1 ... Pattern generator, 2 ... Timing generator, 3 ... Waveform shaper, 4 ... Driver, 10 ... Equalizer circuit, ECU ... Calculation unit, U1 ... First unit, U2 ... 2nd unit, M1 ... 1st multiplier, M2 ... 2nd multiplier, M3 ... 3rd multiplier, M4 ... 4th multiplier, M5 ... 5th multiplier, M6 ... 6th multiplier, M7 ... 7th Multiplier, M8 ... eighth multiplier, ADD1 ... first adder, ADD2 ... second adder, ADD3 ... third adder, ADD4 ...
- the state in which the member A is connected to the member B means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
- the state in which the member C is provided between the member A and the member B refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.
- FIG. 1 is a block diagram showing a configuration of an equalizer circuit 10 according to the embodiment.
- FIG. 1 shows a state in which an equalizer circuit 10 is incorporated in an interface circuit 100 of an ATE or a general semiconductor device.
- the interface circuit 100 is connected to a receiver circuit (not shown) and transmits data via the transmission line 102.
- the data to be transmitted may be binary or an arbitrary multi-value signal such as 4-value or 8-value.
- the pattern generator (PG) 1 generates amplitude data A [N] indicating the amplitude of the signal to be transmitted and timing data T [N] indicating the cycle. N is incremented sequentially from 0. That is, the amplitude of the data is generated as A [0], A [1], A [2],... Sequentially from the top of the data, and the period of the data is T [0], T [ 1], T [2],...
- the equalizer circuit 10 receives the amplitude data A [N] and timing data T [N] for each cycle N, and shapes the waveform so that the waveform distortion caused by the propagation loss of the transmission line 102 is canceled at the receiving end.
- the amplitude data A [N] is corrected, and equalized amplitude data D [N] is generated.
- Timing generator 2 receives timing data T [N] for each cycle N and generates an edge at a timing according to the value.
- the waveform shaper 3 retimes the amplitude data D [N] equalized by the equalizer circuit 10 at the edge generated by the timing generator 2.
- the driver 4 performs digital / analog conversion on the output data of the waveform shaping unit and outputs a multilevel signal. Since various known techniques exist for signal processing by the timing generator 2, the waveform shaper 3, and the driver 4, they may be used.
- the output data D j [N] given by is calculated.
- the function g j (T1, T2) is assumed to indicate a representative value (Representative value) between the range T1 and T2 of the function f j (t).
- the first adder ADD1 adds the output data D 1 [N] to D M [N] of the M calculation units ECU 1 to ECU M and the original amplitude data A [n], and equalized amplitude data D [N] is generated.
- FIG. 2 is an example of a time chart showing the operation of the equalizer circuit 10 of FIG.
- the upper stage shows the original waveform corresponding to A [N] and T [N]
- the lower stage shows the signal waveform corresponding to equalized D [N] and T [N].
- the waveform distortion can be suitably canceled.
- this equalizer circuit 10 When this equalizer circuit 10 is used for an ATE, the RTTC function, jitter injection function, and equalizing function can coexist.
- an equalizing function is used in a communication method in which the data rate changes dynamically or in a communication method in which modulation is performed in both the amplitude direction and the time direction (data is loaded). Can be realized.
- a starting point is a continuous time equalizer (Countinuous Time Equalizer).
- the step waveform S STEP (t) is a waveform with an amplitude A, and is represented by Expression (1).
- 3A and 3B respectively show an output waveform R STEP (t) when a signal having an ideal step waveform S STEP (t) is propagated to a certain transmission line, and a waveform to be output from the equalizer circuit. It is a simulation waveform diagram which shows D EQ (t). The electrical characteristics of the propagation line are fitted to a 1 m long differential line formed on an actual printed circuit board.
- the waveform R STEP (t) is nothing but a step response.
- the waveform R STEP (t) is expanded approximately using M functions f 1 (t), f 2 (t),... F M (t). M is a natural number.
- f 1 (t), f 2 (t),... F M (t) may be in completely different forms, but are preferably defined in the same form. This is to simplify the hardware implementation.
- the waveform R STEP (t) can be approximated by Expression (2).
- M 4.
- the equalizing process for the step waveform of the first step is extended to a continuous data string.
- a transmission line is a passive device and does not behave non-linearly. Therefore, it can be considered that the “superposition principle” in a linear network holds.
- FIG. 4 is a diagram illustrating a state in which a continuous data string S (t) is decomposed into a sum of step waveforms.
- binary data is illustrated, but even if it is ternary or more, it is valid.
- FIG. 5 is a waveform diagram showing an equalizing waveform of the decomposed step waveform.
- FIG. 6 is a diagram showing waveforms obtained by superimposing the waveforms shown in FIG.
- equation (7) is obtained.
- the second step was a continuous time discussion.
- a discrete time equalizer circuit will be considered.
- the level of the equalizing waveform D CT (t) in the continuous time system shown in FIG. 6 changes within each period.
- the equalizing waveform takes a constant value in each period.
- FIG. 7 is a diagram illustrating a continuous-time system equalizing waveform D CT (t) and a discrete-time system equalizing waveform D DT (t n ).
- the waveform D CT (t) is quantized for each cycle.
- the value of the waveform D CT (t n ) is a representative value in the period t n to t n + 1 of the waveform D CT (t).
- Equation (F) is an equalizing waveform to be generated by the discrete-time equalizer circuit.
- an integral average (area average) of the periods T1 to T2 may be used.
- the function f j (t) is defined by Expression (C)
- the function g j (T1, T2) is given by Expression (11).
- equation (12) Substituting equation (11) into equation (F) for the discrete time equalizer yields equation (12).
- the equalizer circuit 10 can observe a waveform with less distortion at the receiving end by performing the signal processing expressed by the equation (F).
- the equalizer circuit 10 since the value of the output data D [N] of the equalizer circuit 10 matches D DT [N] in the equation (F), it is confirmed that the waveform distortion can be canceled.
- the waveform distortion can be canceled by executing the signal processing represented by Expression (13).
- Equation (13) can be transformed into Equation (14).
- the expression (14) can be expressed in the form of the expression (17).
- each calculation unit ECU j is represented by [F T ( ⁇ j , ⁇ j , T [N]) ⁇ F A ( ⁇ j , A [N], T [n] ]]] This term should be calculated.
- FIG. 8 is a circuit diagram showing a first configuration example of the calculation unit ECU j .
- the calculation unit ECU j includes a first unit U1, a second unit U2, and a first multiplier M1.
- the first unit U1 and the second unit U2 respectively perform F A [N] in Expression (16) and F T [N] in Expression (15).
- the first multiplier M1 multiplies the output data F A [N] of the first unit U1 and the output data F T [N] of the second unit U2, and outputs the result as D j [N].
- the first unit U1 for calculating equation (18) may be implemented with a circular filter as shown in FIG. This validity is supported by the following equation (19).
- the first unit U1 includes a second multiplier M2, a third multiplier M3, a first function unit FUNC1, a second adder ADD2, a third adder ADD3, a first delay circuit DLY1, a second delay.
- a circuit DLY2 is included.
- the second multiplier M2 multiplies T [N] by a constant ( ⁇ 1 / ⁇ j ).
- the first function unit FUNC1 receives the output data ( ⁇ T [N] / ⁇ j ) of the second multiplier M2 and outputs data expressed as exp ( ⁇ T [N] / ⁇ j ).
- the first delay circuit DLY1 delays the data A [N] by one cycle according to the time series N, and generates A [N ⁇ 1].
- the second adder ADD2 subtracts A [N ⁇ 1] from A [N].
- the third multiplier M3 multiplies the first data F A [N] by the output data exp ( ⁇ T [N] / ⁇ j ) of the first function unit FUNC1.
- the second delay circuit DLY2 delays the output data of the third multiplier M3 by one cycle corresponding to the time series N.
- the third adder ADD3 adds the output data of the second delay circuit DLY2 and the output data of the second adder ADD2, and generates first data F A [N].
- the second unit U2 includes an inverse number generator INV1, a fourth multiplier M4 to a sixth multiplier M6, a second function unit FUNC2, and a fourth adder ADD4.
- the reciprocal number generator INV1 generates a reciprocal number (1 / T [N]) of the data T [N].
- the fourth multiplier M4 multiplies the output data (1 / T [N]) of the reciprocal number generator INV1 by a constant ( ⁇ j ⁇ ⁇ j ).
- the fifth multiplier M5 multiplies T [N] by a constant ( ⁇ 1 / ⁇ j ).
- the second function unit FUNC2 receives the output data ( ⁇ T [N] / ⁇ j ) of the fifth multiplier M5 and outputs data expressed as exp ( ⁇ T [N] / ⁇ j ).
- the fourth adder ADD4 subtracts the output data of the second function unit FUNC2 from the constant 1.
- the sixth multiplier M6 multiplies the output data of the fourth multiplier M4 and the output data of the fourth adder ADD4 to generate second data F T [N].
- the reciprocal number generator INV1, the first function unit FUNC1, and the second function unit FUNC2 may be an arithmetic unit or a lookup table.
- the second multiplier M2 and the first function unit FUNC1 of the first unit U1 and the fifth multiplier M5 and the second function unit FUNC2 of the second unit U2 calculate the common terms and are shown in FIG. It is desirable to share it. Thereby, a circuit area and calculation cost can be reduced.
- FIG. 9 is a circuit diagram showing a second configuration example of the calculation unit ECU j .
- F A [N] A ′ [N] + A ′ [N ⁇ 1] ⁇ exp ( ⁇ 1 / ⁇ j ⁇ T [N ⁇ 1]) + A ′ [N ⁇ 2] ⁇ exp ( ⁇ 1 / ⁇ j ⁇ (T [N ⁇ 1] + T [N ⁇ 2])) + A ′ [N ⁇ 3] ⁇ exp ( ⁇ 1 / ⁇ j ⁇ (T [N ⁇ 1] + T [N ⁇ 2] + T [N ⁇ 3])) +... (16a) It becomes.
- the first unit U1a in FIG. 9 is configured in an L-order FIR filter format that adds Expression (16a) to the L-th term (L is a natural number).
- FIG. 10 is a circuit diagram showing a configuration of the calculation unit ECU j according to the first modification.
- the third data F T ′ [N] is calculated.
- the second unit U2b includes a fifth multiplier M5, a seventh multiplier M7, a third function unit FUNC3, and an eighth multiplier M8 connected in series.
- the fifth multiplier M5 multiplies T [N] by a constant ( ⁇ 1 / ⁇ j ).
- the seventh multiplier M7 multiplies the output data of the fifth multiplier M5 by a constant (1/2).
- the third function unit FUNC3 receives the output data x of the seventh multiplier M7 and outputs exp (x).
- the eighth multiplier M8 multiplies the output data of the third function unit FUNC3 by a constant ⁇
- the first unit U1 is the same as that of FIG.
- the first multiplier M1 multiplies the first data F A [N] and the third data F T ′ [N].
- the reciprocal generator is not required as compared with the calculation unit ECU j of FIGS. 8 and 9, and the circuit scale can be suppressed.
- FIG. 11 is a circuit diagram showing a configuration of a calculation unit ECU j according to the second modification.
- the circuit in FIG. 11 is a combination of the first unit U1a in FIG. 9 and the second unit U2b in FIG.
- Such a modification is also effective as the present invention.
- FIG. 12 is a circuit diagram showing a configuration of a calculation unit ECU 'j according to a third modification.
- the first delay circuit DLY1 and the second adder ADD2 of the calculation unit ECU of FIG. 8 are shared by the plurality of calculation units ECU 1 to ECU M.
- the entire area of the interface circuit 100d can be reduced as compared with FIG.
- FIG. 13 is a circuit diagram showing a configuration of a calculation unit ECU j according to the fourth modification.
- F T '[N] ⁇ j ⁇ exp ( ⁇ T [N] / (2 ⁇ ⁇ j )) ⁇ in the equation (21c) ⁇ (22) is obtained.
- the calculation unit ECU j in FIG. 13 performs a calculation according to the equation (22). Specifically, the calculation unit ECU j includes adders ADD2, ADD3, ADD5, ADD6, delay circuits DLY1, DLY2, function units FUNC4 to FUNC6, and multipliers M5, M7.
- the fifth multiplier M5 multiplies T [N] by a coefficient ( ⁇ 1 / ⁇ j ).
- the seventh multiplier M7 multiplies the output data of the fifth multiplier M5 by (1/2).
- the fourth function unit FUNC4 generates a logarithm log e (x) of the input data x.
- the sixth adder ADD6 adds the output data of the seventh multiplier M7, the fourth function unit FUNC4, and a constant (log e ( ⁇ j )).
- the sixth function unit FUNC6 receives the output data x of the sixth adder ADD6 and outputs exp (x).
- the fifth adder ADD5 adds the output data of the fifth multiplier M5 and the output data of the fourth function unit FUNC4.
- the fifth function unit FUNC5 receives the output data x of the fifth adder ADD5 and outputs exp (x).
- the second delay circuit DLY2 delays the output data of the fifth function unit FUNC5 by one cycle corresponding to the time series N.
- the third adder ADD3 adds the output data of the second delay circuit DLY2 and the output data of the second adder ADD2, and outputs the result to the fourth function unit FUNC4.
- FIGS. 14A and 14B are block diagrams showing configurations of equalizer circuits 10e and 10f according to sixth and seventh modifications, respectively.
- the equalizer circuit 10e includes a memory 11 instead of the plurality of calculation units ECU.
- the first adder ADD1 adds A [N] and the equalizing amount stored in the memory 11.
- the equalizer circuit 10f is a memory. That is, the equalizing waveform itself given by Expression (F) is calculated in advance and stored in the memory.
- the sixth and seventh modified examples are difficult to apply to data communication in which data to be transmitted cannot be predicted, but are suitable for applications such as semiconductor test equipment that supply predetermined pattern data to the DUT. Available to:
- the present invention can be used for communication technology.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
伝送線路のステップ応答波形RSTEP(t)を、時間tを引数とするM個の関数fj(t)(1≦j≦M)およびステップ波形SSTEP(t)を用いて、
RSTEP(t)=SSTEP(t)・(1-Σj=1:Mfj(t))
で近似する。関数fj(t)の範囲t=T1~T2の間の代表値を関数gj(T1,T2)と書く。
j番目(1≦j≦M)の計算ユニットは、N番目の信号に対して、
Dj[N]=Σn=0:N[(A[n]-A[n-1])・gj(tN-tn,tN+1-tn)]
で与えられる出力データDj[N]を計算する。
トランスミッタは、振幅データA[N]とタイミングデータT[N]を発生するパターン発生器と、上述のイコライザ回路と、イコライザ回路によりイコライズされた振幅データD[N]を、タイミングデータT[N]でリタイミングする波形整形部と、波形整形部の出力データを多値信号に変換するドライバと、を備える。
この態様によれば、送信データのUIよりも長い時定数の伝送線路の波形歪みに対しても好ましいイコライジングを行うことができるため、受信側においてデシジョンフィードバックイコライザなどの複雑な受信イコライザが不要になるという利点がある。
この態様によれば、UIが変化する信号に対しても好ましいイコライジングが行えるため,RTTC機能やジッタインジェクション機能とイコライジングを両立させることができ、あるいはイコライジング量を故意的に変化させてDUTの性能を検査できる。
伝送線路102の電気的特性(電気長、伝搬損失やインピーダンス)は予め測定あるいはシミュレーションによって取得されており、そのステップ応答波形RSTEP(t)が既知であることを前提とする。
そして、そのステップ応答波形RSTEP(t)を、時間tを引数とするM個の関数fj(t)(1≦j≦M)およびステップ波形SSTEP(t)を用いて、
RSTEP(t)=SSTEP(t)・(1-Σj=1:Mfj(t))
で近似する。
Dj[N]=Σn=0:N[(A[n]-A[n-1])・gj(tN-tn,tN+1-tn)]
で与えられる出力データDj[N]を計算する。ここで、関数gj(T1,T2)は、関数fj(t)の範囲T1からT2の間の代表値(Representative value)を示すものとする。
D[N]=A[N]+Σj=1:M(Dj[N])
まず、連続時間系のイコライザ(Countinuous Time Equalizer)を出発点とする。ステップ波形SSTEP(t)は、振幅Aの波形であり、式(1)で表される。
RSTEP(t)=SSTEP(t)・(1-Σj=1:Mfj(t)) …(A)
Σj=1:M()は、()内の要素を変数jを1からMまで加算することを示す。
DEQ(t)=SSTEP(t)・[1+Σj=1:Mfj(t)] …(B)
で表される。
fj(t)=αj・exp(-t/τj) …(C)
で定義される。
α1=0.90 τ1=65ps
α2=0.26 τ2=400ps
α3=0.10 τ3=2000ps
α4=0.14 τ4=100000ps
が例示される。自然数Mは、回路面積とフィッティングの精度(イコライジングの精度)の間のトレードオフを考慮して決めればよいが、現実的なインプリメンテーションを考慮すると、M=1~5の範囲が好ましい。
DAn(t)=SAn(t)・[1+Σj=1:Mfj(t-tn)] …(D)
DCT(t)=A[N]+Σn=0:N[(A[n]-A[n-1])・Σj=1:Mfj(t)]
…(E)
DDT[N]=A[N]+Σn=0:N[(A[n]-A[n-1])・Σj=1:Mgj(tN-tn,tN+1-tn)] …(F)
続いて、式(13)で与えられる信号処理を実現するための具体的な回路の構成を説明する。
[FT(αj,τj,T[N])・FA(τj,A[N],T[n])]
の項を計算すればよい。
第1ユニットU1、第2ユニットU2はそれぞれ、式(16)のFA[N]、式(15)のFT[N]の演算を行う。第1乗算器M1は、第1ユニットU1の出力データFA[N]と、第2ユニットU2の出力データFT[N]を乗算し、Dj[N]として出力する。
逆数発生器INV1は、データT[N]の逆数(1/T[N])を発生する。第4乗算器M4は、逆数発生器INV1の出力データ(1/T[N])に定数(αj・τj)を乗算する。
FA[N]=A’[N]
+A’[N-1]・exp(-1/τj・T[N-1])
+A’[N-2]・exp(-1/τj・(T[N-1]+T[N-2]))
+A’[N-3]・exp(-1/τj・(T[N-1]+T[N-2]+T[N-3]))+・・・・ …(16a)
となる。図9の第1ユニットU1aは、式(16a)を第L項(Lは自然数)まで加算するL次のFIRフィルタ形式で構成される。
上述の実施例では、関数fj(t)の代表値gjとして、積分平均を利用する場合を説明したが、積分平均に代えて、時刻T1と時刻T2の中央のタイミングにおける値を用いてもよい。つまり、
gj(T1,T2)=fj((T1+T2)/2)
であってもよい。
FT’[N]=αj・exp(-T[N]/(2・τj))}
なる第3データFT’[N]を演算する。具体的には第2ユニットU2bは、シリーズに接続された、第5乗算器M5、第7乗算器M7、第3関数ユニットFUNC3、第8乗算器M8を含む。第5乗算器M5は、T[N]に定数(-1/τj)を乗算する。第7乗算器M7は、第5乗算器M5の出力データに定数(1/2)を乗算する。第3関数ユニットFUNC3は、第7乗算器M7の出力データxを受け、exp(x)を出力する。第8乗算器M8は、第3関数ユニットFUNC3の出力データに定数αjを乗算する。
図11は、第2の変形例に係る計算ユニットECUjの構成を示す回路図である。図11の回路は、図9の第1ユニットU1aと図10の第2ユニットU2bの組合せである。かかる変形例も本発明として有効である。
図12は、第3の変形例に係る計算ユニットECU’jの構成を示す回路図である。図12においては、図8の計算ユニットECUの第1遅延回路DLY1および第2加算器ADD2が、複数の計算ユニットECU1~ECUMで共有される。この変形例では、インタフェース回路100d全体の面積を、図8に比べて削減できる。
図13は、第4の変形例に係る計算ユニットECUjの構成を示す回路図である。図13は、図10の回路の一部をLOG変換回路を用いて構成したものである。すなわち、
A×B=exp(logeA+logeB)
なる関係式を、式(21c)の
FT’[N]=αj・exp(-T[N]/(2・τj))}
に適用すると、式(22)を得る。
関数fj(t)の代表値gjとして、時刻T1と時刻T2の値の加算平均値を用いてもよい。
gj(T1,T2)={fj(T1)+fj(T2)}/2
当業者であれば、この式にもとづいても、具体的な回路が構成できよう。
図14(a)、(b)はそれぞれ、第6、第7の変形例に係るイコライザ回路10e、10fの構成を示すブロック図である。
上述の実施の形態では、デジタル信号処理を例に説明したが、その一部あるいは全部をアナログ演算で実現してもよい。
Claims (17)
- 伝送線路を介して伝送すべきN番目(Nは非負整数)の信号の振幅レベルを示す振幅データA[N]と前記信号の周期を示すタイミングデータT[N]を受け、波形整形するイコライザ回路であって、
M個(Mは自然数)の計算ユニットと、
前記M個の計算ユニットの出力データと前記振幅データA[N]を加算し、イコライズされた振幅データを発生する第1加算器と、
を備え、
前記伝送線路のステップ応答波形RSTEP(t)を、時間tを引数とするM個の関数fj(t)(1≦j≦M)およびステップ波形SSTEP(t)を用いて、
RSTEP(t)=SSTEP(t)・(1-Σj=1:Mfj(t))
で近似し、前記関数fj(t)の範囲T1からT2の間の代表値が関数gj(T1,T2)で与えられるとき、
j番目(1≦j≦M)の前記計算ユニットは、N番目の信号に対して、
Dj[N]=Σn=0:N[(A[n]-A[n-1])・gj(tN-tn,tN+1-tn)]
で与えられる出力データDj[N]を計算することを特徴とするイコライザ回路。 - 異なる自然数jに対する関数fj(t)は互いに同じ形式で定義され、前記M個の計算ユニットは互いに同じ構成を有することを特徴とする請求項1に記載のイコライザ回路。
- 前記関数fj(t)は、パラメータαj、τjを用いて、
fj(t)=αj・exp(-t/τj)
で定義されることを特徴とする請求項2に記載のイコライザ回路。 - j番目(1≦j≦M)の前記計算ユニットは、
Σn=0:N[(A[n]-A[n-1])・exp(-1/τj・Σk=n:N-1T[k])]
なる第1データを演算する第1ユニットと、
αj・τj/T[N]・{1-exp(-T[N]/τj)}
なる第2データを演算する第2ユニットと、
前記第1データと前記第2データを乗算する第1乗算器と、
を含むことを特徴とする請求項3に記載のイコライザ回路。 - 前記第1ユニットは、
T[N]に定数(-1/τj)を乗算する第2乗算器と、
前記第2乗算器の出力データ(-T[N]/τj)を受け、exp(-T[N]/τj)なるデータを出力する第1関数ユニットと、
A[N]を時系列Nに応じた1周期遅延させ、A[N-1]を生成する第1遅延回路と、
A[N]からA[N-1]を減算する第2加算器と、
前記第1データに前記第1関数ユニットの出力データを乗算する第3乗算器と、
前記第3乗算器の出力データを、時系列Nに応じた1周期遅延させる第2遅延回路と、
前記第2遅延回路の出力データと前記第2加算器の出力データを加算し、前記第1データを生成する第3加算器と、
を含むことを特徴とする請求項4に記載のイコライザ回路。 - 前記第2ユニットは、
T[N]の逆数(1/T[N])を発生する逆数発生器と、
前記逆数発生器の出力データ(1/T[N])に定数(αj・τj)を乗算する第4乗算器と、
T[N]に定数(-1/τj)を乗算する第5乗算器と、
前記第5乗算器の出力データ(-T[N]/τj)を受け、exp(-T[N]/τj)なるデータを出力する第2関数ユニットと、
定数1から前記第2関数ユニットの出力データを減算したデータを出力する第4加算器と、
前記第4乗算器の出力データと前記第4加算器の出力データを乗算し、前記第2データを生成する第6乗算器と、
を含むことを特徴とする請求項4に記載のイコライザ回路。 - 前記第1ユニットは、
(A[N]-A[N-1])
+(A[N-1]-A[N-2])・exp(-1/τj・T[N-1])
+(A[N-2]-A[N-3])・exp(-1/τj・(T[N-1]+T[N-2]))
+(A[N-3]-A[N-4])・exp(-1/τj・(T[N-1]+T[N-2]+T[N-3]))+・・・・
を第L項(Lは自然数)まで加算するL次のFIRフィルタ形式で構成されることを特徴とする請求項4に記載のイコライザ回路。 - j番目(1≦j≦M)の前記計算ユニットは、
Σn=0:N[(A[n]-A[n-1])・exp(-1/τj・Σk=n:N-1T[k])]
なる第1データを演算する第1ユニットと、
αj・exp(-T[N]/(2・τj))}
なる第3データを演算する第2ユニットと、
前記第1データと前記第3データを乗算する第1乗算器と、
を含むことを特徴とする請求項3に記載のイコライザ回路。 - 前記第1ユニットは、
(A[N]-A[N-1])
+(A[N-1]-A[N-2])・exp(-1/τj・T[N-1])
+(A[N-2]-A[N-3])・exp(-1/τj・(T[N-1]+T[N-2]))
+(A[N-3]-A[N-4])・exp(-1/τj・(T[N-1]+T[N-2]+T[N-3]))
+・・・・
を第L項(Lは自然数)まで加算するL次のFIRフィルタ形式で構成されることを特徴とする請求項8に記載のイコライザ回路。 - 振幅データA[N]とタイミングデータT[N]を発生するパターン発生器と、
請求項1から9のいずれかに記載のイコライザ回路と、
前記イコライザ回路によりイコライズされた振幅データD[N]を、前記タイミングデータT[N]でリタイミングする波形整形部と、
前記波形整形部の出力データを多値信号に変換するドライバと、
を備えることを特徴とするトランスミッタ。 - 被試験デバイスに試験データを供給する試験装置であって、
振幅データA[N]とタイミングデータT[N]を発生するパターン発生器と、
前記タイミングデータT[N]を受け、その値に応じたタイミングでエッジを発生させるタイミング発生器と、
請求項1から9のいずれかに記載のイコライザ回路と、
前記イコライザ回路によりイコライズされた振幅データD[N]を、前記タイミング発生器により生成されたエッジでリタイミングする波形整形部と、
前記波形整形部の出力データを多値信号に変換するドライバと、
を備えることを特徴とする試験装置。 - 伝送線路を介して伝送すべき信号の波形を送信側において整形する方法であって、
前記伝送線路のステップ応答波形RSTEP(t)を、時間tを引数とするM個(Mは自然数)の関数fj(t)(1≦j≦M)およびステップ波形SSTEP(t)を用いて、
RSTEP(t)=SSTEP(t)・(1-Σj=1:Mfj(t))
で近似し、前記関数fj(t)の範囲T1からT2の間の代表値が関数gj(T1,T2)で与えられるとき、
前記方法は、
N番目(Nは非負整数)の前記信号の振幅レベルを示す振幅データA[N]と前記信号の周期を示すタイミングデータT[N]をNをインクリメントしながら順次発生する第1ステップと、
DDT[N]=A[N]+Σn=0:N[(A[n]-A[n-1])・Σj=1:Mgj(tN-tn,tN+1-tn)]
で与えられるイコライズされた振幅DDT[N]を出力する第2ステップと、
を備えることを特徴とする方法。 - 関数f1(t)、f2(t)、…fM(t)は同じ形式で定義されることを特徴とする請求項12に記載の方法。
- 前記関数fj(t)は、パラメータαj、τjを用いて、
fj(t)=αj・exp(-t/τj)
で定義されることを特徴とする請求項13に記載の方法。 - 前記関数gj(T1,T2)は、前記関数fj(t)の時刻T1から時刻T2の間の積分平均であることを特徴とする請求項12または13に記載の方法。
- 前記関数gj(T1,T2)は、
gj(T1,T2)={fj(T1)+fj(T2)}/2
であることを特徴とする請求項12または13に記載の方法。 - 前記関数gj(T1,T2)は、
gj(T1,T2)=fj((T1+T2)/2)
であることを特徴とする請求項12または13に記載の方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2009/000988 WO2010100674A1 (ja) | 2009-03-04 | 2009-03-04 | イコライザ回路およびそれを用いた試験装置 |
JP2010501321A JP5274543B2 (ja) | 2009-03-04 | 2009-03-04 | イコライザ回路、それを用いたトランスミッタおよび試験装置ならびに、波形整形方法 |
US12/808,359 US8320440B2 (en) | 2009-03-04 | 2009-03-04 | Equalizer circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2009/000988 WO2010100674A1 (ja) | 2009-03-04 | 2009-03-04 | イコライザ回路およびそれを用いた試験装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010100674A1 true WO2010100674A1 (ja) | 2010-09-10 |
Family
ID=42709254
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/000988 WO2010100674A1 (ja) | 2009-03-04 | 2009-03-04 | イコライザ回路およびそれを用いた試験装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8320440B2 (ja) |
JP (1) | JP5274543B2 (ja) |
WO (1) | WO2010100674A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019169779A (ja) * | 2018-03-22 | 2019-10-03 | 東芝メモリ株式会社 | クロック・データ再生装置、メモリシステム及びデータ再生方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004518326A (ja) * | 2001-01-11 | 2004-06-17 | エイエスエムエル ユーエス, インコーポレイテッド | 効率的かつ正確なフィルタリングおよび補間のための方法およびシステム |
JP2008271552A (ja) * | 2007-04-16 | 2008-11-06 | Tektronix Internatl Sales Gmbh | デジタル・プリエンファシス波形データ生成方法及び装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112005001349T5 (de) | 2004-06-09 | 2007-04-26 | Advantest Corp. | Taktgenerator und Halbleitertestvorrichtung |
US7502980B2 (en) * | 2006-08-24 | 2009-03-10 | Advantest Corporation | Signal generator, test apparatus, and circuit device |
-
2009
- 2009-03-04 US US12/808,359 patent/US8320440B2/en not_active Expired - Fee Related
- 2009-03-04 WO PCT/JP2009/000988 patent/WO2010100674A1/ja active Application Filing
- 2009-03-04 JP JP2010501321A patent/JP5274543B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004518326A (ja) * | 2001-01-11 | 2004-06-17 | エイエスエムエル ユーエス, インコーポレイテッド | 効率的かつ正確なフィルタリングおよび補間のための方法およびシステム |
JP2008271552A (ja) * | 2007-04-16 | 2008-11-06 | Tektronix Internatl Sales Gmbh | デジタル・プリエンファシス波形データ生成方法及び装置 |
Also Published As
Publication number | Publication date |
---|---|
US8320440B2 (en) | 2012-11-27 |
JPWO2010100674A1 (ja) | 2012-09-06 |
JP5274543B2 (ja) | 2013-08-28 |
US20110051798A1 (en) | 2011-03-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Uncini et al. | Complex-valued neural networks with adaptive spline activation function for digital-radio-links nonlinear equalization | |
US8180609B2 (en) | Jittery signal generation with discrete-time filtering | |
CN102594346B (zh) | 使用滤波器乘积的线性校正器的校准系统和方法 | |
JPH0936782A (ja) | 連続信号等化回路および等化方法 | |
ITTO970633A1 (it) | Procedimento e sistema per la ricezione di segnali digitali | |
US20170295039A1 (en) | Decision feedback equalizer | |
US20070223571A1 (en) | Decision-feedback equalizer simulator | |
JPWO2007010889A1 (ja) | 適応ディジタルフィルタ、fm受信機、信号処理方法、およびプログラム | |
JP3752237B2 (ja) | A/d変換装置 | |
CN102160336B (zh) | 仿真装置和仿真方法 | |
Redfern et al. | A root method for Volterra system equalization | |
US20210021401A1 (en) | Method and apparatus for a one bit per symbol timing recovery phase detector | |
JP5274543B2 (ja) | イコライザ回路、それを用いたトランスミッタおよび試験装置ならびに、波形整形方法 | |
US7023930B2 (en) | Reducing the crest factor of a multicarrier signal | |
US7924911B2 (en) | Techniques for simulating a decision feedback equalizer circuit | |
US9178542B1 (en) | Methods and apparatus for accurate transmitter simulation for link optimization | |
US11683093B2 (en) | Wavelength dispersion compensation apparatus, optical receiving apparatus, wavelength dispersion compensation method and computer program | |
CN101682367B (zh) | 线缆网络中的信号质量确定 | |
US7933323B2 (en) | Method and system for performing timing recovery in a digital communication system | |
Zou et al. | FPGA-based configurable and highly flexible PAM4 SerDes simulation system | |
US3758863A (en) | Device for equalizing binary bipolar signals | |
JP2008219078A (ja) | 等化回路および歪軽減方法 | |
CN105099970A (zh) | 自适应均衡器、自适应均衡方法以及接收机 | |
CN107005307B (zh) | 一种设置均衡装置的方法及均衡装置 | |
TWI435575B (zh) | 接收器以及對接收訊號進行等化處理的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 2010501321 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12808359 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09841041 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09841041 Country of ref document: EP Kind code of ref document: A1 |