WO2010057345A1 - 一种改进的位同步数字化的方法 - Google Patents

一种改进的位同步数字化的方法 Download PDF

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Publication number
WO2010057345A1
WO2010057345A1 PCT/CN2008/073163 CN2008073163W WO2010057345A1 WO 2010057345 A1 WO2010057345 A1 WO 2010057345A1 CN 2008073163 W CN2008073163 W CN 2008073163W WO 2010057345 A1 WO2010057345 A1 WO 2010057345A1
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Prior art keywords
delay
output
bit synchronization
channel
path
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PCT/CN2008/073163
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English (en)
French (fr)
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王可
黄钦旋
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深圳市好易通科技有限公司
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Priority to CN200880002215.XA priority Critical patent/CN101889408B/zh
Priority to PCT/CN2008/073163 priority patent/WO2010057345A1/zh
Publication of WO2010057345A1 publication Critical patent/WO2010057345A1/zh

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation

Definitions

  • the present invention relates to a bit synchronization technology in the field of wireless communication, and relates to an improved bit synchronization digitization method, which can be applied to a digital wireless mobile (Digital Mobile Radio)
  • CPFSK continuous phase frequency shift keying
  • bit synchronization timing recovery is important for the correctness of decoding.
  • bit synchronization is the most basic synchronization.
  • the basic meaning of bit synchronization is that the clock signals of the receiving end and the transmitting end must be in phase with each other, so that the receiving end can correctly receive and judge each symbol sent by the transmitting end.
  • Bit synchronization is the key technology of the physical layer of the wireless communication terminal. It is the key point and difficulty of the demodulation algorithm. It has important images for the final demodulation performance. If the bit synchronization problem cannot be solved, the information cannot be correctly demodulated, that is, The receiving end cannot recognize the information sent by the sender.
  • the most commonly used bit synchronization technology is maximum likelihood estimation, and its synchronization technology based on Fast Fourier Transform (FFT) algorithm is an early-late gate synchronization technique.
  • FFT Fast Fourier Transform
  • the maximum likelihood estimation can be optimal in theory, but the calculation amount is also the most complicated, which is not suitable for digital implementation.
  • the FFT algorithm is currently mainly used in an orthogonal frequency division multiplexing (OFDM) communication system, and some non-linear operations must be performed on the received signal to obtain a desired timing line spectrum.
  • OFDM orthogonal frequency division multiplexing
  • the narrowband bandpass filter or phase-locked loop is utilized.
  • phase locked loop PLL
  • Tone filtering This method has a large amount of computation.
  • Sooner or later door technology is currently mainly used for phase shift keying
  • phase shift keying cylinder called PSK
  • QPSK quadrature phase shift keying
  • DMR is the latest digital professional communication standard that the international ETSI organization is perfecting. Since it has not been fully formed and is now tracked, it can keep technically synchronized with large foreign companies and avoid patented technical barriers, which is equivalent to standing on the same starting line.
  • the core technologies and chips of key parts of digital wireless communication are the current weaknesses in China.
  • the synchronization of DMR is more difficult to implement, and there is almost no relevant scheme for public information, which brings great difficulty to the design of the algorithm.
  • the existing DMR transceiver system is independently developed by the company and can fully realize the functions of modulation and demodulation synchronization.
  • the bit synchronization algorithm currently used by DMR is technically limited by the source. When the source does not meet the requirements, the frame loss phenomenon occurs, and the bit synchronization time is long. The most case is that the synchronization is not always performed. This caused the communication to be unsuccessful.
  • the existing DMR bit synchronization algorithm is as follows: First, a path is preset from the [+1 +3 -1 -3] four-way signal as a synchronization decision, and the +1 path is taken as an example here. Let the input signal at any time be:
  • is the phase accumulated value before the current time
  • is the modulation phase corresponding to the modulation level
  • n is the modulation level
  • is the modulation phase corresponding to the modulation level 1.
  • the input signal is subjected to delay processing to obtain four different delay signals, namely no delay, 2 delays, 4 delays, and 6 delays. Multiplying four local signals in one symbol period, and then multiplying the output values by averaging over the symbol period, and outputting the absolute value of the result. It can be seen that when the symbol +1 comes, the value of one output of the correct bit synchronization is the largest and is 1, and the values of the other three outputs are less than 1.
  • the modulation data is +1 at this time, and the symbol sampling point ⁇ ⁇ is 8.
  • the corresponding output value of the correct bit synchronization is:
  • the existing bit synchronization algorithm is bit-synchronized on the characteristics of the source, so its bit synchronization effect is limited by the source, when the source appears consecutive "1" or does not appear “1"
  • the probability of bit synchronization error is large, which causes the frame loss and bit synchronization time to be longer.
  • the current bit synchronization algorithm is not ideal for anti-noise performance. When the signal-to-noise ratio is low, the performance is significantly reduced.
  • the object of the present invention is to improve the DMR bit synchronization algorithm of the prior art, to solve the problem that the performance of the algorithm is limited by the source form, and to provide an improved bit synchronization digitization method, so that the method is in a random source. It can also run well and meet the requirements of the actual situation, and further improve the performance of the original DMR bit synchronization algorithm when the noise is large.
  • the technical solution adopted by the present invention to solve the technical problem is to construct an improved bit synchronization digitization method.
  • the method includes the following steps:
  • Interval delay of the input signal sequence the signal sequence comprising at least one input signal
  • the input signals of each channel are respectively multiplied by the input signals of at least one local channel in one symbol period, and the multiplied output values are accumulated and averaged in the symbol period;
  • the maximum mean value of each channel is integrated, and the integrated value of each channel is compared, and the corresponding decoded output of the largest integrated value is selected.
  • the decision output of the delay of 0 is:
  • the decision output of the , , , , and delays of 2 is:
  • the decision output of the delay of 4 is:
  • the decision output of the delay of 6 is:
  • the signal sequence interval delay settings are respectively set to: the first path is a delay-free data stream, and the second path is a delay of 2 symbol periods, the third path The delay is 4 symbol periods and the fourth is delayed by 6 symbol periods, so that the parallel synchronous input source is converted into a serial input source.
  • the sine and cosine phase generating steps of 8 points in the symbol are further included, specifically: generating an address, outputting 0-7 cycles, and feeding to the next-stage ROM memory as an address; the ROM memory input is a 4-bit address, Output 12-bit trigonometric function value.
  • the step of combining the delayed signals is further included, which is specifically:
  • the four I and Q signals without delay, delay of 2 symbol periods, time of 4 symbol periods, and delay of 6 symbol periods are combined into one output.
  • step of clock delay is further included, which is specifically:
  • the step of accumulating is further included, specifically: The correlation result of the operation is accumulated at 8 points in the symbol, and the accumulated result is output.
  • the correlation values of the +1/+3/-1/-3 paths of the four-way delay are combined into a serial output.
  • the parallel-to-serial conversion step is further included, specifically:
  • the value of the serial data is assigned to a parallel output when the corresponding clock signal arrives.
  • step of bit synchronization decision is further included, which is specifically:
  • the decision method is independent of the source form, does not depend on the appearance of a certain symbol, and the change of the source form does not affect the quality of the bit synchronization, and the running performance is good in the case of a random source.
  • the improved DMR bit synchronization method maximizes the distance between the correct decision and the wrong decision, which is beneficial to the bit decision ambiguity caused by the degradation of the received signal quality, and the anti-noise performance is greatly improved.
  • FIG. 1 is a schematic diagram of a bit synchronization structure of a DMR communication system in the prior art
  • FIG. 2 is a schematic diagram of a bit synchronization structure of a DMR communication system in the present invention
  • FIG. 3 is a schematic structural diagram of a DMR bit synchronization module in the present invention.
  • Figure 4 is a schematic diagram showing the timing relationship of the present invention.
  • FIG. 5 is a schematic diagram of the combined serial output of the present invention.
  • Figure 6 is a schematic diagram showing the timing relationship of the present invention.
  • Figure 7 is a schematic diagram of the correspondence of serial-to-parallel conversion of the present invention.
  • Figure 8 is a block diagram showing the bit synchronization decision of the present invention.
  • FIG. 9 is a block diagram showing the maximum correlation value of the output delay in the present invention.
  • An improved bit synchronization digitization method of the present invention is directed to any random source, the method comprising: performing an interval delay on an input signal sequence, the signal sequence including at least one input signal; One way of input signal with at least one local channel in one symbol period The input signals are multiplied, and the multiplied output values are accumulated in the symbol period and averaged; the average value of each channel of each input signal is compared, and the mean value of the largest mean value and its corresponding decoded output are selected; And in the preset time window length, the maximum mean value of each way is integrated, and the integrated value of each way is compared, and the corresponding decoded output of the largest integrated value is selected.
  • the signal sequence interval delay setting is respectively set to: the first path is an undelayed data stream, the second path is a delay of 2 symbol periods, and the third path is extended.
  • the 4 symbol periods and the fourth path are delayed by 6 symbol periods, which converts the parallel synchronous input source into a serial input source.
  • the fixed one corresponding to a symbol is no longer selected as the bit synchronization decision, but each symbol is temporarily outputted, and the corresponding maximum value is outputted, and a certain time window length is taken. Seek and get ⁇ ⁇ . Comparing the ⁇ values of four different delays, the largest one corresponds to the correct bit synchronization decision.
  • the decision output of the delay of 2 is:
  • the decision output of one way with a delay of 4 is:
  • the decision output of the delay of 6 is: Due to the limited space, the inference of the inequality is no longer given. It can be seen from the above results that the decision output of one channel with the correct bit synchronization delay is larger than the decision output of the other three channels, so the present invention can select the correct bit synchronization delay.
  • the length of the window function can be flexibly selected according to actual conditions. Increasing the length of the window function can make the bit synchronization decision more secure and reduce the probability of error, but it will increase the amount of calculation slightly. Principle
  • the length of the upper window function is greater than the maximum number of consecutive identical symbols that may appear. Since the occurrence of symbols in the actual situation obeys a certain probability distribution, the same symbol does not appear for a long time, so the window function does not need to take a long time.
  • the improved DMR bit synchronization algorithm of the present invention has a decision method that is independent of the source form and does not depend on the appearance of a certain symbol.
  • the change of the source form does not affect the quality of the bit synchronization.
  • the maximum distance between the correct judgment and the wrong judgment is greatly increased, which is conducive to the ambiguity of the bit decision caused by the degradation of the received signal quality.
  • the improved DMR bit synchronization algorithm has a significant improvement in performance.
  • the error rate of the existing DMR communication system under different Gaussian white noise environments is shown in Table 1 under the existing DMR bit synchronization algorithm, improved DMR bit synchronization, and manual bit synchronization. It can be seen from Table 1 that the performance of the improved bit synchronization algorithm is greatly improved, and is comparable to manual bit synchronization.
  • the specific implementation of the improved DMR bit synchronization method is shown in Figure 2.
  • the DMR baseband bit synchronization module is shown in Figure 3.
  • the following sub-modules gradually give the implementation of the demodulation function. 1.
  • Phase generation this module generates the sine and cosine phases of 8 points in the symbol. It consists of two parts: the generation address and the ROM memory.
  • This module completes the function of generating an address.
  • the output is 0-7 cycles and is sent to the next level ROM as an address.
  • the input is a 4-bit address and the 12-bit trigonometric function value is output.
  • the delay signals are combined.
  • This module combines four I and Q signals without delay, delay 2 bits, delay 4 bits, and delay 6 bits into one output.
  • Clk_38_4k corresponds to the I and Q signals without delay
  • Clk_38_4k_delayl corresponds to the I and Q signals with 2 bits delay
  • Clk_38_4k_delay2 corresponds to the I and Q signals with 4 bits delayed
  • Clk_38_4k_delay3 corresponds to the I and Q signals with 6 bits delayed.
  • the timing relationship is shown in Figure 4.
  • This module completes the four-way 38.4 kHz clock with a fixed delay to keep it in sync with the data.
  • This program completes the delay of four clock cycles of four clock signals Clk_38_4k, Clk_38_4k_delayl, Clk_38_4k_delay2, Clk_38_4k_delay3, Clk_38_4k_delay3, respectively, to cancel the delay of 2 clock cycles of data multiplication and 1 clock cycle of addition. Delay, keeping the clock and data in sync.
  • This module completes the accumulation of the results of the previous operation at the 8 points in the symbol and outputs the accumulated result. There are four modules in this module for four signals with different delays.
  • Phase 1 _squ_delay 2 (15:0) +1 way delay 4 bit data output
  • Phase 1 _squ_delay3 (15:0) +1 channel delay 6-bit data output
  • Phase3_squ_delay3 (15:0) +3 way delay 6-bit data output
  • This module implements parallel output of a total of 16 correlation values in series.
  • the string and conversion correspondence is shown in Figure 7.
  • This module outputs serial inputs in parallel from left to right in the order of this diagram.
  • the current process consists of four identical modules: the value of the serial data is assigned to a parallel output when the corresponding clock signal arrives.
  • This module implements bit synchronization judgment based on the input 16 correlation values. Internally consists of the decode_cmp module and the cmp_decode module.
  • the decode_cmp module implements the function of comparing the correlation values of +1, -1, +3, and -3 to the maximum value of the correlation.
  • the cmp_decode module is responsible for selecting one of the four correlation delay values and outputting the correlation value. First, compare the two correlation values in the four paths, select two larger ones and compare them one more time, and output the largest one. This way corresponds to the correct bit synchronization. At this point, the bit synchronization function is completed.
  • the decision method of the present invention is independent of the source form and does not depend on the appearance of a certain symbol.
  • the change of the source form does not affect the quality of the bit synchronization.
  • the running performance is good in the case of random sources.
  • the improved DMR bit synchronization method maximizes the distance between the correct decision and the wrong decision, which is conducive to confrontation.
  • the bit decision caused by the degradation of the received signal quality is blurred, and the anti-noise performance is greatly improved.

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  • Computer Networks & Wireless Communication (AREA)
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Description

一种改进的位同步数字化的方法 技术领域 本发明涉及无线通信领域中的位同步技术,涉及一种改进的位同步数字化 的方法, 可应用于数字无线移动(Digital Mobile Radio, 筒称 DMR )专业无线 通信领域和所有连续相位移频键控( Continuous Phase Frequency Shift Keying , 筒称 CPFSK )调制方式的通信产品领域。 背景技术
对于任何一种无线通信产品,位同步的实现一直都是一个关键难点。 因为 数字信息是一串相继的码元序列, 由于噪声和码间干扰的存在, 为了获得可靠 的判决结果, 降低系统的误码率, 要求在每个码元周期的最佳采样时刻(眼图 张开最大位置 )对相干解调出的基带信号进行采样判决, 以还原出整齐规则的 信号码流。 由于信号存在传输延时等因素, 这个时刻往往是未知的, 需要通过 位同步定时恢复来获得。因此,位同步定时恢复对解码的正确性有着重要意义。
在数字通信中,位同步是最基本的同步,位同步的基本含义就是接收端和 发射端的时钟信号必须同频同相,这样接收端才能正确接收和判决发送端送来 的每一码元。位同步是无线通信终端物理层的关键技术,是解调算法的重点和 难点, 对最终的解调性能有重要的影像, 如果不能解决位同步问题, 就无法最 终正确解调出信息, 也就是接收端无法识别发送端发送的信息。
而目前存在的最常用位同步技术为最大似然估计,其基于快速傅立叶变换 ( Fast Fourier Transform,筒称 FFT )算法的同步技术,为迟早门( early-late gate ) 位同步技术。 其中最大似然估计理论上可以达到最优, 但运算量也最复杂, 不 适合数字实现。 FFT算法目前主要应用于正交频分复用 ( orthogonal frequency division multiplexing, 筒称 OFDM )通信系统中, 对接收到的信号必须进行一 些非线性的操作以获得所需的定时线谱。例如在传统的非数据辅助定时恢复系 统中, 在对接收信号作相应的非线性处理后, 利用窄带带通滤波器或锁相环
( phase locked loop, 筒称 PLL ) 来提取时钟信号, 这种方法也称之为单频滤 波法 (Tone filtering ), 其运算量较大。 迟早门技术目前主要应用于相移键控
( phase shift keying ,筒称 PSK )和正交相移键控 ( quadrature phase shift keying , 筒称 QPSK )调制方式的通信系统,因此需要寻找一种合适的算法来解决 DMR 面临的同步问题。
DMR是国际 ETSI组织正在完善的最近数字专业通信标准, 由于还没有 完全成型现在进行跟踪就可以与国外大公司在技术上保持同步,避开专利技术 壁垒, 相当于站在同一起跑线上。 另外, 数字无线通信关键部分核心技术及芯 片是我国目前的弱项。
由于 DMR标准规定了较为特殊的调制指数( 0.27 ) , 使得 DMR的同步实 现更加困难,公开资料几乎没有相关的方案可供参考,给算法的设计带来^艮大 的难度。 现有的 DMR收发系统由本公司自主研发, 可完整实现调制解调同步 等功能。 但是 DMR目前采用的位同步算法由于实现技术上受限于信源, 当信 源不满足要求时即会出现丟帧现象, 并且位同步时间较长, 最遭的情况是一直 同步不上, 由此导致通信不成功。
现有的 DMR位同步算法如下:首先从 [+1 +3 -1 -3]四路信号中预设一路作 为同步判决, 此处以 +1路为例。 设任意时刻输入信号为:
ei(wQ +wg +nwct) 其中: W。为初始相位, ^为当前时刻以前的相位累加值, ^为与调制电 平相应的调制相位, 其中 n为调制电平, ^为调制电平 1相对应的调制相位。
首先, 将输入信号做延时处理, 得到四路不同延时信号分别为无延时、 延 时 2位、 延时 4位和延时 6位。 在一个符号周期内与 4路本地信号相乘, 然后 相乘后的输出值在符号周期内累加求平均, 将结果的绝对值输出。 可知, 当符 号 +1来临时,正确位同步的一路输出的值最大且为 1 ,其他三路输出的值都小 于 1。假设此时调制数据为 +1 , 符号采样点^^ ^ 为 8。 则正确位同步的一路对 应的输出值为:
_ 1 8 j(Wo +We + WVN ) ~ jW/N Ί
\ ^ / N sample * / N sample _ 、
½ 一 绝对值输出为:
e =1 当下一符号不为 +1时, 其他三路的输出值可以证明均小于 1 , 此处不再列 出, 位同步过程如图 1所示。
现有技术方案的主要缺点: 现有位同步算法由于在信源的特点上进行位同 步, 因此其位同步效果受限于信源, 当信源出现连续 "1" 或不出现 "1" 时, 位同步出错的概率较大, 由此引起丟帧和位同步时间较长。 当前位同步算法抗 噪声性能不够理想, 当信噪比较低时, 性能有明显的下降。
发明内容 本发明的目的在于针对现有技术的 DMR位同步算法的改进,要解决算法 性能受限于信源形式的问题,提供一种改进的位同步数字化的方法,使该方法 在随机信源下也能运行良好, 满足实际情况的要求, 进一步改善原 DMR位同 步算法在噪声较大时性能恶化的问题。
本发明解决其技术问题所采用的技术方案是:构造一种改进的位同步数字 化的方法, 针对任一随机信源, 所述方法包括下列步骤:
对输入的信号序列进行间隔延时,该信号序列包括至少一路以上的输入信 号;
将每一路的输入信号在一个符号周期内分别与至少一个以上的本地通道 的输入信号相乘, 相乘后的输出值在符号周期内累加并求均值;
将每一路输入信号的每一通道的所述均值进行比较,并选取均值最大的一 路均值及其对应的解码输出; 以及
在预设的时间窗长度,对每一路的最大均值进行积分,并将每一路的积分 值进行比较, 选取积分值最大一路的对应的解码输出。
本发明中, 若在延时为 0时依次接收到数据 +1 , +3, -1 , 取时间窗长度为 2, 则延时为 0的一路的判决输出为: 、 、、 、、 延时为 2的一路的判决输出为:
+∑e ― - e ― ) < 2 ,
Figure imgf000006_0001
延时为 4的一路的判决输出为:
'·>
Figure imgf000006_0002
延时为 6的一路的判决输出为:
、 )
Figure imgf000006_0003
本发明中,若采用四路的复数信号输入,则所述信号序列间隔延时设置分 别设置为: 第一路为无延时数据流, 第二路为延时 2个符号周期, 第三路为延 时 4个符号周期以及第四路为延时 6个符号周期,使得将并行同步输入源转换 成串行输入源。
本发明中, 还包括符号内 8个点的正余弦相位生成步骤, 具体为: 产生地址, 输出 0 - 7个循环, 送入下一级 ROM存储器中作为地址; ROM存储器输入为 4位地址, 输出 12位三角函数值。
本发明中, 还包括延时信号合并的步骤, 具体为:
将无延时、延时 2个符号周期、时 4个符号周期以及延时 6个符号周期的 四路 I、 Q信号合并成一路输出。
本发明中, 还包括时钟延时的步骤, 具体为:
将四路的时钟加上固定延时, 使其与数据保持同步。
本发明中, 还包括累加的步骤, 具体为: 将运算的相关结果在符号内的 8个点累加, 并将累加结果输出。
本发明中, 还包括将四路延时的 +1/+3/-1/-3路的相关值合并串行输出。 本发明中, 还包括并串转换步骤, 具体为:
串行的共 16路相关值并行输出并进行串并转换后, 在相应的时钟信号到 来的时候将串行数据的值赋给并行输出的某一路。
本发明中, 还包括位同步判决的步骤, 具体为:
比较 +1、 +3、 -1、 -3四路的相关值, 将最大的一路的相关值输出。
本发明的技术方案中, 其判决方法与信源形式无关, 不依赖于某一符号的 出现,信源形式的变化并不会影响位同步的质量,在随机信源的情况下运行性 能良好, 改进后的 DMR位同步方法最大限度的拉大了正确判决与错误判决间 的距离,有利于对抗接收信号质量下降导致的位判决模糊,抗噪声性能有大幅 提1¾。 附图说明
图 1是现有技术中 DMR通信系统位同步结构示意图;
图 2是本发明中 DMR通信系统位同步结构示意图;
图 3是本发明中 DMR位同步模块的结构示意图;
图 4是本发明的时序关系示意图;
图 5是本发明的合并串行输出示意图;
图 6是本发明的时序关系示意图;
图 7是本发明的串并转化对应关系的示意图;
图 8是本发明的位同步判决的模块示意图;
图 9是本发明的输出延时中相关值最大一路的模块示意图。 具体实施方式 本发明的一种改进的位同步数字化的方法,是针对任一随机信源, 方法包 括: 对输入的信号序列进行间隔延时, 该信号序列包括至少一路以上的输入信 号;将每一路的输入信号在一个符号周期内分别与至少一个以上的本地通道的 输入信号相乘,相乘后的输出值在符号周期内累加并求均值; 将每一路输入信 号的每一通道的所述均值进行比较,并选取均值最大的一路均值及其对应的解 码输出; 以及在预设的时间窗长度, 对每一路的最大均值进行积分, 并将每一 路的积分值进行比较, 选取积分值最大一路的对应的解码输出。
其中,若采用四路的复数信号输入, 则所述信号序列间隔延时设置分别设 置为: 第一路为未延时数据流, 第二路为延时 2个符号周期, 第三路为延时 4 个符号周期以及第四路为延时 6个符号周期,使得将并行同步输入源转换成串 行输入源。
由于现有技术中 DMR通信系统位同步的思想为, 将 +1、 +3、 -1、 -3中的 一路取出 (比如 +1 ), 分别比较四路不同延时下此路的值, 出现最大值的一路 的延时即对应于最终位同步延时的选取。
本发明对其改进后, 不再选取某符号对应的固定一路作为位同步的判决, 而是在每个符号来临时, 将其对应的最大值 ζ输出, 取一定的时间窗长度, 对 这些值求和得到∑ ζ 。对四路不同延时的∑ ζ值进行比较, 最大的一路对应于 正确的位同步判决。
现举例说明改进后 DMR位同步的实现过程:
筒便起见, 假设在延时为 0时依次接收到数据 [+1 , +3, -1] , 取窗函数长 度为 2。 则延时为 0的一路的判决输出为:
Figure imgf000008_0001
延时为 2的一路的判决输出为: 漏
•e )+
Figure imgf000008_0002
( g
- e +J - e ) <2 延时为 4的一路的判决输出为:
Figure imgf000008_0003
延时为 6的一路的判决输出为:
Figure imgf000009_0001
由于篇幅有限, 不等式的推导不再给出, 由上述结果可见, 有正确位同步 延时的一路的判决输出要大于其他三路的判决输出,故本发明可以选择出正确 的位同步延时。
本发明中,窗函数的长度可以根据实际情况灵活选取。增加窗函数的长度, 可以使得位同步判决更加保险, 降低出错的概率, 但会稍微增大运算量。 原则 上窗函数的长度要大于可能出现的连续相同符号的最大数量。 由于实际情况 中, 符号的出现都服从一定的概率分布, 不会出现长时间的相同符号, 所以窗 函数不需要取的很长。
本发明改进后的 DMR位同步算法, 其判决方法与信源形式无关, 不再依 赖于某一符号的出现,信源形式的变化并不会影响位同步的质量。 同时最大限 度的拉大了正确判决与错误判决间的距离,有利于对抗接收信号质量下降导致 的位判决模糊。
并且, 经多次仿真测试, 改进后的 DMR位同步算法在性能上有较大幅度 的提升。 现有 DMR位同步算法、 改进后 DMR位同步以及手动位同步情况下 现有 DMR通信系统在不同高斯白噪声环境下的误码率如表一所示。通过表一 数据可看出, 改进后的位同步算法性能有 4艮大提升, 而且跟手动位同步相当。 改进后的 DMR位同步方法的具体实现方案如图 2所示。
表一 不同位同步算法下的 DMR通信系统性能对比
Figure imgf000009_0002
无噪声 0 0 930 0 0 950 0. 0128 12 940
SNR=80dB 0 0 930 0 0 950 0. 0128 12 940
SNR=60 dB 0 0 930 0 0 950 0. 0128 12 940
SNR=30 dB 0 0 930 0 0 950 0. 0277 26 940
SNR=20 dB 0 0 930 0 0 950 0. 1074 101 940
SNR=10 dB 0 0 930 0 0 950 0. 1745 164 940
SNR=8 dB 0 0 930 0 0 950 0. 216 203 940
SNR=5 dB 0 0 930 0 0 950 0. 2628 247 940
SNR=2 dB 0 0 930 0 0 950 0. 317 298 940
SNR=0 dB 0 0 930 0. 0032 3 950 0. 333 313 940
SNR=-5 dB 0. 0441 41 930 0. 0474 45 950 0. 3979 374 940
Figure imgf000010_0001
DMR基带位同步模块如图 3所示,下面分模块逐步给出解调功能的实现。 1.相位生成,此模块生成符号内 8个点的正余弦相位。由产生地址和 ROM 存储器两部分组成。
1.1. 产生地址。
此模块完成产生地址的功能。 输出为 0-7循环, 送入下一级 ROM中作为 地址。
1.2. ROM存储器
输入为 4位地址, 输出 12位三角函数值。 共有四个 ROM, 分别存储了调 制数据分别为 1和 3时符号内 8个点的正弦、 余弦值。 存储深度 16, 存储位 宽 12。 存储对应关系如下表:
Figure imgf000010_0002
,5x0.27;r、 ,6x0.27;r、 x0.27^-, ,8x0.27;r、 廳 2 UU¾l ) UU¾l ) UU¾l ) UU¾l )
8 8 8 8
Addr=l Addr=2 Addr=3 Addr=4
. ,0.8br、 . ,2x0.8br、 . ,3x0.8br、 . ,4x0.8br、
ROM 3 sm( 8 ) sin( ) sm( 8 ) sin( )
8 8
Addr=5 Addr=6 Addr=7 Addr=8
. ,5x0.8br、 . ,6x0.8br、 . ,7x0.8br、 . ,8x0.8br、
ROM 3 sin( ) sin( ) sm( 8 ) sin( )
8 8 8
Addr=l Addr=2 Addr=3 Addr=4
Ό.81Λ-Χ ,2x0.8br、 ,3x0.8br、 ,4Χ0·81;Γ、 廳 4 cos( 8 ) cos( ) cos( 8 ) cos( )
8 8
Addr=5 Addr=6 Addr=7 Addr=8
,5χ0·81;τ、 ,6χ0·81;τ、 ,7x0.8br、 ,8x0.8br、 廳 4 cos( ) cos( ) cos( ) cos( )
8 8 8 8
2. 延时信号合并。 此模块将无延时、 延时 2位、 延时 4位、 延时 6位的四路 I、 Q信号合并 成一路输出。 合并后, Clk_38_4k对应无延时的 I、 Q信号; Clk_38_4k_delayl 对应延时 2位的 I、 Q信号; Clk_38_4k_delay2对应延时 4位的 I、 Q信号; Clk_38_4k_delay3对应延时 6位的 I、 Q信号。 其时序关系如图 4所示。
3. 时钟延时。
Figure imgf000011_0001
Clk_38_4k_delayl_dffl Clk_38_4k_delayl延时后的输出
Clk_38_4k_delay2_dffl Clk_38_4k_delay2延时后的输出
Clk_38_4k_delay3_dffl Clk_38_4k_delay3延时后的输出
此模块完成将四路 38.4kHz的时钟加上固定延时, 使其与数据保持同步。 此程 序完成将四路时钟信号 Clk_38_4k、 Clk_38_4k_delayl、 Clk_38_4k_delay2、 Clk_38_4k_delay3分别加上 3倍使能时钟周期的延时, 以抵消数据乘法运算的 2个时钟周期的延时以及加法运算的 1个时钟周期的延时, 使时钟与数据保持 同步。
4. 累加模块。
Figure imgf000012_0001
Phase3_sub_acc(14:0) +3路求差累加后输出
Phase_3_add_acc(14:0) -3路求和累加后输出
Phase_3_sub_acc( 14:0) -3路求差累加后输出
此模块完成将前面运算的相关结果在符号内的 8个点累加,将累加结果输 出。 此模块有四个, 分别针对不同延时的四路信号。
5. 将四路延时的 +1/+3/-1/-3路的相关值合并串行输出。
此模块实现将四路延时, 每路分 +1/-1/+3/-3 四路, 每路分和、 差两路共 4*4*2=32路信号合并成串行的两路输出。 合并串行输出示意 (如图 5所示)。 此模块实现按此示意图的顺序由左到右将 16路输入合并成一路输出。 其时序 关系如图 6所示。
6. 并串转换。
Figure imgf000013_0001
Phase_ 1 _squ_delay 1(15:0) -1路延时 2位数据输出
Phase_3_squ_delay 1(15:0) -3路延时 2位数据输出
Phase 1 _squ_delay 2 (15:0) +1路延时 4位数据输出
Phase3_squ_delay2(l 5: 0) +3路延时 4位数据输出
Phase_ 1 _squ_delay2(l 5:0) -1路延时 4位数据输出
Phase_3_squ_delay2(l 5: 0) -3路延时 4位数据输出
Phase 1 _squ_delay3 (15:0) +1路延时 6位数据输出
Phase3_squ_delay3 (15:0) +3路延时 6位数据输出
Phase— 1 _squ_delay3( 15:0) -1路延时 6位数据输出
Phase_3_squ_delay3( 15:0) -3路延时 6位数据输出
此模块实现将串行的共 16路相关值并行输出。 串并转换对应关系如图 7 所示。此模块按此示意图的顺序将串行输入按从左到右的顺序并行输出。其实 现过程有如下四个相同的模块组成:在相应的时钟信号到来的时候将串行数据 的值赋给并行输出的某一路。
7. 位同步判决 (如图 8所示)。
此模块实现根据输入的 16路相关值做出位同步判断。 内部由 decode_cmp 模块和 cmp_decode模块组成。
7.1. decode_cmp模块。
decode_cmp模块实现比较 +1、 -1、 +3、 -3 四路的相关值, 将最大的一路 的相关值输出的功能。 Syn_cmp模块中共有四个 decode_cmp模块, 它们分别 对应于无延时、 延时 2位、 延时 4位、 延时 6位, 每个模块负责选出相应的延 时中相关值最大的一路。 其内部实现(如图 9所示)。
7.2. cmp_decode模块。
cmp_decode模块负责实现从四路不同延时的相关值中选出 1路最大的,将 其相关值输出。 首先在四路相关值中两两比较,选出两路较大的再进行一次比 较, 将最大的一路输出。 此路对应的即为正确的位同步。 至此, 位同步功能实 现完毕。
由此可知, 本发明的判决方法与信源形式无关, 不依赖于某一符号的出现, 信源形式的变化并不会影响位同步的质量, 在随机信源的情况下运行性能良 好, 改进后的 DMR位同步方法最大限度的拉大了正确判决与错误判决间的距 离,有利于对抗接收信号质量下降导致的位判决模糊,抗噪声性能有大幅提高。

Claims

权 利 要 求 书
1、 一种改进的位同步数字化的方法, 其特征在于, 针对任一随机信源, 所述方法包括下列步骤:
对输入的信号序列进行间隔延时,该信号序列包括至少一路以上的输入信 号;
将每一路的输入信号在一个符号周期内分别与至少一个以上的本地通道 的输入信号相乘, 相乘后的输出值在符号周期内累加并求均值;
将每一路输入信号的每一通道的所述均值进行比较,并选取均值最大的一 路均值及其对应的解码输出; 以及
在预设的时间窗长度,对每一路的最大均值进行积分,并将每一路的积分 值进行比较, 选取积分值最大一路的对应的解码输出。
2、 根据权利要求 1所述的改进的位同步数字化的方法, 其特征在于, 若 在延时为 0时依次接收到数据 +1 , +3 , -1 , 取时间窗长度为 2, 则延时为 0的 一路的判决输出为:
Figure imgf000016_0001
延时为 2的一路的判决输出为
· 十 L · e ) 厶
Figure imgf000016_0002
延时为 4的一路的判决输出为:
Figure imgf000016_0003
X )、
+∑e - e ) < 2 ;
延时为 6的一路的判决输出为:
Figure imgf000017_0001
3、根据权利要求 1或 2所述的改进的位同步数字化的方法,其特征在于, 若采用四路的复数信号输入, 则所述信号序列间隔延时设置分别设置为: 第一 路为无延时数据流, 第二路为延时 2个符号周期, 第三路为延时 4个符号周期 以及第四路为延时 6个符号周期, 使得将并行同步输入源转换成串行输入源。
4、 根据权利要求 2所述的改进的位同步数字化的方法, 其特征在于, 还 包括符号内 8个点的正余弦相位生成步骤, 具体为:
产生地址, 输出 0 - 7个循环, 送入下一级 ROM存储器中作为地址; ROM存储器输入为 4位地址, 输出 12位三角函数值。
5、 根据权利要求 3所述的改进的位同步数字化的方法, 其特征在于, 还 包括延时信号合并的步骤, 具体为:
将无延时、延时 2个符号周期、时 4个符号周期以及延时 6个符号周期的 四路 I、 Q信号合并成一路输出。
6、 根据权利要求 2所述的改进的位同步数字化的方法, 其特征在于, 还 包括时钟延时的步骤, 具体为:
将四路的时钟加上固定延时, 使其与数据保持同步。
7、 根据权利要求 2所述的改进的位同步数字化的方法, 其特征在于, 还 包括累加的步骤, 具体为:
将运算的相关结果在符号内的 8个点累加, 并将累加结果输出。
8、 根据权利要求 2所述的改进的位同步数字化的方法, 其特征在于, 还 包括将四路延时的 +1/+3/-1/-3路的相关值合并串行输出。
9、 根据权利要求 2所述的改进的位同步数字化的方法, 其特征在于, 还 包括并串转换步骤, 具体为:
串行的共 16路相关值并行输出并进行串并转换后, 在相应的时钟信号到 来的时候将串行数据的值赋给并行输出的某一路。
10、根据权利要求 2所述的改进的位同步数字化的方法, 其特征在于, 还 包括位同步判决的步骤, 具体为:
比较 +1、 +3、 -1、 -3四路的相关值, 将最大的一路的相关值输出。
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