WO2010038476A1 - 伝送入力回路 - Google Patents
伝送入力回路 Download PDFInfo
- Publication number
- WO2010038476A1 WO2010038476A1 PCT/JP2009/005102 JP2009005102W WO2010038476A1 WO 2010038476 A1 WO2010038476 A1 WO 2010038476A1 JP 2009005102 W JP2009005102 W JP 2009005102W WO 2010038476 A1 WO2010038476 A1 WO 2010038476A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/54—Systems for transmission via power distribution lines
- H04B3/548—Systems for transmission via power distribution lines the power on the line being DC
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2203/00—Indexing scheme relating to line transmission systems
- H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
- H04B2203/5462—Systems for power line communications
- H04B2203/547—Systems for power line communications via DC power distribution
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2209/00—Arrangements in telecontrol or telemetry systems
- H04Q2209/80—Arrangements in the sub-station, i.e. sensing device
- H04Q2209/82—Arrangements in the sub-station, i.e. sensing device where the sensing device takes the initiative of sending data
- H04Q2209/823—Arrangements in the sub-station, i.e. sensing device where the sensing device takes the initiative of sending data where the data is sent when the measured values exceed a threshold, e.g. sending an alarm
Definitions
- the present invention relates to a transmission input circuit provided in a master unit such as a receiver that detects a transmission current from a slave unit such as a fire detector connected via a transmission line that also serves as a power supply line.
- sensors such as a fire detector and a gas detector are connected to a transmission line from a receiver to monitor abnormalities such as fire and gas leakage (for example, see Patent Documents 1 and 2).
- a digital signal which is a downlink signal such as control information is transmitted from the receiver to the terminal in a voltage mode.
- the terminal transmits a digital signal that is an upstream signal such as sensor information to the receiver in a current mode.
- FIG. 15 shows a conventional monitoring system. As shown in the figure, transmission lines 102a and 102b that also serve as power supply lines are drawn out from a receiver 100 that is a master unit, and an analog type sensor 104 and a repeater 106 that are slave units are connected. A unique address is set for each of the analog sensor 104 and the repeater 106.
- the analog sensor 104 detects the smoke concentration or ambient temperature analog value associated with the occurrence of a fire, and transmits smoke concentration data or temperature data to the receiver 100.
- the receiver 100 determines whether or not a fire has occurred based on the smoke density data or the temperature data, and issues a fire alarm if it is determined that a fire has occurred.
- Sensor lines 108a and 108b are drawn out from the repeater 106, and a plurality of on / off type sensors 110 having no transmission function are connected as loads.
- an alarm current flows to the repeater 106 via the sensor lines 108a and 108b.
- fire alarm data is transmitted from the repeater 106 toward the receiver 100. Then, the receiver 100 issues a fire alarm.
- the receiver 100 sequentially designates the slave unit addresses and sends a polling downlink signal to each slave unit (the analog type sensor 104 and the repeater 106) in the voltage mode.
- the slave unit that has received this polling downlink signal determines its own address and sends back a transmission current, which is an uplink signal indicating a normal state, to the receiver 100.
- FIG. 16 is a diagram showing the receiver 100, the analog sensor 104, and the repeater 106 in the conventional system shown in FIG. 15 by an equivalent circuit.
- the repeater 106 supplies a power to the on / off sensor 110 connected as a load and supplies a steady operating current. Therefore, the repeater 106 can be regarded as a load 122 indicated by a resistor. For this reason, the load current Iz corresponding to the load 122 constantly flows through the transmission lines 102a and 102b.
- the analog type sensor 104 includes a constant current source 112 and a switch 114.
- the CPU 116 in response to polling from the receiver 100, the CPU 116 sends an upstream signal indicating normality back to the receiver 100 as a current pulse signal having a predetermined bit length.
- the current pulse signal transmitted from the analog type sensor 104 is input to the transmission input circuit 118 of the receiver 100, and a current detection voltage pulse signal proportional to the current pulse signal is generated and sent to the CPU 120.
- the CPU 120 that has read the current detection voltage pulse signal recognizes that the analog sensor 104 is normal. That is, the transmission input circuit 118 determines whether or not there is a transmission current from the analog sensor 104 as a slave unit in a state where the load current Iz from the load 122 is flowing through the transmission lines 102a and 102b that also serve as power supply lines. To detect.
- FIG. 17 is a circuit diagram of a conventional transmission input circuit 118 provided in the receiver 100 shown in FIG.
- a predetermined power supply voltage Vc is applied to the transmission line 102a, while the signal line 102b side is connected to the current detection resistor R11 via the diode D11.
- the repeater 106 and the analog sensor 104 are connected to the transmission lines 102a and 102b, and depending on the load 122 of the repeater 106 at idle timing when the transmission current Ia does not flow.
- a load current Iz flows.
- the analog sensor 104 outputs a transmission signal, the transmission current Ia flows on top of the load current Iz.
- a detection voltage corresponding to the line current generated at both ends of the current detection resistor R 11 shown in FIG. 17 is applied to the negative input terminal of the comparator 122.
- a capacitor C11 is connected to the positive input terminal of the comparator 122, and the capacitor C11 is further connected to the input side of the diode D11 via the switch SW11.
- the switch SW11 is switched by the CPU 120 at idle timing when the transmission current Ia from the slave unit such as the analog sensor 104 does not flow, and the forward current drop voltage of the diode D11 is added to the load current detection voltage Vz of the current detection resistor R11.
- FIG. 18 is a time chart showing signal waveforms at various parts in FIG. 18A shows the input voltage to the comparator 112, and FIG. 18B shows the sample timing of the capacitor C11 by the switch SW11.
- the load current detection voltage Vz based on the load current Iz flowing through the transmission lines 102a and 102b is input as the base voltage.
- the reference voltage Vr obtained by adding the threshold voltage Vf, which is the forward drop voltage of the diode D11, to the load current detection voltage Vz of the current detection resistor R11 in the capacitor C11 by switching of the switch SW1 at the idle timing without the transmission current Ia. Is sampled and held.
- a transmission current detection voltage Va corresponding to the transmission current Ia is generated in the current detection resistor R11 in a form that is added to the load current detection voltage Vz.
- FIG. 19 is a time chart showing the time axis of FIG. A pulse signal is sent from the slave unit side by a transmission current Ia at a constant cycle.
- the load voltage Vz corresponding to the load current Iz is shown as a constant voltage, actually, the load current Iz changes gently according to the environmental temperature or the like.
- JP-A-9-91576 Japanese Patent Laid-Open No. 6-301876
- the threshold voltage Vf for detecting the transmission current from the slave unit is determined depending on the forward voltage Vf of the diode D11, so that an arbitrary threshold value cannot be set.
- a reference voltage Vr obtained by adding a threshold voltage Vf which is a forward drop voltage of the diode D11 as an analog voltage is held in the capacitor C11.
- the holding voltage of the capacitor C11 is increased with time due to a leakage current or the like. Change. Therefore, there is a problem that the sample and hold must be frequently performed.
- the present invention has been made in view of the above circumstances, and it is possible to arbitrarily set a threshold voltage for detecting transmission current, and there is no fluctuation due to temperature or time, and the presence or absence of transmission current from a slave unit is accurately determined. It is an object of the present invention to provide a transmission input circuit that can be detected easily.
- the transmission input circuit of the present invention is a transmission input circuit of a master unit that detects the presence or absence of transmission current from a slave unit in a state where a load current from a load is flowing through the transmission line that also serves as a power supply line.
- a current detection resistor that inputs a line current flowing through the transmission line to generate a line current detection voltage; and a threshold voltage that causes a predetermined reference current from a constant current circuit to flow through the current detection resistor by switching.
- a digital variable resistor circuit that generates an arbitrary reference voltage by setting a resistance value according to a digital value; and the line current detection voltage generated by the current detection resistor is input to one of input terminals.
- the reference voltage generated by the digital variable resistor circuit is input to the other input terminal, and a component exceeding the reference voltage in the line current detection voltage is transmitted.
- a comparator that outputs as a detection signal; the switch is turned on at a vacant timing when the transmission current from the slave unit does not flow, the reference current flows from the constant current circuit to the current detection resistor, and corresponds to the load current
- a target adjustment voltage obtained by adding a threshold voltage corresponding to the reference current to the detected load current detection voltage is generated in the current detection resistor, and the reference voltage output from the digital variable resistor is the target adjustment voltage.
- An adjustment processing unit that adjusts the digital value so as to match the voltage.
- the digital variable resistance circuit is input from a series resistance array to which a predetermined internal power supply voltage is applied to both ends, the adjustment processing unit, and the digital value
- a single digital variable resistor having a wiper terminal that outputs a voltage that is varied according to the adjustment value; the digital value that the adjustment processing unit applies to the digital variable resistor is changed by one bit.
- a configuration may be adopted in which the output of the comparator is adjusted to a digital value to be inverted or a digital value just before the inversion.
- the adjustment processing unit when the output of the comparator at the start of adjustment is high level, the adjustment processing unit causes the digital value to invert the high level to low level. While adjusting the digital value to be applied to the digital variable resistor to the digital value when inverted from the high level to the low level or the digital value immediately before the inversion, When the output of the comparator at the start of adjustment is at a low level, the digital value is changed in units of 1 bit in a direction to invert the low level to a high level, and is applied to the digital variable resistor. Adopting a configuration that adjusts the digital value to the digital value when inverted from the low level to the high level or just before the inversion. It may be.
- the digital variable resistor circuit is input from a first series resistor array to which a predetermined internal power supply voltage is applied to both ends, the adjustment processing unit, and the A first digital variable resistor for coarse adjustment having a first wiper terminal that outputs a voltage varied according to a digital value; a second series resistor array to which the predetermined internal power supply voltage is applied at both ends; A second digital variable resistor for fine adjustment having a second wiper terminal that is input from the adjustment processing unit and outputs a voltage that is varied according to the digital value; and the first wiper terminal is connected to the comparator A first resistor provided on a line connected to the other input terminal; a second resistor provided on the line connecting the second wiper terminal to the other input terminal of the comparator; A second resistor having a resistance value larger than that of the first resistor; and the adjustment processing unit is configured to be connected to the first digital variable resistor so that the reference voltage and the target adjustment voltage substantially match.
- a configuration may be adopted in which after adjusting the digital value
- the adjustment processing unit adjusts the position of the second wiper terminal of the second digital variable resistor when adjusting the first digital variable resistor. You may employ
- the digital variable resistor circuit is input from a first series resistor array to which a predetermined internal power supply voltage is applied to both ends, the adjustment processing unit, and the A first digital variable resistor for coarse adjustment having a first wiper terminal that outputs a voltage varied according to a digital value; a second series resistor array to which the predetermined internal power supply voltage is applied at both ends; A second digital variable resistor for fine adjustment having a second wiper terminal that is input from the adjustment processing unit and outputs a voltage that is varied according to the digital value; and the first wiper terminal is connected to the comparator A first resistor provided on a line connected to the other input terminal; a second resistor provided on the line connecting the second wiper terminal to the other input terminal of the comparator; A second resistor having a resistance value greater than the first resistor; a first inverter having an input connected to the adjustment processing unit and an output connected to a ground-side terminal of the second series resistor array; A second inverter, to which the output from
- the second digital variable resistor After adjusting the digital value to be applied to the first digital variable resistor so as to substantially match, the second digital variable resistor is adjusted so that the reference voltage matches the target adjustment voltage.
- a low level signal is inputted to the first inverter and becomes the internal power supply voltage.
- the internal power supply voltage is applied to the second resistor through the first digital variable resistor by obtaining the output of the level signal, and the third resistor is activated by the output of the low level signal from the second inverter.
- a circuit connected to the ground side and connected in parallel to the second resistor and composed of the third resistor and the fourth resistor is formed, whereby the voltage at the series connection point is determined by the position of the second wiper terminal.
- one end of the second digital variable resistor is connected to the ground side to be adjustable, and by obtaining an output of a high level signal from the second inverter, the internal power supply voltage and A circuit for connecting the third resistor and the fourth resistor in series between the grounds is formed, whereby the voltage at the series connection point of the third resistor and the fourth resistor is reduced to 1 ⁇ 2 of the internal power supply voltage.
- Another transmission input circuit of the present invention is a transmission input of a master unit that detects the presence or absence of a transmission current from a slave unit in a state where a load current from a load is flowing through the transmission line that also serves as a power supply line.
- a current detection resistor that inputs a line current flowing through the transmission line to generate a line current detection voltage; and a threshold value by passing a predetermined reference current from the constant current circuit to the current detection resistor by switching.
- the switch is turned on at a vacant timing when the transmission current from the machine does not flow, the reference current is supplied from the constant current circuit to the current detection resistor, and the reference current is detected with respect to the load current detection voltage corresponding to the load current.
- a target adjustment voltage obtained by adding a threshold voltage corresponding to a current is generated in the current detection resistor, and further, the digital value is adjusted so that the reference voltage output from the DA converter matches the target adjustment voltage.
- the constant current circuit In the transmission input circuit according to (1) or (7), the constant current circuit generates the threshold voltage that is a half of a transmission current detection voltage corresponding to the transmission current.
- a configuration may be adopted in which
- the digital variable resistor is connected to the comparator with the reference voltage for detecting the presence or absence of the transmission current from the slave unit in a state where the load is carrying the load current through the transmission line.
- the reference voltage does not change with the passage of time and the transmission current sent from the slave unit can be accurately detected as compared with the conventional configuration in which the capacitor performs sample hold.
- the reference voltage set by the digital variable resistor does not change, if the load current detection voltage is constant, the adjustment of the digital variable resistor is not necessary or the frequency of adjustment can be greatly reduced. Therefore, the processing burden for adjusting the reference voltage can be reduced.
- the transmission current is accurately detected without being affected by the fluctuation of the load current by adjusting the digital variable resistor using idle timing when the transmission current does not flow. be able to.
- the first digital variable resistor for coarse adjustment and the second digital variable resistor for fine adjustment are provided, and the digital voltage is adjusted by adjusting the reference voltage in two steps, coarse adjustment and fine adjustment.
- the processing time required for one adjustment of the resistor can be shortened.
- the second wiper terminal of the second digital variable resistor for fine adjustment is provided during the coarse adjustment.
- the process of fixing the position of the second wiper terminal of the second digital variable resistor for fine adjustment to the midpoint position is not the adjustment of the second digital variable resistor, but two inverters.
- the adjustment process can be performed easily and at high speed.
- 6 is a flowchart showing a reference voltage adjustment process in the embodiment.
- It is a circuit diagram of the receiver provided with the transmission input circuit which concerns on 4th Embodiment of this invention.
- It is a system block diagram which shows the conventional monitoring system. It is the block diagram which showed the repeater and the analog type sensor in the conventional monitoring system with the equivalent circuit.
- 18 is a time chart showing a comparator input voltage and sample hold timing in the conventional transmission input circuit shown in FIG. It is a time chart which shows the timing of the reception voltage and sample hold in the conventional transmission input circuit when load current is stable.
- FIG. 1 is a block diagram showing the structure of a receiver in a monitoring system to which the present invention is applied, together with an analog type sensor and a repeater.
- an analog type sensor 14 and a repeater 16 that are slave units are connected to transmission lines 12 a and 12 b that are drawn from a receiver 10 that is a master unit toward a warning area.
- the analog type sensor 14 and the repeater 16 have a transmission function for transmitting and receiving an upstream signal and a downstream signal to and from the receiver 10.
- a unique address having a maximum address of, for example, 127 addresses is assigned in advance for each transmission line.
- the analog type sensor 14 detects the density (smoke density) or temperature (for example, room temperature) of smoke generated by a fire, and transmits the detected value to the receiver 10 as analog data.
- the presence or absence of a fire is determined from the received analog data of smoke density or temperature, and an alarm is issued if it is determined that a fire has occurred.
- the repeater 16 is provided to connect a plurality of on / off type sensors 20 having no transmission function to the transmission lines 12a and 12b.
- the repeater 16 has a transmission function with the receiver 10.
- Each on / off type sensor 20 is connected to the sensor lines 18a and 18b drawn from the repeater 16.
- the on / off type sensor 20 detects a fire, it sends an alarm current between the sensor lines 18a and 18b, and the repeater 16 receives this alarm current, and fire alarm data indicating the occurrence of a fire is received by the receiver 10. Transmit to.
- Downlink signals from the receiver 10 to the analog type sensor 14 and the repeater 16 as slave units are transmitted in the voltage mode.
- the receiver 10 transmits the polling signal by sequentially specifying the slave unit addresses at a constant polling cycle.
- This polling signal is transmitted as a voltage pulse that changes the voltage between the transmission lines 12a and 12b between 18 volts and 30 volts, for example.
- the upstream signal from the analog type sensor 14 and the repeater 16 to the receiver 10 is transmitted in the current mode. That is, a signal current is caused to flow between the transmission lines 12a and 12b at the timing of bit 1 of the transmission data, and the upstream signal is transmitted to the receiver 10 as a so-called current pulse train. At this time, the transmission current flows.
- the transmission lines 12a and 12b are also used as power supply lines for the analog type sensor 14 and the repeater 16 as slave units. That is, the transmission lines 12a and 12b vary the supply voltage in the range of 18 volts to 30 volts when the downstream signal is transmitted in the voltage mode, and a voltage supply of 18 volts is provided at the minimum. That is, power is continuously supplied from the receiver 10 as the master unit to the analog type sensor 14 and the repeater 16 as the slave units.
- the power supplied via the transmission lines 12 a and 12 b is also supplied via the repeater 16 to the sensor lines 18 a and 18 b drawn from the repeater 16. As a result, electric power is supplied to each on / off type sensor 20 via the sensor lines 18a and 18b.
- the receiver 10 is provided with a CPU 22 and a transmission circuit unit 24 corresponding to the CPU 22.
- the transmission lines 12a and 12b are drawn from the transmission circuit unit 24.
- the transmission circuit unit 24 is provided with a transmission output circuit 26 and a transmission input circuit 28 according to an embodiment of the present invention.
- the transmission output circuit 26 outputs a downstream signal to the transmission lines 12a and 12b in the voltage mode based on a command instruction such as polling from the CPU 22, for example.
- the transmission input circuit 28 outputs a transmission current detection signal indicating this reception to the CPU 22 when receiving an upstream signal in a current mode from the analog type sensor 14 or the repeater 16 as a slave unit, that is, a transmission current, Causes the CPU 22 to perform a fire alarm operation.
- the receiver 10 is provided with a display unit 30, an operation unit 32, a storage unit 34, and a transfer unit 36.
- Various alarm outputs and alarm displays necessary for fire monitoring are provided. , Operation, storage of monitoring information, output of transfer signal, etc.
- the analog sensor 14 is provided with a CPU 38, a sensor unit 40, and a transmission circuit unit 42.
- the sensor unit 40 detects the concentration (smoke concentration) or temperature of smoke generated by the fire and outputs it to the CPU 38.
- the transmission circuit unit 42 receives the downstream signal of the polling command specifying its own address from the receiver 10 and, when the CPU 38 determines that it is normal, transmits the response upstream signal indicating normality to the receiver 10 in the current mode. .
- the CPU 38 detects the occurrence of a fire, it transmits a fire alert signal, which is an upstream signal of a fire interrupt, to the receiver 10 as a response to the polling command specifying its own address.
- the repeater 16 is provided with a CPU 44, a notification receiving unit 46, and a transmission circuit unit 48. Sensor lines 18a and 18b are drawn out from the notification receiving unit 46, and the on / off type sensors 20 are connected to the sensor lines 18a and 18b as loads.
- the on / off type sensor 20 detects the occurrence of a fire, an alarm current is passed between the sensor lines 18a and 18b, and the alarm receiver 46 receives the alarm current and outputs it to the CPU 44. Then, the CPU 44 causes the transmission circuit unit 48 to transmit a fire interrupt upstream signal to the receiver 10 as a response to the polling command specifying the self address.
- the repeater 16 also receives an upstream signal indicating normality in the current mode when there is no abnormality when receiving the downstream signal of the polling command specifying the self-address from the receiver 10. 10 is transmitted.
- the receiver 10 transmits a normal monitoring polling command in which slave unit addresses are sequentially specified.
- a normal monitoring response is made. Therefore, the receiver 10 can detect the presence or absence of a failure in the analog sensor 14 or the repeater 16 based on the presence or absence of a response to the polling command.
- the analog sensor 14 receives a batch AD conversion command that is repeatedly output at every polling command transmission period for all sensor addresses of the receiver 10.
- the analog type sensor 14 samples analog detection data such as smoke density and temperature by the fire detection mechanism (sensor unit 40) incorporated therein, and compares it with a predetermined fire level. When this fire level is exceeded, it is determined that a fire has occurred.
- a fire is made to the receiver 10 at the timing of transmitting a polling command designating its own sensor address thereafter. Send an interrupt signal.
- the fire interrupt signal a signal that is not normally used, such as a response bit of all 1, is used.
- the repeater 16 also samples the reception state by the notification receiving unit 46 based on the batch AD conversion command from the receiver 10. When the relay 16 detects the notification reception, the repeater 16 transmits an interrupt signal to the receiver 10 at the timing of the polling command designating the subsequent sensor address.
- the receiver 10 When the receiver 10 receives a fire interrupt signal from the analog type sensor 14 or the repeater 16, the receiver 10 issues a group search command, and receives from the group including the analog type sensor 14 or the repeater 16 that detects the fire. Receive fire interrupt response to determine group. Subsequently, the receiver 10 performs polling by sequentially specifying addresses for the individual analog sensors 14 and repeaters 16 included in the determined group, and sends a fire response (analog data or fire alarm data). By receiving it, the sensor address of the analog sensor 14 or the repeater 16 that detects the fire is recognized, and a fire alarm operation is performed.
- group addresses are set for every 8 units.
- a fire interrupt response is made from the group including the analog type sensor 14 that detects the occurrence of a fire.
- the group including the analog type sensor 14 or the repeater 16 that detects the occurrence of fire can be specified.
- FIG. 2 is a circuit diagram showing a configuration of the transmission input circuit 28 according to the present embodiment.
- the transmission input circuit 28 provided in the receiver 10 includes a current detection resistor R0, a comparator 48, a constant current circuit 50, a switch 52 using a transistor, a MOS-FET, or the like, and a digital A variable resistor 54 and a pull-up resistor R5 are provided.
- a current detection resistor R0 is provided on the transmission line 12b side into which the load current Iz flowing according to the load and the transmission current Ia sent as an upstream signal from the slave unit flow. Is connected. As a result, the current detection resistor R0 generates a current detection voltage Vi proportional to the line current flowing from the transmission line 12b.
- the current detection voltage Vi generated by the current detection resistor R0 is input to the negative input terminal of the comparator 48.
- the reference voltage Vr set by the digital variable resistor 54 is input to the positive input terminal of the comparator 48.
- the comparator 48 is at the H (High) level when the current detection voltage Vi is less than the reference voltage Vr, and is inverted to the L (Low) level when the current detection voltage Vi exceeds the reference voltage Vr. Is output. The output from the comparator 48 is pulled up to the internal power supply voltage Vd via the resistor R5.
- the constant current circuit 50 has one end connected to the transmission line 12a through which the power supply voltage Vc flows, and the other end connected to the current detection resistor R0 via the switch 52.
- a predetermined reference current Ie flows to the current detection resistor R0 via the switch 52.
- a threshold voltage Ve for detecting the transmission current detection voltage is generated in the current detection resistor R0.
- the CPU 22 is provided with an adjustment processing unit 55 as a function realized by executing the program.
- the adjustment processing unit 55 turns on the switch 52 at a vacant timing when the transmission current Ia does not flow through the transmission lines 12a and 12b, that is, at a predetermined adjustment timing when only the load current Iz due to the load flows.
- the reference current Ie flows from 50 toward the current detection resistor R0.
- the adjustment processing unit 55 controls the control value C in the digital variable resistor 54 so that the reference voltage Vr matches the adjustment target voltage Vt input from the current detection resistor R0 to the negative input terminal of the comparator 48. Adjust (digital value).
- FIG. 3 is a block diagram showing a circuit configuration of the digital variable resistor 54 of the present embodiment.
- the digital variable resistor 54 includes a series resistor array 56, an up / down counter 60, a nonvolatile memory 62, a control circuit 64, and a decoder 66.
- the series resistor array 56 is a switch in which a predetermined number of fixed resistors r having a predetermined resistance value are connected in series, and switches using MOS-FETs or the like at both ends thereof and connection portions between the resistors r. One end of 58 is connected. The other end of each switch 58 is connected to a common wiring 56a.
- a power supply terminal 68 is taken out from one end of the series resistance circuit of the series resistance array 56, and a ground terminal 70 is taken out from the other end. Further, the common wiring 56 a side connected via the switch 58 is connected to the wiper terminal 72.
- the series resistor array 56 can switch its resistance value over, for example, 256 stages by turning on and off the switch 58 by the output of the decoder 66, and thus, the series resistor array 56 is applied between the power supply terminal 68 and the ground terminal 70.
- the direct current voltage can be adjusted to a voltage of any of 256 stages and output.
- An up / down counter 60 is connected to the decoder 66.
- the up / down counter 60 receives a count signal, which is a control signal input to the control terminal 73, and thereby performs an up count or a down count between a minimum value and a maximum value.
- the binary data counted by the up / down counter 60 is converted by the decoder 66 into, for example, decimal data of 1 to 256 stages. Then, by turning on the switch 58 at the position corresponding to the decimal data sent out from the decoder 66, the voltage corresponding to the value (number of stages) set by the decoder 66 can be taken out from the wiper terminal 72.
- the control circuit 64 performs timing control for the up / down counter 60 and the decoder 66.
- the digital variable resistor 54 is provided with a nonvolatile memory 62 for storing the value of the up / down counter 60.
- the nonvolatile memory 62 is set in the up / down counter 60. Thereby, even if the power is turned off, the adjustment value at that time can be held. If the adjustment value does not need to be retained even when the power is turned off, the nonvolatile memory 62 need not be provided.
- FIG. 4 is a time chart showing the relationship between the comparator input voltage and the reference voltage adjustment timing in this embodiment.
- FIG. 4A shows the input voltage of the comparator 48. Normally, only the load current Iz flowing from the transmission line 12b to the load is input to the comparator 48. For this reason, the load voltage Vz corresponding to the load current Iz is generated in the current detection resistor R0 and is input to the input terminal of the comparator 48 as the line current detection voltage Vi.
- the adjustment processing unit 55 provided in the CPU 22 in FIG. 2 performs the timing t1 to the timing when only the load current Iz flows from the transmission line 12b, that is, the idle timing when the transmission current Ia is not sent from the slave unit. During t2, adjustment processing of the reference voltage Vr generated from the digital variable resistor 54 is executed.
- the switch 52 is turned on, the reference current Ie from the constant current circuit 50 is supplied to the current detection resistor R0, and added to the load current detection voltage Vz based on the load current Iz that is basically flowing.
- a threshold voltage Ve corresponding to the current Ie is generated.
- the adjustment processing unit 55 adjusts the digital value serving as the control value C for the digital variable resistor 54, and the reference voltage Vr output from the digital variable resistor 54 is applied to the negative input terminal.
- the adjustment process ends when the adjustment target voltage Vt is reached.
- the threshold voltage Ve generated in the current detection resistor R0 by the reference current Ie from the constant current circuit 50 is one half of the transmission current detection voltage Va generated in the current detection resistor R0 by the reporting current Ia from the slave unit. It is determined based on the value of the reference current Ie that generates the voltage.
- the increment with respect to the current detection voltage Vz exceeds the reference voltage Vr that is, when the increase exceeds the threshold voltage Ve
- the comparator 48 reverses the transmission current detection signal inverted to the L level for a voltage portion exceeding the reference voltage Vr. Is output to the CPU 22.
- FIG. 5 is a flowchart showing the reference voltage adjustment process in the present embodiment.
- step S3 the process proceeds to step S3 to check whether or not the output of the comparator 48 is at the H level. As a result, if the output of the comparator 48 is at the H level, the output voltage from the digital variable resistor 54 is higher than the target adjustment voltage Vt. In this case, the process proceeds to step S4 and the digital variable resistor 54 The control value C for 1 is counted down by 1 bit. Then, the value of the up / down counter 60 shown in FIG. As a result, the output voltage of the digital variable resistor 54 having a high value approaches the adjustment target voltage V1.
- step S6 it is determined whether or not the output of the comparator 48 is inverted from the H level to the L level, and the countdown in steps S3 and S4 is repeated until the output is inverted to the L level.
- the output voltage of the digital variable resistor 54 passes the adjustment target voltage Vi with a 1-bit change, the H level output before the 1-bit change is inverted to the L-level output after the 1-bit change. Accordingly, it is determined that the adjustment is finished at this point, and the process proceeds to step S7, where the switch 52 is turned off and the adjustment process is finished.
- step S3 if the result of the first check of the output of the comparator 48 in step S3 is an L level output, the output voltage of the digital variable resistor 54 is smaller than the adjustment target voltage Vt. If so, the process proceeds to step S5. Then, an up / down counter provided in the digital variable resistor 54 is counted up by the control value C in units of 1 bit. Then, when the output of the comparator 48 is inverted from the L level to the H level during counting up in step S6, it is determined that the output voltage of the digital variable resistor 54 matches the adjustment target voltage Vt, and the switch is switched in step S7. 52 is turned off and the adjustment process is terminated.
- the digital variable resistor 54 according to the inverted control value is used. Is the reference voltage Vr.
- the output voltage of the digital variable resistor 54 with the control value one bit before the inversion may be used as the reference voltage Vr.
- FIG. 6 is a time chart showing the relationship between the line current detection voltage and the reference voltage adjustment timing when the load current is stable.
- 6A shows a line current detection voltage input to the comparator 48. Since the load current Iz is constant, a constant load current detection voltage Vz is generated accordingly.
- a pulsed transmission current detection voltage Va is generated by the transmission current Ia from the slave unit in a form that is added to the constant load current detection voltage Vz.
- the reference voltage Vr is set to a voltage obtained by adding a threshold voltage Ve, which is a half of the transmission current detection voltage Va, to the basic load current detection voltage Vz by the adjustment process of the digital variable resistor 54. .
- the comparator 48 detects and outputs a transmission current detection signal for a portion of the transmission current detection voltage Va that exceeds the reference voltage Vr.
- the transmission current sent from the slave unit is output at a constant cycle, for example, as a normal response to polling in which the slave unit addresses are sequentially specified from the receiver 10 shown in FIG.
- the digital variable resistor 54 is used so that the reference voltage Vr with time elapses as in the case of sample-holding with a conventional capacitor. There is no decline. Therefore, for example, the reference voltage adjustment timing can be set for every other empty timing as shown in FIG. 6B, for example, instead of all the empty timings of the transmission current periodically output.
- FIG. 7 is a time chart showing the relationship between the line current detection voltage and the reference voltage adjustment timing when the load current fluctuates.
- a constant consumption current flows, and the total flows as a load current.
- this load current is not necessarily constant, and changes gradually according to temperature and aging.
- FIG. 7A shows the fluctuation of the load current detection voltage Vz according to such a gentle fluctuation of the load current Iz.
- the reference voltage Vr can be set while following the variation of the load current Iz.
- a time reference such as a configuration in which a sample capacitor and sample is held between the adjustment of the reference voltage and the adjustment of the next reference voltage. No voltage change occurs. Therefore, the transmission current can be detected more accurately.
- FIG. 8 is a circuit diagram showing a second embodiment of the transmission input circuit of the present invention.
- a digital variable resistor for coarse adjustment and a digital variable resistor for fine adjustment are provided in order to shorten the adjustment time of the reference voltage.
- the transmission input circuit 28 provided in the receiver 10 includes a current detection resistor R0, a comparator 48, a constant current circuit 50, and a switch 52, as in the case of the first embodiment. And a pull-up resistor R5.
- the transmission input circuit 28 of the present embodiment is provided with a first digital variable resistor 54-1 for coarse adjustment and a second digital variable resistor 54-2 for fine adjustment. .
- the first digital variable resistor 54-1 is connected to the positive input terminal of the comparator 48 via the first resistor R1 having a sufficiently large resistance value.
- the second digital variable resistor 54-2 is also connected to the plus input terminal of the comparator 48 through a second resistor R2 having a sufficiently large resistance value.
- the first resistor R1 and the second resistor R2 determine the adjustment ratio of the reference voltage Vr by the two digital variable resistors 54-1 and 54-2, and the resistance of the first resistor R1 on the coarse adjustment side.
- the value is made smaller than the resistance value of the second resistor R2 on the fine adjustment side.
- the adjustment ratio on the coarse adjustment side by the first digital variable resistor 54-1 is 1.
- the adjustment voltage by the second digital variable resistor 54-2 can be set to 1/10 with the same operation amount.
- FIG. 9 shows an equivalent circuit diagram in which the reference voltage for the comparator 48 is changed by coarse adjustment and fine adjustment by the two digital variable resistors 54-1 and 54-2 in the present embodiment.
- the first and second digital variable resistors 54-1 and 54-2 are connected between the same internal power supply voltage Vd and the ground side, and the respective wiper terminals are connected to the first resistor R1 and the first resistor R1. It is connected to a connection point P that reaches the positive input terminal of the comparator 48 via a two-resistance R2.
- the first digital variable resistor 54-1 for coarse adjustment and the second digital variable resistor 54-2 for fine adjustment are provided, so that the reference The resolution of voltage adjustment can be made finer, and at the same time the adjustment time can be shortened.
- first and second digital variable resistors 54-1 and 54-2 have the following performance.
- ⁇ Maximum adjustment voltage 10 volts
- Minimum resolution 1 millivolt at 10 microseconds / time
- the maximum adjustment time is 100 milliseconds.
- the adjustment time is as short as 2 milliseconds, with 1 millisecond being twice.
- FIG. 10 is a flowchart showing a reference voltage adjustment process in the present embodiment.
- step S11 it is determined whether or not it is an adjustment timing without a transmission current from the slave unit.
- step S12 the switch 52 is turned on, and the reference current Ie is caused to flow from the constant current circuit 50 to the current detection resistor R0.
- step S13 the wiper terminal of the second digital variable resistor 54-2 is set to the midpoint position. This is because, if the wiper position of the second digital variable resistor 54-2 is at the position of the minimum voltage 0 volts or the voltage position of the maximum voltage Vd, the first digital variable resistor 54 This is to prevent the adjustment by ⁇ 1 from being impossible.
- step S14 it is determined whether or not the output of the comparator 48 is at the H level. If the result of determination is that it is at the H level, the reference voltage Vr is greater than the adjustment target voltage Vt. Therefore, the countdown of the first control value C1 is performed as -1 in step S15, and the comparator 48 in step S17. Steps S14 and S15 are repeated until the output of is inverted to L level.
- step S14 determines whether the output of the comparator 48 is at the L level, the reference voltage Vr is smaller than the adjustment target voltage Vt, so the process proceeds to step S16 and the first digital variable resistor As the count up of the first control value C1 for the unit 54-1, +1 is performed. Subsequently, the processes in steps S14 and S16 are repeated until the output of the comparator 48 is inverted to the H level in step S17.
- step S17 If it is determined in step S17 that the output of the comparator 48 has been inverted, it is determined that the coarse adjustment of the first digital variable resistor 54-1 has been completed, and the second digital variable resistor 54- in the next steps S18 to S21. Perform 2 fine adjustment.
- step S18 if the output of the comparator 48 is at the H level in step S18, -1 is performed to count down the second control value C2 in step S19. On the other hand, if the output of the comparator 48 is at the L level, a process of +1 for counting up the second control value C2 is performed in step S20.
- step S21 When the inversion of the output of the comparator 48 is determined in step S21 by repeating counting up or counting down of the second control value C2, it is determined that the reference voltage Vr matches the target adjustment voltage Vt, and the switch is switched in step S22. To turn off the fine adjustment.
- FIG. 11 is a circuit diagram showing a third embodiment of the transmission input circuit of the present invention.
- the adjustment process of the CPU 22 that fixes the second digital variable resistor 54-2 for fine adjustment at the midpoint position during the coarse adjustment of the first digital variable resistor 54-1 in the second embodiment. Since the software processing by the unit 55 is complicated, the processing for holding the second digital variable resistor 54-2 at the midpoint position is performed by hardware using a logic circuit and a resistance circuit.
- the transmission input circuit 28 provided in the receiver 10 includes a current detection resistor R0, a comparator 48, a constant current circuit 50, a switch 52, and a pull, as in the second embodiment.
- An up resistor R5, a first digital variable resistor 54-1 for coarse adjustment, and a second digital variable resistor 54-2 for fine adjustment are provided.
- a logic circuit including inverters 74 and 76 and a resistor circuit including a third resistor R3 and a fourth resistor R4 are added to the second digital variable resistor 54-2 side. Then, by outputting a control signal from the adjustment processing unit 55 provided in the CPU 22 to the inverter 74, the output on the second digital variable resistor 54-2 side in terms of hardware and the position of the wiper terminal as the midpoint position The output voltage can be fixed.
- the first inverter 74 inputs a control signal generated from the adjustment processing unit 55 of the CPU 22 and connects its output to the ground terminal of the second digital variable resistor 54-2.
- the second inverter 76 inputs the output of the inverter 74 and connects the output to the plus input terminal of the comparator 48 via the third resistor R3.
- a fourth resistor R4 is connected in parallel with the third resistor R3.
- the internal power supply voltage Vd is output as the H level output voltage of the first inverter 74 and the second inverter 76. Therefore, the resistor network for the positive input terminal of the comparator 48 at this time is as shown in FIG. 12A.
- the wiper terminal is connected to a point P that is a point to be connected to the comparator 48 through the first resistor R1.
- the internal power supply voltage Vd is applied to the ground terminal side at the H level output of the first inverter 74. Therefore, the same internal power supply voltage Vd is applied to the wiper terminal.
- the second resistor R3 is connected to the internal power supply voltage Vd.
- An equivalent circuit is realized in which a parallel circuit including a third resistor R3 and a fourth resistor R4 is connected in series to R2.
- the first digital variable resistor 54-1 does not depend on the position of the wiper terminal of the second digital variable resistor 54-2, and performs rough adjustment to make the reference voltage Vr substantially coincide with the target adjustment voltage Vt. It can be performed.
- the adjustment processing unit 55 inverts the output to the first inverter 74 from the L level output so far to the H level output. For this reason, the output of the first inverter 74 is inverted from the H level to the L level, the ground terminal of the second digital variable resistor 54-2 becomes the L level and is connected to the ground side, and the normal internal power supply voltage is applied. Return to state.
- the L level output of the first inverter 74 is inverted by the second inverter 76 to become the H level output, and the internal power supply voltage Vd is applied to the other end side of the third resistor R3.
- This state is shown by an equivalent circuit shown in FIG. 12B.
- the first digital variable resistor 54-1 has the wiper terminal at the position after the coarse adjustment.
- the second digital variable resistor 54-2 connects the wiper terminal to the connection point P to the comparator 48 via the second resistor R2, and further to the P point that is the connection point to the comparator 48.
- a series connection point R of a series circuit including the three resistors R3 and the fourth resistor R4 is connected.
- FIG. 13 is a flowchart showing a reference voltage adjustment process in the present embodiment.
- the adjustment process shown in FIG. 13 is basically the same as that shown in the flowchart of the second embodiment, but (a) prior to the coarse adjustment by the first digital variable resistor 54-1 in step S31. A low level output is made to the first inverter 74 to create a circuit state equivalent to the case where the wiper position of the second digital variable resistor 54-2 shown in FIG. )
- step S38 the coarse adjustment proceeds and prior to fine adjustment by the second digital variable resistor 54-2, a high level output is performed to the first inverter 74, and the second digital variable resistor 54- shown in FIG. And a process of creating an equivalent circuit state capable of coarse adjustment by 2 is newly provided.
- steps S31 and S32 in FIG. 13 correspond to steps S11 and S12 in FIG. 10
- steps S34 to S37 correspond to steps S14 to S17 in FIG. 10
- steps S40 to S44 further correspond to steps in FIG. This corresponds to S18 to S22.
- FIG. 14 is a circuit diagram showing a fourth embodiment of the transmission input circuit of the present invention.
- a DA converter is used as means for setting a reference voltage for the comparator 48.
- the transmission input circuit 28 provided in the receiver 10 is basically the same as that of the first embodiment, and includes a current detection resistor R0, a comparator 48, a constant current circuit 50, and a switch 52. And a pull-up resistor R5.
- a DA converter 78 is provided instead of the digital variable resistor 54 shown in FIG.
- the adjustment processing unit 55 provided in the CPU 22 causes the reference current Ie to flow from the constant current circuit 50 by turning on the switch 52 at the adjustment timing, thereby generating the current in the current detection resistor R0.
- the reference voltage adjustment processing in this embodiment is basically the same as that described in the flowchart of FIG. 5 in the first embodiment, and the digital value for the DA converter 78 is used as the control value in steps S4 and S5 in FIG. The only difference is that it is +1 or -1 in 1-bit units.
- the digital variable resistor used in the first embodiment can be regarded as a kind of DA converter because the digital value is converted into an analog voltage and output.
- the point that the output voltage is adjusted by switching the series resistor array 56 is a unique configuration, and a circuit for converting a digital signal into an analog voltage that takes other configurations is shown in FIG.
- each of the above embodiments has taken as an example a repeater in which an on-off type fire detector is connected as a device that mainly sends a load current to the transmission line drawn from the receiver, but is not limited thereto, The same applies when a gas leak detector, a burglar alarm, or the like other than the on / off type sensor is connected.
- the present invention includes appropriate modifications that do not impair the object and advantages thereof, and is not limited only by the numerical values shown in the above embodiments.
- a transmission input circuit that can arbitrarily set a threshold voltage for detecting a transmission current and can accurately detect the presence or absence of the transmission current from a slave unit without fluctuation due to temperature or time passage. can do.
Abstract
Description
本願は、2008年10月02日に、日本に出願された特願2008-257173号に基づき優先権を主張し、その内容をここに援用する。
なお、負荷電流Izに対応した負荷電圧Vzを一定電圧として示しているが、実際には、環境温度などに応じて負荷電流Izが緩やかに変化する。
(1)本発明の伝送入力回路は、電源供給線を兼ねた伝送線に負荷からの負荷電流が流れている状態で、子機からの伝送電流の有無を検出する親機の伝送入力回路であって、前記伝送線を流れる線路電流を自らに入力して線路電流検出電圧を生成する電流検出抵抗と;スイッチングにより、定電流回路からの所定の基準電流を前記電流検出抵抗に流して閾値電圧を生成させるスイッチと;デジタル値に応じて抵抗値を設定することにより任意の基準電圧を生成するデジタル可変抵抗回路と;入力端子の一方に前記電流検出抵抗で生成した前記線路電流検出電圧が入力されると共に、入力端子の他方に前記デジタル可変抵抗回路で生成した前記基準電圧が入力され、さらに、前記線路電流検出電圧のうちの、前記基準電圧を越える成分を伝送電流検出信号として出力するコンパレータと;前記子機からの前記伝送電流が流れていない空きタイミングで前記スイッチをオンにして前記定電流回路から前記電流検出抵抗に前記基準電流を流し、前記負荷電流に対応した負荷電流検出電圧に対して前記基準電流に対応した閾値電圧を加算した目標調整電圧を前記電流検出抵抗に生成させ、さらには、前記デジタル可変抵抗器から出力される前記基準電圧が前記目標調整電圧と一致するように前記デジタル値を調整する調整処理部と;を備える。
[第1実施形態]
図1は、本発明が適用された監視システムにおける受信機の構成を、アナログ型感知器及び中継器と共に示したブロック図である。図1において、本発明が適用される監視システムでは、親機である受信機10から警戒区域に向けて引き出された伝送線12a,12bに、子機であるアナログ型感知器14及び中継器16を複数接続している。
アナログ型感知器14は、火災により発生した煙の濃度(煙濃度)または温度(例えば室温)を検出し、検出した値をアナログデータとして受信機10に伝送する。一方、受信機10側では、受信した煙濃度または温度のアナログデータから火災発生の有無を判断し、火災発生と判断された場合には警報を発する。
受信機10は、通常の監視時では、子機アドレスを順次指定した正常監視用のポーリングコマンドを送信している。アナログ型感知器14及び中継器16は、自己の設定アドレスに一致するポーリングコマンドを受信すると、正常監視応答を行う。このため、受信機10は、ポーリングコマンドに対する応答の有無により、アナログ型感知器14又は中継器16の障害の有無を検出することができる。
この図5に示すように、基準電圧調整処理は、まずステップS1で、子機からの伝送電流Iaの送出がない空きタイミングとなる調整タイミングか否かを判別する。そして、調整タイミングであると判別すると、ステップS2に進み、スイッチ52をオンにする。そして、定電流回路50から電流検出抵抗R0に基準電流Ieを流し、コンパレータ48のマイナス入力端子に対してVt=Vz+Veとなる目標調整電圧Vtを入力させる。
図8は、本発明の伝送入力回路の第2実施形態を示す回路図である。本実施形態では、基準電圧の調整時間を短縮するために、粗調整用のデジタル可変抵抗器と微調整用のデジタル可変抵抗器とを設けている。
Vr=V1-(V1-V2)R1/(R1+R2) (1)
即ち、基準電圧Vrは、第1及び第2のデジタル可変抵抗器54-1,54-2におけるワイパー端子電圧V1,V2の差電圧(V1-V2)を第1抵抗R1と第2抵抗R2で分圧して、例えばワイパー端子電圧V1から減算した値となる。
・最大調整電圧:10ボルト
・最小分解能 :1ミリボルトを10マイクロ秒/回
このような調整性能を持っていた場合、例えば第1デジタル可変抵抗器54-1の1台のみで調整する場合には、10000段の調整ステップを持つデジタル可変抵抗器が必要となり、最大調整時間は100ミリ秒かかることになる。
図11は、本発明の伝送入力回路の第3実施形態を示す回路図である。本実施形態では、上記第2実施形態における第1デジタル可変抵抗器54-1の粗調整の際に微調整用の第2デジタル可変抵抗器54-2を中点位置に固定するCPU22の調整処理部55によるソフトウェア処理が煩雑であることから、第2デジタル可変抵抗器54-2を中点位置に保持する処理を論理回路及び抵抗回路によりハードウェア的に行うようにしている。
R3=2×R2R4=2×R2 (2)
コンパレータ48に対する基準電圧Vrの調整時には、まず第1デジタル可変抵抗器54-1による粗調整を行うが、この時の調整処理部55は、第1インバータ74にLレベル信号を出力する。第1インバータ74は、Lレベル信号の入力を受けてHレベル信号を反転出力する。これを受けて、第2インバータ76は、Hレベル入力を反転させてLレベル出力を生ずる。
図14は、本発明の伝送入力回路の第4実施形態を示す回路図であり、本実施形態では、コンパレータ48に対して基準電圧を設定する手段として、DAコンバータを用いている。
12a,12b 伝送線
14 アナログ型感知器
16 中継器
18a,18b 感知器回線
20 オンオフ型感知器
22,38,44 CPU
24 伝送回路部
26 伝送出力回路
28 伝送入力回路
30 表示部
32 操作部
34 記憶部
36 移報部
40 センサ部
42,48 伝送回路部
46 発報受信部
48 コンパレータ
50 定電流回路
52,58 スイッチ素子
54 デジタル可変抵抗器
54-1 第1デジタル可変抵抗器
54-2 第2デジタル可変抵抗器
55 調整処理部
56 直列抵抗アレイ
60 アップダウンカウンタ
62 不揮発メモリ
64 制御回路
68 電源端子
70 グランド端子
72 ワイパー端子
74 第1インバータ
76 第2インバータ
78 ADコンバータ
Claims (8)
- 電源供給線を兼ねた伝送線に負荷からの負荷電流が流れている状態で、子機からの伝送電流の有無を検出する親機の伝送入力回路であって、
前記伝送線を流れる線路電流を自らに入力して線路電流検出電圧を生成する電流検出抵抗と;
スイッチングにより、定電流回路からの所定の基準電流を前記電流検出抵抗に流して閾値電圧を生成させるスイッチと;
デジタル値に応じて抵抗値を設定することにより任意の基準電圧を生成するデジタル可変抵抗回路と;
入力端子の一方に前記電流検出抵抗で生成した前記線路電流検出電圧が入力されると共に、入力端子の他方に前記デジタル可変抵抗回路で生成した前記基準電圧が入力され、さらに、前記線路電流検出電圧のうちの、前記基準電圧を越える成分を伝送電流検出信号として出力するコンパレータと;
前記子機からの前記伝送電流が流れていない空きタイミングで前記スイッチをオンにして前記定電流回路から前記電流検出抵抗に前記基準電流を流し、前記負荷電流に対応した負荷電流検出電圧に対して前記基準電流に対応した閾値電圧を加算した目標調整電圧を前記電流検出抵抗に生成させ、さらには、前記デジタル可変抵抗器から出力される前記基準電圧が前記目標調整電圧と一致するように前記デジタル値を調整する調整処理部と;
を備えたことを特徴とする伝送入力回路。 - 前記デジタル可変抵抗回路が、両端に所定の内部電源電圧が印加される直列抵抗アレイと、前記調整処理部から入力されてかつ前記デジタル値に応じて可変された電圧を出力するワイパー端子とを有する単一のデジタル可変抵抗器を備え;
前記調整処理部が、前記デジタル可変抵抗器に対して付与する前記デジタル値を、1ビット変化で前記コンパレータの出力が反転するデジタル値又は反転直前のデジタル値に調整する;
ことを特徴とする請求項1に記載の伝送入力回路。 - 前記調整処理部が、
調整開始時の前記コンパレータの出力がハイレベルの場合は、このハイレベルをローレベルに反転させる方向に前記デジタル値を1ビット単位で変化させてかつ、前記デジタル可変抵抗器に対して付与する前記デジタル値を、前記ハイレベルから前記ローレベルに反転した時のデジタル値または反転直前のデジタル値に調整する一方、
調整開始時の前記コンパレータの出力がローレベルの場合は、このローレベルをハイレベルに反転させる方向に前記デジタル値を1ビット単位で変化させてかつ、前記デジタル可変抵抗器に対して付与する前記デジタル値を、前記ローレベルから前記ハイレベルに反転した時のデジタル値または反転直前のデジタル値に調整する、
ことを特徴とする請求項2に記載の伝送入力回路。 - 前記デジタル可変抵抗回路が、
両端に所定の内部電源電圧が印加される第1直列抵抗アレイと、前記調整処理部から入力されてかつ前記デジタル値に応じて可変された電圧を出力する第1ワイパー端子とを有する粗調整用の第1デジタル可変抵抗器と;
両端に前記所定の内部電源電圧が印加される第2直列抵抗アレイと、前記調整処理部から入力されてかつ前記デジタル値に応じて可変された電圧を出力する第2ワイパー端子とを有する微調整用の第2デジタル可変抵抗器と;
前記第1ワイパー端子を前記コンパレータの前記他方の入力端子に接続するラインに設けられた第1抵抗と;
前記第2ワイパー端子を前記コンパレータの前記他方の入力端子に接続する前記ラインに設けられてかつ、前記第1抵抗よりも大きい抵抗値を有する第2抵抗と;
を備え、
前記調整処理部が、
前記基準電圧と前記目標調整電圧とが略一致するように、前記第1デジタル可変抵抗器に対して付与する前記デジタル値を調整した後に、
前記基準電圧と前記目標調整電圧とが一致するように、前記第2デジタル可変抵抗器に対する前記デジタル値を調整する、
ことを特徴とする請求項1に記載の伝送入力回路。 - 前記調整処理部が、前記第1デジタル可変抵抗器を調整する際に、前記第2デジタル可変抵抗器の前記第2ワイパー端子の位置を中点位置に固定する
ことを特徴とする請求項4に記載の伝送入力回路。 - 前記デジタル可変抵抗回路が、
両端に所定の内部電源電圧が印加される第1直列抵抗アレイと、前記調整処理部から入力されてかつ前記デジタル値に応じて可変された電圧を出力する第1ワイパー端子とを有する粗調整用の第1デジタル可変抵抗器と;
両端に前記所定の内部電源電圧が印加される第2直列抵抗アレイと、前記調整処理部から入力されてかつ前記デジタル値に応じて可変された電圧を出力する第2ワイパー端子とを有する微調整用の第2デジタル可変抵抗器と;
前記第1ワイパー端子を前記コンパレータの前記他方の入力端子に接続するラインに設けられた第1抵抗と;
前記第2ワイパー端子を前記コンパレータの前記他方の入力端子に接続する前記ラインに設けられてかつ、前記第1抵抗よりも大きい抵抗値を有する第2抵抗と;
前記調整処理部に入力が接続される一方、前記第2直列抵抗アレイのグランド側端子に出力が接続された第1インバータと;
この第1インバータからの前記出力が入力接続されてかつ、前記第2抵抗の2倍の抵抗値を有する第3抵抗を介して前記コンパレータの前記他方の入力端子に出力接続された第2インバータと;
前記コンパレータの前記他方の入力端子とグランドとの間に接続された前記第2抵抗の2倍の抵抗値を有する第4抵抗と;
を備え、
前記調整処理部が、
前記基準電圧と前記目標調整電圧とが略一致するように、前記第1デジタル可変抵抗器に対して付与する前記デジタル値を調整した後に、前記基準電圧と前記目標調整電圧とが一致するように、前記第2デジタル可変抵抗器に対して付与する前記デジタル値を調整し、
また、前記第1デジタル可変抵抗器の抵抗値を調整する際に、ローレベル信号を前記第1インバータに入力して前記内部電源電圧となるハイレベル信号の出力を得ることにより前記第1デジタル可変抵抗器を介して前記第2抵抗に前記内部電源電圧を印加すると共に、前記第2インバータからのローレベル信号の出力により、前記第3抵抗をグランド側に接続して前記第2抵抗に前記第3抵抗及び第4抵抗からなる並列回路を直列接続する回路を形成し、これにより、直列接続点の電圧を、前記第2ワイパー端子の位置が中点位置にあるときの出力電圧と同じ値に設定し、
さらには、前記第2デジタル可変抵抗器の抵抗値を調整する際に、ハイレベル信号を前記第1インバータに入力してローレベル信号の出力を得ることにより前記第2デジタル可変抵抗器の一端をグランド側に接続して調整可能にすると共に、前記第2インバータからのハイレベル信号の出力を得ることにより前記内部電源電圧及び前記グランド間に前記第3抵抗及び前記第4抵抗を直列接続する回路を形成し、これにより、前記第3抵抗及び前記第4抵抗の直列接続点の電圧を前記内部電源電圧の1/2に設定する、
ことを特徴とする請求項1に記載の伝送入力回路。 - 電源供給線を兼ねた伝送線に負荷からの負荷電流が流れている状態で、子機からの伝送電流の有無を検出する親機の伝送入力回路であって、
前記伝送線を流れる線路電流を自らに入力して線路電流検出電圧を生成する電流検出抵抗と;
スイッチングにより、定電流回路から所定の基準電流を前記電流検出抵抗に流して閾値電圧を生成させるスイッチと;
デジタル値に応じた任意の基準電圧を発生するDAコンバータと;
入力端子の一方に前記電流検出抵抗で生成した前記線路電流検出電圧が入力されると共に、入力端子の他方に前記DAコンバータが生成した前記基準電圧が入力され、前記線路電流検出電圧のうちの、前記基準電圧を越える成分を伝送電流検出信号として出力するコンパレータと;
前記子機からの前記伝送電流が流れていない空きタイミングで前記スイッチをオンにして前記定電流回路から前記電流検出抵抗に前記基準電流を流し、前記負荷電流に対応した負荷電流検出電圧に対して前記基準電流に対応した閾値電圧を加算した目標調整電圧を前記電流検出抵抗に生成させ、さらには、前記DAコンバータから出力される前記基準電圧が前記目標調整電圧と一致するように前記デジタル値を調整する調整処理部と;
を備えたことを特徴とする伝送入力回路。 - 前記定電流回路が、前記伝送電流に対応した伝送電流検出電圧の1/2となる閾値電圧を生成する前記基準電流を供給する
ことを特徴とする請求項1又は7に記載の伝送入力回路。
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JP2010531760A JP5275359B2 (ja) | 2008-10-02 | 2009-10-02 | 伝送入力回路 |
US13/122,184 US8373445B2 (en) | 2008-10-02 | 2009-10-02 | Transmission input circuit |
AU2009298992A AU2009298992B2 (en) | 2008-10-02 | 2009-10-02 | Transmission input circuit |
CN2009801387790A CN102171732B (zh) | 2008-10-02 | 2009-10-02 | 传输输入电路 |
EP09817515.1A EP2352133B1 (en) | 2008-10-02 | 2009-10-02 | Transmission input circuit |
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CN102593789A (zh) * | 2011-01-14 | 2012-07-18 | 鸿富锦精密工业(深圳)有限公司 | 电阻设置系统及电阻设置方法 |
TWI492527B (zh) * | 2011-01-20 | 2015-07-11 | Hon Hai Prec Ind Co Ltd | 電阻設置系統及電阻設置方法 |
US9840744B2 (en) | 2013-03-15 | 2017-12-12 | Dow Agrosciences Llc | Markers linked to reniform nematode resistance |
CN114720851A (zh) * | 2022-04-01 | 2022-07-08 | 珠海妙存科技有限公司 | 一种芯片电源兼容性验证系统及方法 |
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US20130127430A1 (en) * | 2011-11-18 | 2013-05-23 | Diodes Incorporated | Power Regulator for Driving Pulse Width Modulator |
DE102013225101A1 (de) * | 2013-12-06 | 2015-07-02 | Siemens Aktiengesellschaft | System und Verfahren zur rückwirkungsfreien Kommunikation |
FR3047380B1 (fr) * | 2016-01-29 | 2018-05-18 | STMicroelectronics (Alps) SAS | Detection d'un branchement analogique dans un decodeur video |
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EP2352133A1 (en) | 2011-08-03 |
US8373445B2 (en) | 2013-02-12 |
JPWO2010038476A1 (ja) | 2012-03-01 |
CN102171732B (zh) | 2013-08-14 |
CN102171732A (zh) | 2011-08-31 |
JP5275359B2 (ja) | 2013-08-28 |
AU2009298992B2 (en) | 2014-11-20 |
EP2352133A4 (en) | 2014-07-30 |
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US20110175589A1 (en) | 2011-07-21 |
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