WO2010038278A1 - Circuit de traitement de signaux numériques et circuit de commande numérique - Google Patents

Circuit de traitement de signaux numériques et circuit de commande numérique Download PDF

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Publication number
WO2010038278A1
WO2010038278A1 PCT/JP2008/067765 JP2008067765W WO2010038278A1 WO 2010038278 A1 WO2010038278 A1 WO 2010038278A1 JP 2008067765 W JP2008067765 W JP 2008067765W WO 2010038278 A1 WO2010038278 A1 WO 2010038278A1
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WO
WIPO (PCT)
Prior art keywords
circuit
digital
output
value
moving average
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PCT/JP2008/067765
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English (en)
Japanese (ja)
Inventor
不二雄 黒川
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国立大学法人長崎大学
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Priority to PCT/JP2008/067765 priority Critical patent/WO2010038278A1/fr
Publication of WO2010038278A1 publication Critical patent/WO2010038278A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0248—Filters characterised by a particular frequency response or filtering method
    • H03H17/026—Averaging filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
    • H03H2017/0222—Phase error

Definitions

  • the present invention provides a digital signal processing circuit having a simple configuration in which digital control corresponding to analog PID control is realized by combining a first filter circuit that performs processing such as moving average and a second filter circuit having high-pass characteristics.
  • the present invention also relates to a digital control circuit having excellent dynamic characteristics and equipped with this processing circuit.
  • a typical power conversion circuit (indicated by reference numeral 9) as shown in FIG. 11 includes a switch circuit 91 that receives the voltage Ei of the power supply 4 and an inductor that is connected to the switch circuit 91 and stores and discharges energy. 92 and a load 3 is connected to the output terminal of the power conversion circuit 9.
  • the control device 90 When the power converter 9 is driven, the control device 90 performs constant voltage control, constant current control, and constant power control.
  • the constant voltage control the average value or effective value (Eo) of the output voltage eo is normally detected, and feedback control is performed so that, for example, the deviation between the detected value Eo and the target value Eo * becomes zero.
  • the average value or effective value (Io) of the output current io is detected, and feedback control is performed so that the deviation between the detected value Io and the target value Io * becomes zero. Further, for example, the peak value, average value or effective value (I L ) of the current i L flowing through the inductor 92 is detected, and constant current control is performed so that the deviation between the detected value I L and the target value I L * becomes zero. May be performed.
  • constant power control normally, the product of output voltage eo and output current io (or the product of Eo and Io) is detected, and feedback control is performed so that the deviation between detected value P and target value P * becomes zero. is doing.
  • the deviation (X * ⁇ X) between the detected value of voltage, current, and power (here, X) and the target value (X * ) is obtained by a comparator.
  • the deviation (X * ⁇ X) is subjected to analog processing such as proportional compensation (P compensation), proportional / integral compensation (PI compensation), or proportional / integral / derivative compensation (PID compensation).
  • the conventional control method described above cannot perform high-speed processing because a delay in an analog element such as a comparator is inevitable.
  • the switching frequency is limited to about 2 MHz.
  • the analog control circuit is naturally unprogrammable, so it is not suitable for characteristic adjustment or design change.
  • the FIR filter is formed by connecting a plurality of sets of a delay block that returns one sample before and a block that multiplies the output value of this delay block by a weight parameter. You can make properties. However, it is not easy to obtain the values of these weight parameters, and it is necessary to perform a complicated analysis. Even if such an analysis can be performed, the FIR filter has an integral characteristic, so that a phase delay is likely to occur. Therefore, it cannot normally be applied to control.
  • the IIR filter does not simply multiply the output of the delay block by the weight parameter like the FIR filter, but incorporates feedback processing. Thereby, since integral characteristics and differential identification can be held together, phase lag can be suppressed.
  • the IIR filter it is not easier to obtain parameter values for stable operation (for example, no oscillation) than FIR, and the algorithm becomes more complicated, so that it is practically impossible to apply to control. is there.
  • An object of the present invention is to realize digital control corresponding to analog PID control by combining a first filter that performs moving average processing or FIR processing and a second filter circuit having a high-pass characteristic, with a simple configuration. It is an object of the present invention to provide a signal processing circuit and a digital control circuit having an excellent dynamic characteristic equipped with this processing circuit.
  • the gist of the digital signal processing circuit of the present invention is (1) to (4).
  • a first filter circuit that inputs a digital value and performs a moving average process or a finite impulse response (FIR) process
  • a second filter circuit that inputs the digital value and has a high-pass characteristic and a leading phase
  • An adder circuit for generating a signal for adding the output of the first filter circuit and the output of the second filter circuit
  • a digital signal processing circuit wherein a phase delay occurring in the first filter circuit is compensated by an output of the second filter circuit.
  • a digital signal having a phase lag output from the first filter circuit and a second filter circuit typically a digital differentiation circuit, having a high-pass characteristic and a leading phase characteristic).
  • the signal output by the digital adder is added by a digital adder.
  • a digital signal with compensated phase delay can be obtained.
  • the moving average calculates a circuit, 2 r pieces of the FIFO capable of storing sampled values, type 2 r pieces of sampling values stored in the FIFO adder for sequentially output by adding these And a shift register that shifts and outputs the addition result data from the adder to the lower order of r bits and outputs the digital control circuit according to (1).
  • the differentiation circuit includes a FIFO that can store two sampling values, a subtracter that inputs the two sampling values stored in the FIFO, subtracts them, and outputs them sequentially, and the subtractor
  • a first coefficient multiplier circuit that multiplies the output of the first filter circuit by a predetermined coefficient and outputs the multiplied value
  • a second coefficient multiplying circuit for multiplying the output of the second filter circuit by a predetermined coefficient and outputting the multiplied value
  • the gist of the digital control circuit of the present invention is (5) or (6).
  • a digital control circuit equipped with the digital signal processing circuit according to (1) A digital control circuit, wherein the digital value is a deviation (X * -X) between a detected value X of a predetermined electric quantity of a device to be controlled and a target value X * of the electric quantity. Since the first filter circuit does not have differential characteristics, the output phase of the first filter circuit is originally delayed, but a digital control signal in which the phase delay is compensated by the second filter circuit can be obtained.
  • the predetermined amount of electricity of the device to be controlled is Output voltage, output current or output power of the device to be controlled, Current flowing through the switch element of the device to be controlled, A current flowing through a reactor for energy storage included in the control target device; (4) The digital control circuit according to (5).
  • the first filter circuit for performing the moving average process and the finite impulse response process, the second filter circuit having a high-pass characteristic, and the digital addition circuit can be configured by a relatively simple circuit. Therefore, the configuration is simple, and it is suitable for making a high-speed control-dedicated IC or FPGA.
  • the present invention can be applied to various digital signal processing circuits, for example, a control circuit for a power conversion device and a sound processing circuit.
  • control equivalent to or higher than PID control in analog control can be performed.
  • control at a switching frequency on the order of 2 MHz is the limit, but control at a switching frequency much higher than this frequency can be realized by a digital circuit.
  • (A) is explanatory drawing which shows one Embodiment of the digital signal processing circuit of this invention
  • (B) is a figure which shows a digital signal by a discrete value.
  • (A) is a block diagram of a moving average circuit used in the present invention
  • (B) is an example of frequency characteristics of the moving average circuit
  • (C) is an example of phase characteristics of the moving average circuit.
  • (A) is an example of frequency characteristics of a differentiation circuit
  • (B) is an example of phase characteristics of a differentiation circuit.
  • FIG. It is explanatory drawing which shows the example which deform
  • (A) is a circuit which calculates a moving average
  • (B) is a graph which shows four sampling points. It is a figure which shows the differentiation circuit used by this invention.
  • (A) shows the transient characteristics of the reactor current when the power conversion circuit is simulated by the PID controller
  • (B) shows the transient characteristics of the reactor current when the power conversion circuit is simulated by the digital control circuit of the present invention.
  • FIG. It is explanatory drawing which shows the conventional power converter circuit.
  • FIG. 1A is an explanatory diagram showing an embodiment of a digital signal processing circuit of the present invention.
  • the digital signal processing circuit 11A includes a moving average circuit 111A, a differentiating circuit 112, and an adding circuit 113.
  • the moving average circuit 111A is the first filter circuit of the present invention
  • the differentiating circuit 112 is the second filter circuit of the present invention.
  • FIG. 1B a digital signal (discrete value), ..., X (1), X (2), ..., X (M), ... Indicates.
  • the time axis is ..., 1, 2, ..., M-1, M, ... It is shown by.
  • the digital value X is, for example, a deviation of electricity such as voltage, current, and power.
  • the moving average circuit 111A receives the digital value X and calculates a moving average MQ (n).
  • the differentiating circuit 112 receives the digital value X, and calculates the time-sequential n-time phase-lag differential value (compensation amount) CQ (n) generated in the moving average circuit 111A.
  • the adding circuit 113 adds the moving average MQ (n) and the compensation amount CQ (n) to generate a digital signal Dc (n) that compensates for the phase delay. Note that FIG. 1A shows the flow of processing, and does not show the signal value of each part at a certain moment.
  • Equation 1 The difference equation of the moving average MQ at time n in time series is expressed by Equation 1.
  • MQ (n) (1 / M) ⁇ X (k) (Equation 1)
  • M is the number of samples.
  • n is a coefficient corresponding to the sampling time M.
  • FIG. 2A shows a block diagram of the moving average circuit 111A.
  • the Z ⁇ 1 block means that the digital value of the previous sampling is output.
  • a coefficient multiplication circuit (1 / M) is provided at the final stage of the moving average circuit 111A.
  • digital values X (M), X (M ⁇ 1),. .., X (2), X (1) is summed and multiplied by (1 / M).
  • a coefficient multiplication circuit can be provided in the subsequent stage of the moving average circuit 111A and the differentiation circuit 112. It can be used together with a coefficient multiplication circuit provided at the subsequent stage of the moving average circuit 111A.
  • FIG. 2B shows an example of the frequency characteristic of the moving average circuit 111A
  • FIG. 2C shows an example of the phase characteristic of the moving average circuit 111A.
  • the output of the moving average circuit 111A has a phase delay in the practical frequency range.
  • the differentiation circuit 112 in FIG. 1A has high-pass characteristics, and the compensation amount CQ (n) at time n in time series is expressed by Equation 2.
  • CQ (n) (X (k) ⁇ X (k ⁇ 1)) / ⁇ t (Formula 2)
  • ⁇ t is a discrete time interval
  • k is any value from 2 to M, for example.
  • n is a coefficient corresponding to the sampling time M-1.
  • CQ (n) is a differential value using a discrete value sequence
  • the time interval can be represented by ⁇ 2t as shown in Equation 3.
  • CQ (n) (X (k) ⁇ X (k ⁇ 2)) / ⁇ 2t (Expression 3)
  • k is, for example, any value from 2 to M, for example, any value from 3 to M.
  • FIG. 3A shows an example of the frequency characteristic of the differentiating circuit 112
  • FIG. 3B shows an example of the phase characteristic of the differentiating circuit 112.
  • the adding circuit 113 adds the moving average MQ (n) and the output of the differentiating circuit 112 (compensation amount CQ (n)), so that the influence of the phase delay of MQ (n) depends on CQ (n). Reduced.
  • FIG. 4 is an explanatory view showing another embodiment of the digital signal processing circuit of the present invention.
  • the digital signal processing circuit 11B includes an FIR filter circuit 111B, a differentiating circuit 112, an adding circuit 113, and a coefficient multiplying circuit.
  • the moving average circuit 111B is the first filter circuit of the present invention
  • the differentiation circuit 112 is the second filter circuit of the present invention, like the digital signal processing circuit of FIG.
  • the difference equation at time n in the time series of the FIR filter circuit 111B is expressed by Expression 4.
  • FQ (n) ⁇ a k X (k) (Formula 4)
  • M is the number of samples
  • a k is a weighting coefficient.
  • n is a coefficient corresponding to the sampling time M.
  • FIG. 5 shows a block diagram of the FIR filter circuit 111B.
  • the block of Z ⁇ 1 means that the digital value of the previous sampling is output.
  • a coefficient multiplication circuit (a k ) is provided in the subsequent stage of the block of Z ⁇ 1 , and when X (M) is input to the FIR filter circuit 111B, a M X (M), a M ⁇ 1 X The sum of (M ⁇ 1),..., A 2 X (2), a 1 X (1) is calculated.
  • a coefficient multiplication circuit may be provided at the subsequent stage of the FIR filter circuit 111 ⁇ / b> B and the differentiation circuit 112, similarly to the moving average circuit 111 ⁇ / b> A of FIGS. 1 (A) and 2 (A). it can.
  • the frequency characteristics and phase characteristics of the FIR filter circuit 111B are the same as those shown for the moving average circuit 111A in FIGS. 2B and 2C, and the output FQ (n) of the FIR filter circuit 111B has a practical frequency range. A phase lag occurs.
  • the compensation amount CQ (n) at time n in time series which is the output of the differentiating circuit 112 in FIG.
  • CQ (n) is a differential value using a discrete value sequence, for example, the time interval can be represented by ⁇ 2t, and can be expressed as in Expression 3 described above.
  • a coefficient multiplication circuit is provided at the subsequent stage of the FIR filter circuit 111B and the differentiation circuit 112 as in the moving average circuit 111A of FIGS. 1 (A) and 2 (A). be able to. Also in the digital signal processing circuit 11B of FIG. 4, the phase of the output CQ (n) of the differentiating circuit 112 is advanced in the practical frequency range. Therefore, the addition circuit 113 adds the output FQ (n) of the FIR filter circuit 111B and the output of the differentiation circuit 112 (compensation amount CQ (n)), so that the influence of the phase delay of FQ (n) is CQ. Canceled by (n).
  • FIG. 6 is an explanatory diagram showing an embodiment of the digital control circuit of the present invention.
  • the power conversion circuit is controlled by a digital control circuit having the digital signal processing circuit 11A of FIG. 1 mounted thereon.
  • the power conversion circuit is controlled by the digital control circuit having the digital signal processing circuit 11B of FIG.
  • the following description also applies to the case of controlling the above.
  • the power conversion circuit 2 includes a switch circuit 21 that inputs a voltage Ei from the power supply 4 and an inductor 22 that is connected to the switch circuit 21 and stores and releases energy.
  • the switch circuit 21 includes a load 3. (The inductor 22 may be connected between the switch circuit 21 and the load 3 depending on the power conversion method).
  • the digital control circuit 1 includes an input unit 12, an input comparison unit 13, a digital signal processing circuit 11A, and a control signal output unit 14.
  • the input unit 12 has a signal selection function, and can select either the output voltage eo or the output current io, or can select both the output voltage eo and the output current io.
  • the digital control circuit 1 can perform various controls such as a constant voltage mode, a constant current mode, a power mode, an overcurrent limit mode, and an overvoltage limit mode. For example, when the digital control circuit 1 performs control in the constant voltage mode, the input unit 12 selects only eo, and when the load 3 increases rapidly, the input unit 12 switches to only io selection, The digital control circuit 1 performs control in the overcurrent limit mode. Further, in the process of shifting from the constant voltage mode to the overcurrent limiting mode, the input unit 12 selects both eo and io, performs multiplication of eo and io, and the digital control circuit 1 performs control in the power mode. May be performed.
  • the output of the input unit 12 is set to ad.
  • the voltage detection value is not limited to the instantaneous value eo, but may be an average value or an effective value Eo.
  • the detected current value is not limited to the instantaneous value io, and may be an average value or an effective value Io.
  • the input comparison unit 13 following the input unit 12 includes an operational amplifier 131 and an A / D converter 132.
  • the differential amplifier 131 outputs a difference (ad * ⁇ ad) between the power detection value ad and the target value ad *, and the A / D converter 132 converts the difference (ad * ⁇ ad) into a digital signal, and the deviation. It is output to the digital signal processing circuit 11 as (digital discrete value X).
  • the A / D converter 132 is provided at the subsequent stage of the differential amplifier 131.
  • the differential amplifier 131 in this case, a digital comparator
  • an A / D converter may be provided at the subsequent stage of the A / D converter 132. it can.
  • an A / D converter may be provided in the previous stage of the input unit 12.
  • the input unit 12 is an A / D converter 1211 and 1212 and a digital multiplier 122
  • the comparison unit 13 is a digital comparator.
  • the output of the digital multiplier 122 is indicated by D
  • the comparator 13 inputs the output D and the target value D *, and outputs the digital deviation D * ⁇ D as X.
  • a coefficient multiplication circuit 114 is provided in the subsequent stage of the moving average circuit 111 ⁇ / b> A
  • a coefficient multiplication circuit 115 is provided in the subsequent stage of the differentiation circuit 112.
  • the digital signal processing circuit 11A constitutes a part of the control circuit, performs arithmetic processing of the moving average MQ (n) of the digital deviation D X , and the coefficient multiplication circuit 114 applies a predetermined coefficient K to MQ (n). Multiplying by M , the moving average manipulated variable K M ⁇ MQ (n) is output. Further, the differential circuit 112 performs arithmetic processing of the digital deviation X of the differential value CQ (n), the coefficient multiplying circuit 115 multiplies a predetermined coefficient K D in CQ (n), moving average operation amount K D -Outputs CQ (n).
  • the adder circuit 113 adds the output K A ⁇ MQ (n) of the coefficient multiplier circuit 114 and the output differential value K D ⁇ CQ (n) of the coefficient multiplier circuit 115 to obtain a signal Dc (n) compensated for the phase delay. Output.
  • the circuit for calculating the moving average can also be composed of a shift register as shown in FIG. In FIG. 8A, the circuit for calculating the moving average includes a FIFO 1301, an adder 1302, a shift register 1303, and a coefficient multiplication circuit 1304.
  • the FIFO 1301 sequentially inputs sampling values and stores a plurality of consecutive sampling values.
  • a state is shown in which four sampling values X1, X2, X3, and X4 shown in FIG. 8B are stored.
  • the coefficient multiplication circuit 1304 multiplies ⁇ Xi by a coefficient (including a coefficient (1/4) for averaging) K M / 4, and outputs K M ⁇ (1/4) ⁇ Xi.
  • the shift register 1303 shifts the addition result (for example, binary number: b 1 b 2 b 3 b 4 ) twice to the lower side to calculate (X1 + X2 + X3 + X4) / 2 2, and outputs the shifter 1313 (X1 + X2 + X3 + X4) ) / 2 2 may be multiplied by a coefficient K M to output AM (n).
  • the coefficient multiplication circuit 1304 can be integrated with the shift register 1303.
  • the differentiating circuit 112 can be composed of a FIFO 1121, a subtracting circuit 1122, and a coefficient multiplying circuit 1123.
  • the FIFO 1121 inputs the last two values X 3 and X 4 among X 1, X 2, X 3, and X 4 and outputs these values to the subtraction circuit 1122.
  • Subtraction circuit 1122 outputs the subtracted value (X3-X4) to the coefficient multiplier circuit 1123, the coefficient multiplying circuit 1123 subtracts value (X3-X4) to be multiplied by a coefficient K D derivative value CQ (n) Output.
  • the FIFO 1121 in FIG. 9 can be shared with the FIFO 1301 of the circuit for calculating the moving average shown in FIG.
  • FIG. 10A shows the transient characteristics of the reactor current when the power conversion circuit 2 is simulated by the PID control device
  • FIG. 10B shows the reactor when the power conversion circuit 2 is simulated by the digital control circuit 1. Current transient characteristics are shown. Overshoot when the reactor current flows is greater in FIG. 10 (A), the by choosing appropriately the parameters K M and K D as described above in FIG. 10 (B), the is suppressed.

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Abstract

La présente invention concerne un circuit de traitement de signaux numériques qui parvient à une commande numérique correspondant à une commande PID analogique par l’association d’un premier filtre qui mène le traitement moyen du déplacement, etc., ainsi qu'un second circuit de filtre qui mène le traitement passe-bas, etc., et un circuit de commande numérique dans lequel est monté le circuit de traitement. Le circuit de traitement de signaux numériques (11) est caractérisé en ce qu'il comprend un circuit moyen de déplacement (111A) auquel est appliquée une valeur numérique X, un circuit de différenciation (112) auquel la valeur numérique est appliquée et qui mène un traitement de différenciation, ainsi qu'un circuit d'ajout (113) qui génère un signal d'ajout d'une sortie à partir du circuit moyen de déplacement (111A) et qui forme le circuit de différenciation (112), compensant ainsi le retard de phase généré dans le circuit moyen de déplacement (111A) au moyen de la sortie du circuit de différenciation (112).
PCT/JP2008/067765 2008-09-30 2008-09-30 Circuit de traitement de signaux numériques et circuit de commande numérique WO2010038278A1 (fr)

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PCT/JP2008/067765 WO2010038278A1 (fr) 2008-09-30 2008-09-30 Circuit de traitement de signaux numériques et circuit de commande numérique

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PCT/JP2008/067765 WO2010038278A1 (fr) 2008-09-30 2008-09-30 Circuit de traitement de signaux numériques et circuit de commande numérique

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH066233A (ja) * 1992-06-19 1994-01-14 Hitachi Ltd 移動平均フィルタ、及びこれを用いたａ／ｄ変換器
JPH0854902A (ja) * 1994-05-06 1996-02-27 Vlt Corp フィードバックコントロールシステム
WO2003100782A1 (fr) * 2002-05-28 2003-12-04 Sony Corporation Dispositif et procede de traitement de signal et dispositif de reproduction de donnees numeriques

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH066233A (ja) * 1992-06-19 1994-01-14 Hitachi Ltd 移動平均フィルタ、及びこれを用いたａ／ｄ変換器
JPH0854902A (ja) * 1994-05-06 1996-02-27 Vlt Corp フィードバックコントロールシステム
WO2003100782A1 (fr) * 2002-05-28 2003-12-04 Sony Corporation Dispositif et procede de traitement de signal et dispositif de reproduction de donnees numeriques

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