WO2009152781A1 - 片式电阻器及其制造方法 - Google Patents

片式电阻器及其制造方法 Download PDF

Info

Publication number
WO2009152781A1
WO2009152781A1 PCT/CN2009/072360 CN2009072360W WO2009152781A1 WO 2009152781 A1 WO2009152781 A1 WO 2009152781A1 CN 2009072360 W CN2009072360 W CN 2009072360W WO 2009152781 A1 WO2009152781 A1 WO 2009152781A1
Authority
WO
WIPO (PCT)
Prior art keywords
nickel
layer
electrode
electrode layer
insulating substrate
Prior art date
Application number
PCT/CN2009/072360
Other languages
English (en)
French (fr)
Inventor
杨金波
王鑫培
Original Assignee
Yang Jinbo
Wang Xinpei
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yang Jinbo, Wang Xinpei filed Critical Yang Jinbo
Publication of WO2009152781A1 publication Critical patent/WO2009152781A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips

Definitions

  • the present invention relates to a chip resistor and a method of fabricating the same.
  • Chip resistors are one of the small electronic components that are widely used in a variety of small electronic devices.
  • the conventional chip resistor is formed by forming a top electrode layer on the insulating substrate by screen printing, and then sintering the silver electrode at both ends of the insulating substrate at 800 ° C - 100 (rC temperature).
  • a resistive layer is formed by screen printing yttrium oxide paste on the blank areas of the upper electrode layers, and then sintered into a resistive layer at a temperature of 800 ° C to 1000 ° C.
  • the surface of the electrode is plated to form a nickel film, which covers the silver electrode, and then electroplated with tin to form a tin plating layer, covering the nickel layer, thereby forming a chip resistor.
  • Figure 1 shows a cross-sectional view of a conventional chip resistor. This type of chip resistor is fabricated in the following manner.
  • the upper electrode layers 3a, 3b and the back electrode layers 4a, 4b are formed by screen printing on the upper and lower surfaces of the alumina insulating substrate 1 having a purity of 95% - 98%, at a temperature of 800 ° C - 1000 ° C Sintered into a 4 ⁇ electrode.
  • the resistive layer 2 is formed by screen printing between the upper electrode layers 3a, 3b of the alumina insulating substrate 1, and then sintered into a resistive layer 2 at a temperature of 800 ° C - 1000 ° C to be bonded to the upper electrode layers 3a, 3b.
  • a glass protective layer 8 is formed by screen printing to cover the entire resistive layer 2, and is sintered into a glass protective layer 8 at a temperature of 500 ° C to 700 ° C.
  • the end surface electrode layers 6a, 6b are formed by vacuum sputtering to be connected to the upper electrode layers 3a, 3b and the back electrode layers 4a, 4b, respectively.
  • an electroplated nickel layer 7a, 7b is formed on the surfaces of the upper electrode layers 3a, 3b, the end surface electrode layers 6a, 6b, and the back electrode layers 4a, 4b by electroplating, and then the surface of the electroplated nickel layers 7a, 7b is plated by electroplating.
  • the electroplated tin layers 9a, 9b are formed in such a manner that a chip resistor is formed.
  • the chip resistor formed by this method can cause the electroplated nickel layers 7a, 7b to be separated from the upper electrode layers 3a, 3b due to the high temperature during soldering of the client in actual use, thereby causing the solder and the upper electrode layer of the client. A chemical reaction occurs in 3a, 3b, causing chip resistor failure.
  • the present invention has been made to solve the above problems, and to provide a nickel or nickel-base alloy electrode chip resistor having a low production cost, a large amount of energy saving, and a more reliable electrical performance of a resistor, and a method of manufacturing the same.
  • a nickel or nickel-based alloy electrode chip resistor of the present invention comprises at least: an insulating substrate, a resistive layer formed on at least one side of the insulating substrate, and at least at an end of the resistive layer a pair of upper electrode layers formed on the upper surface of the insulating substrate and the upper surface of the insulating substrate, wherein the resistive layer and the electrode layer are bonded together by metal-metal physical bonding, and the electrode layer is nickel or nickel Base alloy layer.
  • a pair of nickel or nickel-based alloy back electrode layers formed on the back surface of the insulating substrate and/or a side surface of the insulating substrate at least partially covering the upper electrode layer and having at least partially covering the back electrode layer
  • the upper electrode layer is bonded to the resistive layer and the insulating substrate by vacuum arc ion plating of nickel or a nickel-based alloy.
  • the back electrode layer and/or the end face electrode layer are bonded to the insulating substrate by vacuum arc ion plating of nickel or a nickel-based alloy.
  • the resistance layer is formed by high-temperature sintering of a cerium oxide slurry or vacuum sputtering of NiCr or NiCrS i using a nickel-based alloy, and the resistance of the electrode layer is smaller than the resistance of the resistance layer.
  • the resistor made by the above method since nickel or a nickel-based alloy is used instead of silver as an electrode, the above-mentioned metal layer separation and chemical reaction phenomenon are not generated in actual use, and not only the resistance electrical property requirement can be fully satisfied, but also The processing program is reduced, the reliability of the resistor is greatly improved, and the chip resistor having excellent electrical performance can be manufactured efficiently and at low cost.
  • DRAWINGS 1 is a cross-sectional view of a conventional chip silver electrode resistor.
  • Fig. 2 is a cross-sectional view showing a nickel or nickel-base alloy electrode thick film chip resistor according to a first embodiment of the present invention.
  • Fig. 3 is a manufacturing flow chart of the second embodiment.
  • Figure 4 is a cross-sectional view showing a thick film resistor of a nickel or nickel-base alloy electrode according to a second embodiment of the present invention.
  • Figure 5 is a manufacturing flow chart of Embodiment 2 of the present invention.
  • Figure 6 is a cross-sectional view showing a nickel or nickel-base alloy electrode film chip resistor of Example 3 of the present invention.
  • Figure 7 is a manufacturing flow chart of Embodiment 3 of the present invention.
  • chip resistors or chip resistors referred to in the present invention include thin film chip resistors and thick film chip resistors unless otherwise specified.
  • the nickel or nickel-based alloy electrode chip resistor of the present invention comprises at least: an insulating substrate 1 having a resistive layer 2 formed on at least one side of the insulating substrate, and at least a pair of upper electrode layers 3a, 3b that are in contact with the upper surface of the end of the resistive layer and the upper surface of the insulating substrate, the resistive layer 2 and the electrode layers 3a, 3b are physically joined by metal-metal
  • the electrode layer is a nickel or nickel based alloy layer.
  • a pair of nickel or nickel-based alloy back electrode layers 4a, 4b formed on the back surface of the insulating substrate, and a pair of nickel at least partially covering the upper electrode layer and at least partially covering the back electrode layer are formed on the side surface of the insulating substrate
  • the end face electrode layers 6a, 6b are directly made of nickel or a nickel-based alloy instead of silver as an electrode and the end or portion of the resistive layer is combined with the end of the resistive layer, and the above metal layer separation and chemical reaction phenomenon are not generated in actual use. It can fully meet the requirements of electrical resistance performance, and greatly reduces the processing procedure, greatly improving the reliability of resistor use.
  • the above electrode layers may be combined with a resistive layer by various methods, such as sintering, electroplating, etc., if conditions permit, but nickel or nickel-based alloys are easily oxidized at high temperatures, thereby increasing contact resistance and the like.
  • at least the upper electrode layer is bonded to the resistive layer and the insulating substrate by vacuum arc ion plating of nickel or a nickel-based alloy.
  • a method of ion-plating nickel or a nickel-based alloy by vacuum arc can be used, and an insulating substrate and an adjacent electrode layer can be used. Close or cover together, as shown in Figure 2, Figure 4 and Figure 6.
  • the resistive layer in the present invention is not particularly limited, and may be a thick film resistor, such as a high temperature sintering using a cerium oxide slurry; or a thin film resistor such as vacuum sputtering N i Cr Or N i CrS i or the like, of course, whether it is a thick film resistor or a film resistor, the resistance of the electrode layer should be less than or much smaller than the resistance of the resistor layer.
  • a method for producing a nickel or nickel-base alloy electrode chip resistor of the present invention usually, a resistive layer 2 is formed on at least one side of the insulating substrate 1 (the resistive layer is usually sintered at a high temperature using a cerium oxide paste) And then forming a pair of upper electrode layers 3a, 3b at least in contact with the upper surface of the end portion of the resistive layer 2, wherein the resistive layer 2 and the electrode layers 3a, 3b are physically joined by metal-metal
  • the electrode layer is a nickel or nickel based alloy layer.
  • the resistive layer in the present invention may be formed by sintering a conventional cerium oxide slurry at a high temperature, or may be formed by vacuum sputtering of nickel, nickel-based alloy, N i Cr or N i CrS i , of course.
  • the resistance of the electrode layer should be less than or much less than the resistance of the resistive layer.
  • Fig. 2 is a cross-sectional view showing a thick film resistor of a nickel or nickel-base alloy electrode according to a first embodiment of the present invention.
  • 1 is the insulating substrate of the present invention
  • 2 is the resistive layer of the present invention
  • 3a, 3b are the front end electrode layers of the present invention
  • the resistive layer 2 is yttrium oxide paste by screen printing.
  • the material is printed on the insulating substrate 1 by sintering, and thereafter, the mask pattern of the front end electrode layers 3a, 3b and the back end electrode layers 4a, 4b is formed by screen printing, using vacuum arc ion plating nickel or nickel base.
  • the upper end electrode layers 3a, 3b and the back end electrode layers 4a, 4b are formed, and then the side electrode layers 6a, 6b are formed by vacuum arc ion plating, and then nickel plating is performed by an electroplating process. Layer and tin plating.
  • the oxidized cerium oxide of the present invention is sintered at 800 ° C - 1 000 ° C to form a film.
  • the invention adopts glass or polymer slurry after the preparation of the resistive layer 2 and the glass protective layer 8
  • the resistive layer 2 is masked and then dried at 8 ⁇ TC-20 (rC temperature to form a positive and negative electrode layer pattern as shown in the figure.
  • the prepared substrate 1 is placed in a vacuum arc ion plating chamber
  • the upper end electrode layer 3a 3b and the back end electrode layers 4a, 4b are formed by vacuum arc ion plating nickel or a nickel-based alloy, and then the protective layer 5 is formed of a resin as the resistive layer 2 by screen printing.
  • the film is cured at a temperature of 100 ° C to 250 ° C, and then the chip resistor is folded into strips.
  • the side electrode layers 6a 6b are formed by vacuum ion plating. After the process is completed, the process is completed. , the chip resistor is folded into a granular shape, and the nickel plating layer 7a 7b is placed in the plating bath, and the tin layer 9a 9b is further plated.
  • TCR temperature coefficient of resistance
  • ST0L short-time overload test
  • BS bending test
  • Fig. 4 is a cross-sectional view showing a nickel or nickel-base alloy thick film chip resistor according to a second embodiment of the present invention
  • Fig. 5 is a flow chart showing the manufacture of a nickel or nickel-base alloy thick film chip resistor according to a second embodiment of the present invention.
  • the manufacture of the chip resistor can be omitted by directly using a nickel or a nickel-based alloy as an electrode material, and the electroplating process of the first embodiment can be omitted, and the electrode layer 3a, 3b, the end electrode layer 6a can be directly applied by electroplating. 6,b, the surfaces of the back electrode layers 4a, 4b are directly tinned as a solder layer.
  • Example 3
  • Figure 6 is a cross-sectional view showing a sheet-type resistor of a nickel or nickel-based alloy film of Example 3
  • Figure 7 is a flow chart for manufacturing a sheet resistor of a nickel or nickel-base alloy film of Example 3.
  • the resistive layer 2 of the present example no longer employs a film forming method of screen printing thick film technology, but forms the resistive layer 2 by a vacuum sputtering method using NiCr and/or NiCrS i as a resistive material of the resistive layer.
  • a resistive pattern is formed by using a screen printing mask, and then sputtered into a resistive layer; then, the upper end electrode layers 3a, 3b, the back end electrode layers 4a, 4b are patterned by screen printing, and a vacuum arc is used.
  • Ion plating nickel or The method of the nickel-based alloy forms the upper end electrode layers 3a, 3b, the back end electrode layers 4a, 4b, and thereafter the vacuum-arc ion plating method is used to form the side electrode layers 6a, 6b, after 1 00-200 °. C, 4-1 0 hour tempering treatment, the chip resistor is folded into a granular shape, placed in a plating bath, and a solder layer is plated.
  • the nickel or nickel-based alloy film chip resistor produced by the embodiment 3 of the present invention has excellent electrical properties, and a low temperature coefficient of resistance (TCR) and a preferable short-time overload and good bending resistance test can be obtained.
  • TCR temperature coefficient of resistance

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Description

片式电阻器及其制造方法 技术领域
本发明涉及一种片式电阻器及其制造方法。
背景技术
随着近年来手机、 笔记本电脑、 MP3、 MP4等小型电子设备的发展， 对广泛 应用于电子电路中的小型电子元件的需求也在日益增加。 片式电阻则是小型电 子元件中的一种， 其广泛应用于各种小型电子设备当中。
传统的片式电阻器制作是在绝缘基片上通过丝网印刷的方法形成上面两端 电极层， 然后在 800°C-100(rC温度下烧结制成绝缘基片上面两端的银电极。 其 后， 在上面两端电极层空白区域通过丝网印刷氧化钌浆料制成电阻层， 再在 800 °C-1000°C温度下烧结成电阻层。 为了确保焊接工艺的可靠性， 最后， 在银电极 表面电镀形成镍膜， 覆盖银电极， 再电镀锡形成镀锡层， 覆盖镍层， 由此制成 片式电阻器。
图 1 展示的是传统片式电阻器剖面图。 这种类型的片式电阻器按以下方式 制造。
首先， 在纯度为 95% - 98%的氧化铝绝缘基片 1的上面及背面通过丝网印刷 形成上面电极层 3a， 3b和背面电极层 4a， 4b, 在 800°C— 1000°C温度下烧结成 4艮 电极。 在氧化铝绝缘基片 1的上面电极层 3a， 3b间通过丝网印刷形成电阻层 2, 然后在 800°C— 1000°C温度下烧结成电阻层 2, 使之与上面电极层 3a， 3b连接， 再通过丝网印刷形成玻璃保护层 8复盖整个电阻层 2, 在 500°C— 700°C温度下 烧结成玻璃保护层 8。
然后采用真空溅射的方法形成端面电极层 6a，6b, 使之分别与上面电极层 3a，3b和背面电极层 4a，4b连接。 然后采用电镀的方法在上面电极层 3a， 3b、 端 面电极层 6a，6b、 背面电极层 4a， 4b的表面形成电镀镍层 7a， 7b, 再通过电镀的 方法在电镀镍层 7a， 7b的表面形成电镀锡层 9a， 9b,由此方式制成片式电阻。 采用这种方法制成的片式电阻器在实际使用中由于客户端焊接时的高温极 易造成电镀镍层 7a，7b与上面电极层 3a，3b分离， 而造成客户端的锡焊料与上 面电极层 3a， 3b发生化学反应， 导致片式电阻器故障。
发明内容
本发明就是为了解决上述问题， 提供一种生产成本低， 大量节约能源， 电 阻的电气性能更加可靠的镍或镍基合金电极片式电阻器及其制造方法。 为达到上述目的， 本发明的镍或镍基合金电极片式电阻器，至少包括： 绝缘 基片， 在所述的绝缘基片至少一面上形成有电阻层， 以及至少在所述电阻层端 部的上面及绝缘基片上面面接触形成的一对上面电极层， 所述的电阻层与所述 的电极层是通过金属 -金属间物理接合而结合在一起， 所述的电极层为镍或镍基 合金层。 特别是， 在所述绝缘基片背面形成的一对镍或镍基合金背面电极层和 /或在 所述绝缘基片侧面形成有至少部分覆盖上面电极层和有至少部分覆盖背面电极 层的一对镍端面电极层。 特别是， 至少上面电极层是通过真空电弧离子镀镍或镍基合金的方法与所 述的电阻层及绝缘基片结合在一起。 特别是， 所述背面电极层和 /或端面电极层是通过真空电弧离子镀镍或镍基 合金的方法与绝缘基片结合在一起。 特别是， 所述电阻层是采用氧化钌浆料高温烧结而成或采用镍基合金真空 溅射 NiCr或 NiCrS i而成， 所述电极层的电阻小于所述电阻层的电阻。
采用上述方法制成的电阻器， 由于用镍或镍基合金代替银做为电极， 在实 际使用中不会再产生上述金属层分离和化学反应现象， 不仅完全可以满足电阻 电气性能的要求， 而且减少了加工程序， 极大地提高电阻器使用的可靠性， 可 以高效、 低成本制造出电气性能出色的片式电阻器。
附图说明 图 1是传统片式银电极电阻器的剖面图。
图 2 是本发明实施例 1的镍或镍基合金电极厚膜片式电阻器的剖面图 图 3是实施例 2的制造流程图。
图 4是本发明实施例 2的镍或镍基合金电极厚膜片式电阻器的剖面图。 图 5是本发明实施例 2的制造流程图。
图 6是本发明实施例 3的镍或镍基合金电极薄膜片式电阻器的剖面图。 图 7是本发明实施例 3的制造流程图。
具体实施方式
下面结合附图和实施例对本发明作进一步地说明。 本发明所称的片式电阻或片式电阻器除有特殊指明的外，包括薄膜片式电 阻器和厚膜片式电阻器。
如图 2至图 7所示， 本发明的镍或镍基合金电极片式电阻器，其至少包括： 绝缘基片 1 , 在所述的绝缘基片至少一面上形成有电阻层 2 , 以及至少在所述电 阻层端部的上面及绝缘基片上面面接触的一对上面电极层 3a、 3b , 所述的电阻 层 2与所述的电极层 3a、 3b是通过金属 -金属间物理接合而结合在一起， 所述 的电极层为镍或镍基合金层。 在所述绝缘基片背面形成的一对镍或镍基合金背 面电极层 4a、 4b , 在所述绝缘基片侧面形成有至少部分覆盖上面电极层和有至 少部分覆盖背面电极层的一对镍端面电极层 6a、 6b , 直接采用镍或镍基合金代 替银做为电极与电阻层端部或部分与电阻层端部结合， 在实际使用中不会再产 生上述金属层分离和化学反应现象， 可以完全满足电阻电气性能的要求， 并且 大大地减少了加工程序， 极大地提高电阻器使用的可靠性。 上述的各电极层在条件允许的情况下， 可采用各种方法与电阻层结合， 例 如烧结、 电镀等， 但考虑镍或镍基合金在高温下极易氧化， 从而增加接触电阻 等问题， 本发明中至少上面电极层是通过真空电弧离子镀镍或镍基合金的方法 与所述的电阻层及绝缘基片结合在一起。 作为背面电极层和端面电极层同样可 采用通过真空电弧离子镀镍或镍基合金的方法与绝缘基片以及相邻的电极层结 合或覆盖在一起， 如图 2、 图 4和图 6所示。 如前所述， 对本发明中的电阻层未做特殊限定， 既可以是厚膜式电阻， 如 采用氧化钌浆料高温烧结而成； 也可以是薄膜式电阻， 如采用真空溅射 N i Cr或 N i CrS i 等材质而成， 当然无论是厚膜式电阻还是薄膜式电阻， 其电极层的电阻 应小于或远小于所述电阻层的电阻。 本发明镍或镍基合金电极片式电阻器的制造方法： 通常是在所述的绝缘基 片 1 至少一面上形成有电阻层 2 (该电阻层通常是采用氧化钌浆料高温烧结而 成）；然后至少在所述电阻层 2端部的上面面接触的形成一对上面电极层 3a、 3b , 所述的电阻层 2与所述的电极层 3a、 3b是通过金属 -金属间物理接合而结合在 一起， 所述的电极层为镍或镍基合金层。 在制造过程中， 本发明中的电阻层可采用惯用的氧化钌浆料高温烧结而成， 也可采用真空溅射镍、 镍基合金、 N i Cr或 N i CrS i等材质而成， 当然电极层的电 阻应小于或远小于所述电阻层的电阻。 下面通过实施例和附图作进一步地说明。
实施例 1
图 2是本发明实施例 1 的镍或镍基合金电极厚膜片式电阻器的剖面图。 在 该图中， 1是本发明所述绝缘基片， 2是本发明所述电阻层， 3a，3b是本发明所 述正面两端电极层， 电阻层 2 是通过丝网印刷将氧化钌浆料印刷在绝缘基片 1 上烧结而成， 此后， 通过丝网印刷形成正面两端电极层 3a， 3b和背面两端电极 层 4a，4b 的掩膜图形， 采用真空电弧离子镀镍或镍基合金的方法， 形成上面两 端电极层 3a，3b , 背面两端电极层 4a， 4b , 此后再用真空电弧离子镀的方法形成 侧面两端电极层 6a， 6b,然后再利用电镀工艺形成镀镍层和镀锡层。
下面结合图 3详细说明制作该片式电阻器的方法
本发明电阻浆料氧化钌在 800 °C -1 000 °C烧结成膜。
本发明是在电阻层 2及玻璃保护层 8制备完成后采用玻璃或高分子浆料将 其电阻层 2进行掩膜， 然后在 8{TC-20(rC温度下干燥， 形成如图所示的正背面 两端电极层图形。 将制备好的基片 1 放入到真空电弧离子镀膜室中， 采用真空 电弧离子镀镍或镍基合金的方法形成上面两端电极层 3a 3b和背面两端电极层 4a, 4b,然后通过丝网印刷， 由树脂形成保护层 5作为电阻层 2的保护膜，在 100 °C-250°C的条件下， 固化树脂， 再将片式电阻折成条， 露出两端后利用真空离 子镀膜的方法形成侧面两端电极层 6a 6b，上述制程工艺结束后， 将片式电阻折 成粒状， 放入电镀槽中镀镍层 7a 7b, 再镀锡层 9a 9b, 这样制成的片式电阻元 件的电阻温度系数（TCR), 短时过载实验（ST0L)，弯曲实验（BS)如下表所示：
TCR
Figure imgf000007_0001
短时间过负荷
Figure imgf000007_0002
表 2 Bending Tes t
Figure imgf000008_0001
表 3 实施例 2
图 4是本发明实施例 2的镍或镍基合金厚膜片式电阻器剖面图， 图 5是本 发明实施例 2的镍或镍基合金厚膜片式电阻器的制造流程图。
该片式电阻的制造由于直接采用了镍或镍基合金作为电极材料， 可以将实 施例 1的镀镍工序省掉， 而直接通过电镀的方法， 在上面电极层 3a，3b，端面电 极层 6a， 6b , 背面电极层 4a， 4b的表面直接镀锡来作为焊锡层。 实施例 3
图 6是实施例 3的镍或镍基合金薄膜片式电阻的剖面图， 图 7是实施例 3 的镍或镍基合金薄膜片式电阻的制造流程图
下面结合图 6图 7详细说明实施例 3镍或镍基合金薄膜片式电阻的制造方 法。 本实例的电阻层 2 不再采用丝网印刷厚膜技术的成膜方法， 而是通过真空 溅射的方法用 NiCr和 /或 NiCrS i作为电阻层的电阻材料形成电阻层 2。 首先采 用丝网印刷掩膜制成电阻图形，然后溅射成电阻层； 接着用丝网印刷形成上面两 端电极层 3a， 3b,背面两端电极层 4a， 4b的掩膜图形， 采用真空电弧离子镀镍或 镍基合金的方法形成上面两端电极层 3a， 3b,背面两端电极层 4a， 4b,此后再利用 真空电弧离子镀的方法制成侧面两端电极层 6a， 6b,经过 1 00-200 °C， 4-1 0小时的 回火处理， 将片式电阻折成粒状， 放入电镀槽中， 镀上焊锡层
采用本发明实施例 3制成的镍或镍基合金薄膜片式电阻的电气性能极佳， 可获得较低的电阻温度系数（TCR )及较佳的短时间过载与良好的抗弯曲试验。 以上虽然结合附图描述了本发明的实施方式， 但是本领域技术人员可 以在权利所要求的范围内做出各种变形或修改。

Claims

权利要求书
1、 一种镍或镍基合金电极片式电阻器，至少包括： 绝缘基片， 在所述的绝 缘基片至少一面上形成电阻层， 以及至少在所述电阻层端部的上面及绝缘基片 上面面接触形成的一对上面电极层， 所述的电阻层与所述的电极层是通过金属- 金属间物理接合而结合在一起， 其特征在于： 所述的电极层为镍或镍基合金层。
2、 如权利要求 1的镍或镍基合金电极片式电阻器， 其特征在于： 在所述绝 缘基片背面形成的一对镍或镍基合金背面电极层。
3、 如权利要求 2的镍或镍基合金电极片式电阻器， 其特征在于： 在所述绝 缘基片侧面形成有至少部分覆盖上面电极层和有至少部分覆盖背面电极层的一 对镍端面电极层。
4、 如权利要求 1或 2或 3所述的镍或镍基合金电极片式电阻器， 其特征在 于： 至少所述上面电极层是通过真空电弧离子镀镍或镍基合金的方法与所述的 电阻层及绝缘基片结合在一起， 所述背面电极层是通过真空电弧离子镀镍或镍 基合金的方法与所述的绝缘基片结合在一起。
5、 如权利要求 1或 2或 3所述的镍或镍基合金电极片式电阻器， 其特征在 于： 端面电极层是通过真空电弧离子镀镍的方法与所述上面电极层， 背面电极 层及绝缘基片结合在一起。
6、 如权利要求 1或 2或 3所述的镍或镍基合金电极片式电阻器， 其特征在 于：所述电阻层是采用氧化钌浆料高温烧结而成或采用真空溅射 N i C r或 N i C r S i 而成， 所述电极层的电阻小于所述电阻层的电阻。
7、 如权利要求 1或 2或 3所述的镍或镍基合金电极片式电阻器， 其特征在 于： 通过真空电弧离子镀镍或镍基合金形成的上面电极层， 背面电极层和端面 电极层， 再通过电镀的方法在上面电极层， 背面电极层和端面电极层形成镍层， 最后再镍层表面电镀锡层。
8、 如权利要求 1或 2或 3所述的镍或镍基合金电极片式电阻器， 其特征在 于： 通过真空电弧离子镀镍或镍基合金形成的上面电极层， 背面电极层和端面 电极层是直接通过电镀形成镀锡层。
9、 一种镍或镍基合金电极片式电阻器制造方法， 其特征在于： 在所述的绝 缘基片至少一面上形成有电阻层； 至少在所述电阻层端部的上面面接触形成的 一对上面电极层， 所述的电阻层与所述的电极层是通过金属 -金属间物理接合而 结合在一起， 所述的电极层为镍或镍基合金层。
10、 如权利要求 9的镍或镍基合金电极片式电阻器制造方法， 其特征在于： 在所述绝缘基片背面形成的一对镍或镍基合金背面电极层。 在所述绝缘基片侧 面形成有至少部分覆盖上面电极层和有至少部分覆盖背面电极层的一对镍端面 电极层。
11、 如权利要求 9或 10所述的镍或镍基合金电极片式电阻器制造方法， 其 特征在于： 至少上面电极层是通过真空电弧离子镀镍或镍基合金的方法与所述 的电阻层及绝缘基片结合在一起， 所述背面电极层是通过真空电弧离子镀镍或 镍基合金的方法与所述的绝缘基片结合在一起。
12、 如权利要求 9或 10所述的镍或镍基合金电极片式电阻器制造方法， 其 特征在于： 端面电极层是通过真空电弧离子镀镍的方法与与所述上面电极层， 背面电极层及绝缘基片结合在一起。
13、 如权利要求 9或 10所述的镍或镍基合金电极片式电阻器制造方法， 其 特征在于： 所述电阻层是采用氧化钌浆料高温烧结而成或采用真空溅射 NiCr或 NiCrS i而成， 所述电极层的电阻小于所述电阻层的电阻。
PCT/CN2009/072360 2008-06-20 2009-06-19 片式电阻器及其制造方法 WO2009152781A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200810126735.3 2008-06-20
CNA2008101267353A CN101369478A (zh) 2008-06-20 2008-06-20 镍或镍基合金电极片式电阻器及其制造方法

Publications (1)

Publication Number Publication Date
WO2009152781A1 true WO2009152781A1 (zh) 2009-12-23

Family

ID=40413242

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2009/072360 WO2009152781A1 (zh) 2008-06-20 2009-06-19 片式电阻器及其制造方法

Country Status (2)

Country Link
CN (1) CN101369478A (zh)
WO (1) WO2009152781A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101369478A (zh) * 2008-06-20 2009-02-18 杨金波 镍或镍基合金电极片式电阻器及其制造方法
TWI497535B (zh) 2011-07-28 2015-08-21 Cyntec Co Ltd 具有軟性材料層之微電阻元件及其製造方法
CN102903467B (zh) * 2011-07-29 2016-04-06 乾坤科技股份有限公司 具有软性材料层的微电阻元件及其制造方法
CN102800448B (zh) * 2012-08-23 2015-11-04 中国振华集团云科电子有限公司 氮化钽片式薄膜电阻器及其制造方法
WO2016027692A1 (ja) * 2014-08-18 2016-02-25 株式会社村田製作所 電子部品および電子部品の製造方法
CN105336461A (zh) * 2015-11-21 2016-02-17 贝迪斯电子有限公司 一种抗硫化片式厚膜电阻的制作方法
US10242774B2 (en) * 2017-04-27 2019-03-26 Samsung Electro-Mechanics Co., Ltd. Chip resistance element and chip resistance element assembly
CN110364318B (zh) * 2018-03-26 2021-08-17 国巨电子（中国）有限公司 高频电阻器与高频电阻器的制造方法
CN110289143A (zh) * 2019-06-05 2019-09-27 北京七一八友晟电子有限公司 超小型片式厚膜固定电阻器及制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030117258A1 (en) * 2001-12-20 2003-06-26 Samsung Electro-Mechanics Co., Ltd. Thin film chip resistor and method for fabricating the same
JP2003282304A (ja) * 2002-03-25 2003-10-03 Koa Corp チップ抵抗器およびその製造方法
JP2005191206A (ja) * 2003-12-25 2005-07-14 Matsushita Electric Ind Co Ltd 抵抗器およびその製造方法
CN101369478A (zh) * 2008-06-20 2009-02-18 杨金波 镍或镍基合金电极片式电阻器及其制造方法
CN201233778Y (zh) * 2008-06-20 2009-05-06 杨金波 镍或镍基合金电极片式电阻器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030117258A1 (en) * 2001-12-20 2003-06-26 Samsung Electro-Mechanics Co., Ltd. Thin film chip resistor and method for fabricating the same
JP2003282304A (ja) * 2002-03-25 2003-10-03 Koa Corp チップ抵抗器およびその製造方法
JP2005191206A (ja) * 2003-12-25 2005-07-14 Matsushita Electric Ind Co Ltd 抵抗器およびその製造方法
CN101369478A (zh) * 2008-06-20 2009-02-18 杨金波 镍或镍基合金电极片式电阻器及其制造方法
CN201233778Y (zh) * 2008-06-20 2009-05-06 杨金波 镍或镍基合金电极片式电阻器

Also Published As

Publication number Publication date
CN101369478A (zh) 2009-02-18

Similar Documents

Publication Publication Date Title
WO2009152781A1 (zh) 片式电阻器及其制造方法
TW201007780A (en) Resistive component and making method thereof
US20110089025A1 (en) Method for manufacturing a chip resistor having a low resistance
US6856234B2 (en) Chip resistor
TW408342B (en) Resistor and its manufacturing method
JPH11222664A (ja) メタルマスク、このメタルマスクを用いた抵抗体の形成方法およびこのメタルマスクを用いた抵抗器の製造方法
TWI230453B (en) Over-current protection device and manufacturing method thereof
JP4083971B2 (ja) 積層セラミック電子部品及びその製造方法
CN101399100A (zh) 热敏电阻芯片及其制造方法
TW200901236A (en) Chip resistor and method for fabricating the same
CN201233778Y (zh) 镍或镍基合金电极片式电阻器
JP2004200373A (ja) 電子部品および製造方法
JP2006287063A (ja) 電子部品
JP3665591B2 (ja) チップ抵抗器
CN101364463A (zh) 芯片电阻器及其制法
KR102021667B1 (ko) 베이스 금속 또는 베이스 금속 합금의 전극들을 가지는 높은 전도성이 있는 낮은 저항 칩 레지스터를 제조하는 방법
CN219370713U (zh) 一种玻璃基表贴式点火电阻器
JP3092451B2 (ja) 角形薄膜チップ抵抗器およびその製造方法
JP2004319195A (ja) チップ型ヒューズ
TWM345324U (en) Electrode plate resistor of nickel or nickel-based alloy
KR101148259B1 (ko) 칩 저항기 및 그 제조방법
CN116913630A (zh) 芯片电阻器及芯片电阻器的制造方法
JP2008244211A (ja) 薄膜チップ抵抗器の製造方法
TWI325139B (zh)
JP2009076838A (ja) サーミスターチップおよびその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09765420

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09765420

Country of ref document: EP

Kind code of ref document: A1