WO2009116202A1 - 実装基板、実装基板セット、およびパネルユニット - Google Patents
実装基板、実装基板セット、およびパネルユニット Download PDFInfo
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- WO2009116202A1 WO2009116202A1 PCT/JP2008/070383 JP2008070383W WO2009116202A1 WO 2009116202 A1 WO2009116202 A1 WO 2009116202A1 JP 2008070383 W JP2008070383 W JP 2008070383W WO 2009116202 A1 WO2009116202 A1 WO 2009116202A1
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
Definitions
- the present invention relates to a mounting board set that is a mounting board on which a mounting board, circuit elements, and the like are mounted, and a panel unit that is a panel (liquid crystal display panel or the like) including the mounting board set.
- the mounting substrate 111 (specifically, the base of the mounting substrate 111 and The main substrate 112) is subjected to plastic deformation. More specifically, the inverted U-shaped wall 151 is formed in a partial region of the main board 112 around the circuit element 121.
- a circuit generated in the mounting substrate 111 that does not include the inverted U-shaped wall 151 as shown in FIGS. 11A and 11B (a cross-sectional view taken along line aa ′ in FIG. 11A).
- the element 121 is peeled off, for example, the corner of the circuit element 121 where the fillet 152 of the adhesive 131 is difficult to be formed is not peeled off from the mounting substrate 111 (note that an arrow f in the figure means a load).
- the mounting substrate 111 as described in Patent Document 1 requires a step of plastic deformation, and is limited to a material that can be plastically deformed. Therefore, the manufacturing process of the mounting substrate 111 is troublesome, and a highly versatile material cannot be used for the mounting substrate 111 (the cost of the mounting substrate 111 may increase due to the material cost).
- the bump 122 is preferably connected to a wiring (not shown) included in the mounting substrate 111, and the wiring is preferably covered with a solder resist film.
- the mounting surface 112 ⁇ / b> A of the mounting substrate 111 has the inverted U-shaped wall portion 151, it also becomes a cause of peeling and breaking of the solder resist film.
- the present invention has been made in view of the above situation.
- the object of the present invention is, when a circuit element is mounted, a simple mounting board that prevents the circuit element from peeling from the mounting board, and a mounting board set that is completed by mounting the circuit element on the mounting board,
- Another object of the present invention is to provide a panel set in which the mounting board set and a liquid crystal display panel are connected.
- a mounting board including a supply wiring for supplying current to a circuit element
- the mounting surface area of the mounting board that overlaps the circuit element to be mounted is defined as a mounting area
- at least the mounting surface and the non-mounting surface that is the back surface of the mounting surface Reinforcing wiring that overlaps the corner of the mounting area is formed on one surface.
- the corner of the circuit element overlaps the corner of the mounting area. Therefore, if the vicinity of the corner of the mounting area is bent, the corner of the circuit element may be peeled off from the mounting substrate due to the bending.
- the reinforcing wiring is positioned so as to overlap with the corner of the mounting area, the vicinity of the corner of the mounting area increases in rigidity and does not bend. Therefore, with such a mounting substrate, even if the circuit element is mounted, the corners of the circuit element are not peeled off from the mounting substrate.
- the reinforcing wiring advance from the corner of the mounting area to the outside of the mounting area.
- the bent portion of the mounting board is outside the mounting area where no reinforcing wiring exists. Therefore, the corners of the mounting area are surely not bent, and even if the circuit elements are mounted on the mounting board, the corners of the circuit elements are not peeled off from the mounting board.
- the mounting substrate satisfy the following conditional expression (1) by extending a line that bisects the angle at the corner of the mounting region to a virtual bisector. 0 ⁇ L / D ⁇ 30 Conditional expression (1)
- L The longest length from one end of the virtual bisector that overlaps the corner of the mounting area to the outside of the mounting area and overlaps the virtual bisector and reaches the edge of the reinforcing wiring
- D Reinforcement It is the thickness of the wiring.
- a region for mounting circuit elements (mounting region) must be ensured with high accuracy.
- a solder resist film (first protection) by photolithography capable of forming a film with high accuracy Film) is formed.
- the non-mounting surface does not require film forming accuracy as high as the mounting surface, and thus, for example, a highly rigid cover lay film (second protective film) is formed which is superior to the solder resist film. .
- a protective film that covers at least the supply wiring on the mounting surface is a first protective film (solder resist film, etc.), and a protective film that covers at least the supply wiring on the non-mounting surface is a second protective film (coverlay film, etc.).
- a line that bisects the angle at the corner is extended into a virtual bisector. Then, in the mounting substrate, the shortest distance between one end of the reinforcing wiring that overlaps the virtual bisector and one end of the second protective film that overlaps the virtual bisector is the main substrate that is the base of the mounting substrate and the first protective film. It is desirable to form only with.
- the mounting board can be prevented from bending the mounting area in itself.
- one end that overlaps the bump of the circuit element in the mounting area is set as an electrode overlapping point, and a group of a plurality of electrode overlapping points is set as an electrode overlapping point group, and a line that bisects the angle at the corner of the mounting area is extended.
- Reinforcement wiring when a virtual bisector is used, and a line connecting the electrode overlap points adjacent to each other at the shortest distance between the virtual bisectors at the outermost electrode overlap point in the electrode overlap point group It is desirable to advance from the corner of the mounting area to the inside and beyond the boundary line.
- the reinforcing wiring extends to the center of the mounting area. Therefore, the inside of the mounting area on the mounting substrate is not reliably bent due to the presence of the reinforcing wiring.
- the reinforcing wiring may also serve as the supply wiring. In such a case, even if the bumps of the circuit elements are relatively large and the bump arrangement pitch is narrow, the area of the reinforcing wiring increases.
- an adhesive is interposed between the circuit element and the mounting area. If it becomes like this, a mounting area
- a mounting board set including the above mounting board and a circuit element mounted on the mounting board can also be said to be the present invention.
- the bump included in the circuit element is a mounting board set connected to the supply wiring connected to the electrode overlapping point, a part of the supply wiring connected to the circuit element is not bent due to the presence of the reinforcing wiring. As a result, peeling between the bumps of the circuit element and the supply wiring is prevented.
- a panel unit including the above mounting board set and a liquid crystal display panel connected to the mounting board set can also be said to be the present invention.
- FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2.
- FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 2.
- FIG. 3 is a plan view showing bumps of a circuit element.
- FIG. 11 is a perspective view of a conventional mounting board set different from FIG. 10.
- FIG. 11B is a cross-sectional view taken along the line a-a ′ of FIG. 11A.
- Mounting board 12 Main board 13 Supply wiring 14 Connection wiring (supply wiring) 15 Solder resist film (first protective film) 16 Coverlay film (second protective film) 17 Reinforcing wiring MA Mounting area PP Corner of mounting area AA Open area IL Virtual bisecting line BL Boundary line WL Bending line 21 Circuit element 22 Bump 31 Adhesive PU Liquid crystal display panel ST Mounting board set UT Panel unit
- FIG. 5 is a plan view showing a liquid crystal display panel PU built in an electronic device such as a mobile phone and a mounting board set ST connected to the liquid crystal display panel PU.
- FIG. 2 is an enlarged plan view of the mounting board set ST.
- There is a unit (a unit in which the liquid crystal display panel PU and the mounting substrate set ST are combined is referred to as a panel unit UT).
- 3A and 3B are a cross-sectional view taken along line AA ′ and a cross-sectional view taken along line BB ′ in FIG. 2 (the line AA ′ is a virtual bisector described later). IL).
- the mounting board set ST shown in these drawings includes various circuit elements 21 and a mounting board 11 on which the circuit elements 21 are mounted.
- the circuit element 21 is an ACF (Anisotropic Conductive Film) or NCF (NCF). Mounted with adhesive 31 such as Non Conductive Film ⁇ .
- FIG. 1 which is a plan view excluding the circuit element 21 is added to the above drawings, and the mounting substrate 11 will be described in detail.
- the mounting substrate 11 includes a main substrate 12, a supply wiring 13, a connection wiring 14, a solder resist film (first protective film) 15, a coverlay film (second protective film) 16, and a reinforcing wiring 17.
- the main board 12 is a member that becomes a base of the mounting board 11 and has flexibility. Therefore, the mounting board 11 including the main board 12 is also referred to as an FPC (Flexible Printed Circuits) board.
- FPC Flexible Printed Circuits
- substrate 12 a polyimide resin and PET (polyethylene terephthalate) are mentioned, for example.
- the supply wiring 13 is connected to, for example, a bump (projection electrode) 22 included in the circuit element 21 and supplies a current from a power source (not shown) to the circuit element 21. Therefore, as shown in FIG. 3B, the bump 22 and the supply wiring 13 are connected.
- the supply wiring 13 may be formed on at least one of the front surface (mounting surface) 12A and the back surface (non-mounting surface) 12B of the main substrate 12.
- connection wiring 14 is a wiring formed on the back surface 12B of the main substrate 12, as shown in FIG. 3A, for example, and connects the supply wirings 13 to each other. Note that this connection wiring 14 also plays a role similar to that of the supply wiring 13 in that current is supplied to the circuit element 21, and thus can be said to be a kind of the supply wiring 13.
- the solder resist film 15 is a resin film formed by photolithography, and protects the supply wiring 13 by covering the surface 12A of the main substrate 12 (more specifically, the solder resist film 15 is provided on the mounting surface 12A by the supply wiring 13). Covering at least).
- the solder resist film 15 does not cover the entire surface 12A of the main substrate 12, but as shown in FIG. 1, a partial region (opening region) of the surface 12A on the main substrate 12 on which the circuit element 21 is scheduled to be mounted. AA) is not covered. For this reason, photolithography capable of patterning with high accuracy is used in order to secure a region not covered with the solder resist film 15.
- the cover lay film 16 is a film that covers the wiring (the supply wiring 13 and the connection wiring 14 and the like) formed on the back surface 12B of the main substrate 12 (more specifically, the cover lay film 16 covers the connection wiring 14 on the non-mounting surface 12B. Cover at least the supply wiring 13). Therefore, the coverlay film 16 does not exist in a region where the wiring is not formed on the back surface 12B of the main substrate 12 (for example, a region of the back surface 12B immediately below the circuit element 21).
- the cover lay film 16 is inferior to the solder resist film obtained by photolithography in patterning accuracy, but is higher in insulation and rigidity than the solder resist film 15.
- the reinforcing wiring 17 prevents a part of the mounting substrate 11 from being bent, and determines a place where the mounting substrate 11 is bent. As an example, as shown in FIG. 1, the reinforcing wiring 17 overlaps the corner PP of the mounting area MA that is the area of the surface 12 ⁇ / b> A on the main substrate 12 that overlaps the circuit element 21. Specifically, the reinforcing wiring 17 advances from the corner PP of the mounting area MA to the outside of the mounting area MA.
- the side that deviates from the mounting area MA is bent with the reinforcing wiring 17 as a boundary, not near the corner of the circuit element 21.
- the reinforcing wiring 17 is positioned so as to overlap the corner of the circuit element 21 so that the vicinity of the corner of the circuit element 21 on the mounting substrate 11 can withstand the load F.
- the reinforcing wiring 17 allows the partial region of the mounting board 11 to withstand the load F, so that the partial region of the mounting substrate 11 on the side deviating from the mounting region MA with respect to itself as a boundary. By the bend area.
- the corner of the circuit element 21 is not peeled off from the mounting substrate 11 due to the load F. And if such peeling does not occur, the performance defect (for example, contact failure) of the circuit element 21 does not occur, and the quality as the mounting board set ST is improved.
- the corners of the circuit elements 21 are peeled off from the mounting substrate 11 occupy most of the connection failures of the circuit elements 21 in the mounting substrate set ST (note that the fillet of the adhesive 31 is unlikely to occur at the corners of the circuit elements 21. (This is one reason why the corner of the circuit element 21 is peeled off from the mounting substrate 11). Therefore, if the corners of the circuit element 21 are not peeled off from the mounting substrate 11, the process defects are reduced, and the high-quality mounting substrate installation ST is used for a long time.
- the shape of the reinforcing wiring 17 is not particularly limited.
- it may be a square shape, or may be other polygonal shapes, circular shapes, linear shapes, net shapes, and detour shapes.
- the mounting substrate 11 it is desirable that the following conditional expression (1) is satisfied.
- This conditional expression (1) is from one end of the reinforcing wiring 17 that overlaps the corner PP of the mounting area MA to the outside of the mounting area MA and overlaps the virtual bisector IL and reaches the edge of the reinforcing wiring 17. Is standardized by the length of the thickness of the reinforcing wiring 17. Note that “L” in the figure indicates only the interval of + notation described below.
- the reinforcing wiring 17 overlaps only inside the mounting area MA. Therefore, when the load F is applied to the mounting substrate 11, the mounting substrate 11 does not bend along the bending line WL (see FIG. 2), and the mounting substrate 11 can be bent near the corner of the circuit element 21. As a result, the corners of the circuit element 21 may be peeled off from the mounting substrate 11.
- the mounting substrate 11 when the value of L / D exceeds the upper limit value, the length of the reinforcing wiring 17 overlapping the virtual bisector IL becomes excessively long, and the reinforcing wiring 17 itself is easily bent. Therefore, when the load F is applied to the mounting substrate 11, the mounting substrate 11 may be bent and the reinforcing wiring 17 may be bent. Then, one end of the reinforcing wiring 17 that overlaps the corner of the circuit element 21 (the corner PP of the mounting area MA) may be bent. If the reinforcing wiring 17 is bent in this way, the mounting board 11 is bent near the corner of the circuit element 21, and the corner of the circuit element 21 may be peeled off from the mounting board 11.
- the mounting substrate 11 is not bent near the corner of the circuit element 21 and the corner of the circuit element 21 is not peeled off from the mounting substrate 11. As a result, the performance defect of the circuit element 21 does not occur, and the quality as the mounting board set ST is improved.
- conditional expression (1a) that defines the following conditional ranges is satisfied. 0 ⁇ L / D ⁇ 20 Conditional expression (1a)
- the shortest distance K between one end of the reinforcing wiring 17 that overlaps the virtual bisector IL and one end of the coverlay film 16 that overlaps the virtual bisector IL is the main substrate 12 and the solder. It is desirable to form only with the resist film 15.
- the shortest distance K including two members (main substrate 12 and solder resist film 15) having relatively low rigidity is more easily bent than the distance L including relatively high rigidity reinforcing wiring 17. . Therefore, when the load F is applied to the mounting substrate 11, the interval L in the mounting substrate 11 is bent without bending the interval L in the mounting substrate 11. Therefore, the corners of the circuit element 21 are not reliably peeled off from the mounting substrate 11.
- the reinforcing wiring 17 does not prevent only the corner of the circuit element 21 from being peeled off from the mounting substrate 11.
- the reinforcing wiring 17 does not bend the inside of the mounting area MA in the mounting substrate 11 and reliably prevents the bumps 22 of the circuit element 21 and the supply wiring 13 from peeling off. .
- the reinforcing wiring 17 has only to advance from the corner PP of the mounting area MA to the inside of the mounting area MA.
- the reinforcing wiring 17 that has advanced to the inside of the mounting area MA extends toward the center of the mounting area MA. Therefore, the inside of the mounting area MA on the mounting substrate 11 is not bent due to the presence of the reinforcing wiring 17.
- the reinforcing wiring 17 is more preferably inward from the corner PP of the mounting area MA and advanced beyond the boundary line BL.
- the reinforcing wiring 17 extends further to the center side of the mounting area MA than the front end of the supply wiring 13. Therefore, the inside of the mounting area MA on the mounting substrate 11 is not further bent due to the presence of the reinforcing wiring 17.
- the bumps 22 included in the circuit element 21 may be arranged in a grid as shown in FIG. Then, the electrode overlapping points BP of the mounting area MA corresponding to such circuit elements 21 are arranged in a grid pattern as shown in FIG.
- the electrodes adjacent to each other with the virtual bisector IL sandwiched between them at the shortest distance A line connecting the overlapping points BP can be said to be a boundary line BL.
- the boundary line BL is the outermost electrode at the grouped electrode overlapping point BP.
- the line overlaps the electrode overlapping points BP that are adjacent to each other with the shortest distance between the virtual bisector IL.
- FIG. 1, FIG. 6, and FIG. 8 are summarized, the following can be said. That is, a group of a plurality of electrode overlapping points BP is used as an electrode overlapping point group, and the reinforcing wiring 17 advances from the corner PP of the mounting area MA so as to overlap the shortest outer peripheral range in the electrode overlapping point group. If this is the case, the inside of the mounting area MA on the mounting substrate 11 is not reliably bent due to the presence of the reinforcing wiring 17.
- the reinforcing wiring 17 overlaps the shortest outer peripheral range in the electrode overlapping point group while overlapping its corner with the virtual bisector IL. With this configuration, the interior of the mounting area MA near the corner of the circuit element 21 is not reliably bent due to the presence of the reinforcing wiring 17.
- the reinforcing wiring 17 is formed on the mounting surface 12A of the mounting substrate 11, but is not limited thereto. That is, the supply wiring 17 may be formed on the non-mounting surface 12 ⁇ / b> B of the mounting substrate 11.
- the bump 22 of the circuit element 21 may be connected to the reinforcing wiring 17. That is, the reinforcing wiring 17 may perform the same function as the supply wiring 13 (in short, the reinforcing wiring 17 may also serve as the supply wiring 13).
- the reinforcing wiring 17 The area increases. For example, as shown in FIG. 8, when the electrode overlapping points BP of the mounting area MA are dense, it can be useful that the reinforcing line 17 also serves as the supply line 13.
- the mounting area MA is connected to the circuit element 21 having a relatively high rigidity via the adhesive 31. Therefore, the mounting area MA on the mounting substrate 11 is not bent.
- the mounting area MA is connected to the relatively high-rigidity circuit element 21 and the reinforcing wiring 17 via the adhesive 31.
- the reinforcing wiring 17, the adhesive 31, and the circuit element 21 are stacked in this order on the mounting area MA, and a four-layer structure of the mounting area MA, the reinforcing wiring 17, the adhesive 31, and the circuit element 21 is formed. . Therefore, even if the load F is applied to the mounting substrate 11, the mounting area MA that is part of the multilayer structure is not bent.
- liquid crystal display panel PU was mentioned as a panel, it is not limited to this.
- it may be an organic EL (electroluminescence) panel or a plasma panel.
Abstract
Description
0<L/D≦30 … 条件式(1)
ただし、
L :実装領域の隅に重なる仮想2等分線の一端から、実装領域の外側に向
かい、かつ仮想2等分線に重なって、補強配線の縁に至るまでの最長
の長さ
D :補強配線の厚み長
である。
12 主基板
13 供給配線
14 連絡配線(供給配線)
15 ソルダーレジスト膜(第1保護膜)
16 カバーレイフィルム(第2保護膜)
17 補強配線
MA 実装領域
PP 実装領域の隅
AA 開口領域
IL 仮想2等分線
BL 境界線
WL 屈曲線
21 回路素子
22 バンプ
31 接着剤
PU 液晶表示パネル
ST 実装基板セット
UT パネルユニット
実施の一形態について、図面に基づいて説明すれば、以下の通りである。なお、便宜上、ハッチングや部材符号等を省略する場合もあるが、かかる場合、他の図面を参照するものとする。
ただし、
L :実装領域MAの隅PPに重なる補強配線17の一端から、実装領域MA
の外側に向かい、かつ仮想2等分線ILに重なって、補強配線17の縁
に至るまでの最長の長さ(ただし、仮想2等分線ILに重なって、実装
領域MAの外側に向かって延びるLは “+”表記され、実装領域MA
の内側に向かって延びるLは“-”表記される)
D :補強配線17の厚み長
である。
0<L/D≦20 … 条件式(1a)
なお、本発明は上記の実施の形態に限定されず、本発明の趣旨を逸脱しない範囲で、種々の変更が可能である。
Claims (12)
- 回路素子に対して電流供給する供給配線を含む実装基板にあって、
実装される上記回路素子に重なる上記実装基板の実装面の領域を実装領域とすると、
上記実装面および上記実装面の裏面である非実装面の少なくとも一方の面に、上記実装領域の隅に重なる補強配線が形成される実装基板。 - 上記補強配線は、上記実装領域の隅から、上記実装領域の外側へと進出する請求項1に記載の実装基板。
- 上記実装領域の隅における角度を2等分する線を延ばして仮想2等分線とし、
下記条件式(1)が満たされる請求項2に記載の実装基板。
0<L/D≦30 … 条件式(1)
ただし、
L :上記実装領域の隅に重なる上記仮想2等分線の一端から、上記実装領
域の外側に向かい、かつ上記仮想2等分線に重なって、上記補強配線
の縁に至るまでの最長の長さ
D :上記補強配線の厚み長
である。 - 上記実装面における上記供給配線を少なくとも覆う保護膜を第1保護膜、上記非実装面における上記供給配線を少なくとも覆う保護膜を第2保護膜とし、
上記実装領域の隅における角度を2等分する線を延ばして仮想2等分線とすると、
上記仮想2等分線に重なる上記補強配線の一端と上記仮想2等分線に重なる上記第2保護膜の一端との最短間隔は、上記実装基板の基体である主基板と上記第1保護膜とだけで形成される請求項1に記載の実装基板。 - 上記補強配線は、上記実装領域の隅から、上記実装領域の内側へと進出する請求項1に記載の実装基板。
- 上記実装領域にて上記回路素子のバンプに重なる一端を電極重畳点とするとともに、複数の電極重畳点の集まりを電極重畳点群とし、
上記実装領域の隅における角度を2等分する線を延ばして仮想2等分線とし、
上記電極重畳点群での最外の電極重畳点において、仮想2等分線を挟みかつ最短距離で隣り合う上記電極重畳点同士を結ぶ線を境界線とすると、
上記補強配線は、上記実装領域の隅から内側に向かい、上記境界線を越えて進出する請求項5に記載の実装基板。 - 上記補強配線が、上記供給配線も兼ねる請求項1に記載の実装基板。
- 上記回路素子と上記実装領域との間に接着剤が介在する請求項1に記載の実装基板。
- 請求項1~8のいずれか1項に記載の実装基板と、
上記実装基板に実装された回路素子と、
を含む実装基板セット。 - 請求項6に記載の実装基板と、
上記実装基板に実装された回路素子と、
を含み、
上記回路素子に含まれるバンプが、上記電極重畳点につながる上記供給配線に接続される実装基板セット。 - 請求項9に記載の実装基板セットと、
上記実装基板セットにつながる液晶表示パネルと、
を含むパネルユニット。 - 請求項10に記載の実装基板セットと、
上記実装基板セットにつながる液晶表示パネルと、
を含むパネルユニット。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/933,159 US20110019125A1 (en) | 2008-03-19 | 2008-11-10 | Mounted board, mounted board set, and panel unit |
CN2008801278657A CN101960587B (zh) | 2008-03-19 | 2008-11-10 | 安装基板、安装基板组件和面板单元 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-070671 | 2008-03-19 | ||
JP2008070671 | 2008-03-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009116202A1 true WO2009116202A1 (ja) | 2009-09-24 |
Family
ID=41090619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/070383 WO2009116202A1 (ja) | 2008-03-19 | 2008-11-10 | 実装基板、実装基板セット、およびパネルユニット |
Country Status (3)
Country | Link |
---|---|
US (1) | US20110019125A1 (ja) |
CN (1) | CN101960587B (ja) |
WO (1) | WO2009116202A1 (ja) |
Cited By (4)
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---|---|---|---|---|
JP2013191898A (ja) * | 2013-07-04 | 2013-09-26 | Rohm Co Ltd | 半導体装置 |
US9117774B2 (en) | 2004-09-28 | 2015-08-25 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
CN106330212A (zh) * | 2016-08-31 | 2017-01-11 | 联想(北京)有限公司 | 载波聚合接收装置及射频前端装置 |
US11842972B2 (en) | 2004-09-28 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5452290B2 (ja) * | 2010-03-05 | 2014-03-26 | ラピスセミコンダクタ株式会社 | 表示パネル |
KR20140026844A (ko) * | 2012-08-23 | 2014-03-06 | 삼성전자주식회사 | 디바이스로부터의 결제 요청을 인증하는 방법 및 시스템 |
JP7202785B2 (ja) * | 2018-04-27 | 2023-01-12 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11163475A (ja) * | 1997-11-27 | 1999-06-18 | Nec Corp | 電子部品を実装したフレキシブル回路基板ユニット |
JP2000068328A (ja) * | 1998-08-21 | 2000-03-03 | Olympus Optical Co Ltd | フリップチップ実装用配線基板 |
JP2004356144A (ja) * | 2003-05-27 | 2004-12-16 | Fujikura Ltd | 部品実装フレキシブル回路基板 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4251129B2 (ja) * | 2004-10-25 | 2009-04-08 | セイコーエプソン株式会社 | 実装構造体、電気光学装置及び電子機器 |
-
2008
- 2008-11-10 US US12/933,159 patent/US20110019125A1/en not_active Abandoned
- 2008-11-10 WO PCT/JP2008/070383 patent/WO2009116202A1/ja active Application Filing
- 2008-11-10 CN CN2008801278657A patent/CN101960587B/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11163475A (ja) * | 1997-11-27 | 1999-06-18 | Nec Corp | 電子部品を実装したフレキシブル回路基板ユニット |
JP2000068328A (ja) * | 1998-08-21 | 2000-03-03 | Olympus Optical Co Ltd | フリップチップ実装用配線基板 |
JP2004356144A (ja) * | 2003-05-27 | 2004-12-16 | Fujikura Ltd | 部品実装フレキシブル回路基板 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9117774B2 (en) | 2004-09-28 | 2015-08-25 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US9721865B2 (en) | 2004-09-28 | 2017-08-01 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US9831204B2 (en) | 2004-09-28 | 2017-11-28 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US10522494B2 (en) | 2004-09-28 | 2019-12-31 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US10818628B2 (en) | 2004-09-28 | 2020-10-27 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US11355462B2 (en) | 2004-09-28 | 2022-06-07 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US11842972B2 (en) | 2004-09-28 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
JP2013191898A (ja) * | 2013-07-04 | 2013-09-26 | Rohm Co Ltd | 半導体装置 |
CN106330212A (zh) * | 2016-08-31 | 2017-01-11 | 联想(北京)有限公司 | 载波聚合接收装置及射频前端装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101960587B (zh) | 2012-10-03 |
CN101960587A (zh) | 2011-01-26 |
US20110019125A1 (en) | 2011-01-27 |
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