WO2009090974A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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WO2009090974A1
WO2009090974A1 PCT/JP2009/050417 JP2009050417W WO2009090974A1 WO 2009090974 A1 WO2009090974 A1 WO 2009090974A1 JP 2009050417 W JP2009050417 W JP 2009050417W WO 2009090974 A1 WO2009090974 A1 WO 2009090974A1
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Prior art keywords
well region
semiconductor device
low
forming
concentration diffusion
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PCT/JP2009/050417
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English (en)
Japanese (ja)
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Masayasu Tanaka
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Nec Corporation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MISFET whose source and drain electrodes are in Schottky contact with a channel region in a semiconductor substrate, and a manufacturing method thereof.
  • MISFET Metal-Insulator-Semiconductor Field Effect Transistor
  • MISFET Metal-Insulator-Semiconductor Field Effect Transistor
  • a metal electrode made of a compound of a metal such as a refractory metal or a noble metal and a semiconductor is used as a source electrode and a drain electrode, and a Schottky junction is formed on a semiconductor substrate.
  • a formed Schottky-Source / Drain (SSD) -MISFET structure has been proposed.
  • an LSI (Large-Scale Integration) circuit in which a MISFET is integrated on a semiconductor substrate is required to suppress various leakage currents generated in the MISFET and reduce standby power consumption.
  • One of the leakage currents is a junction leakage current that flows between the source and drain electrodes and the semiconductor substrate (substrate electrode).
  • the SSD-MISFET in order to reduce the junction leakage current, it is preferable to use a material that has a high junction potential barrier (Schottky barrier) with respect to the substrate for the metal electrodes constituting the source and drain electrodes. .
  • Schottky barrier junction potential barrier
  • Patent Document 1 describes a technique using a material having a high potential barrier. Specifically, bulk Si crystal is used as a semiconductor substrate, and Er silicide or Yb silicide is used for an N-type MISFET and Pt silicide or Ir silicide is used for a P-type MISFET as a metal electrode. Patent Document 2 describes a technique for reducing junction leakage current by using an SOI (Silicon-on-Insulator) substrate as a semiconductor substrate in addition to using the above materials.
  • SOI Silicon-on-Insulator
  • the junction leakage current can be significantly suppressed by using the SOI substrate.
  • the SOI substrate has a problem that the manufacturing process is complicated and the manufacturing cost is very high as compared with a normal bulk Si substrate.
  • an object of the present invention is to provide a semiconductor in which an SSD-MISFET is formed on a semiconductor substrate, which does not require the use of an SOI substrate, has low junction leakage current, and can suppress the short channel effect.
  • An object of the present invention is to provide a device manufacturing method and a semiconductor device formed by such a method.
  • the present invention includes a first conductivity type well region formed on a surface portion of a semiconductor substrate, a gate insulating film formed on the well region, a gate electrode formed on the gate insulating film, and the gate A pair of first-conductivity type low-concentration diffusion regions having an impurity concentration lower than the impurity concentration of the well region, and a surface portion of the pair of low-concentration diffusion regions formed on the surface portion of the well region across the electrode
  • a semiconductor device comprising a source electrode and a drain electrode, each of which is formed of a metal or a compound of a metal and a semiconductor and forms a Schottky junction with the semiconductor substrate.
  • the present invention further includes introducing a impurity into a surface portion of a semiconductor substrate to form a well region, forming a gate insulating film and a gate electrode on the surface of the well region, and sandwiching the gate electrode Forming a pair of low-concentration diffusion regions having an impurity concentration lower than that of the well region on a surface portion of the well region; and forming a Schottky junction with the semiconductor substrate on the surface of the pair of low-concentration diffusion regions
  • a method for manufacturing a semiconductor device is provided. The method includes forming a source electrode and a drain electrode.
  • an SSD-MISFET having a small junction leakage current, low power consumption, a short channel effect is suppressed, and a manufacturing cost can be reduced. can get.
  • FIG. 2A to 2E are cross-sectional views sequentially showing the manufacturing method of the first example for manufacturing the semiconductor device of the embodiment step by step.
  • 3A to 3C are cross-sectional views sequentially showing the manufacturing method of the second example for manufacturing the semiconductor device of the embodiment step by step.
  • FIG. 1 is a cross-sectional view of a semiconductor device having an SSD-MISFET according to this embodiment.
  • the semiconductor device shown in FIG. 1 includes a Si substrate (semiconductor substrate) 11, a trench type element isolation region 12 formed on the surface portion of the Si substrate 11, and a well region 20 formed on the surface portion of the Si substrate 11. And have.
  • the SSD-MISFET includes a gate insulating film 13 formed between the element isolation regions 12 on the surface of the well region 20, a gate electrode 14 formed immediately above the gate insulating film 13, and the gate electrode 14 and the gate insulating film 13.
  • An interlayer insulating film 17 is formed so as to cover the gate electrode 14 and the side wall film 15, and a wiring / contact 18 is connected to the source electrode 16a and the drain electrode 16b.
  • the low concentration region 19 is different from the conventional SSD-MISFET semiconductor device.
  • the low concentration region 19 is a semiconductor having the same conductivity type as the well region 20, and the net impurity concentration is lower in the low concentration region 19 than in the well region 20.
  • the depletion layer of the Schottky junction extending to the bottoms of the source and drain electrodes 16a and 16b becomes longer by providing the low-concentration region 19 as compared with the case where it is not provided. For this reason, the electric field inside the depletion layer is weakened, and the junction leakage current can be reduced for the following reason.
  • the junction leakage current of the SSD-MISFET is a reverse current that flows through the Schottky junction.
  • the reverse current JR is theoretically expressed as a depletion layer internal electric field E, Richardson coefficient A ** , Schottky barrier height ⁇ B0 , semiconductor dielectric constant ⁇ s , elementary charge q, Boltzmann coefficient k, and
  • the absolute temperature T is expressed by the following formula.
  • the semiconductor substrate was assumed to be p-type and the impurity distribution was assumed to be uniform.
  • the depletion layer internal electric field E, the impurity concentration N in the semiconductor substrate at the contact surface, the diffusion potential V B in the semiconductor substrate, and a reverse voltage V R applied to the junction the formula:
  • the diffusion potential V B is expressed by the following equation depending on the Schottky barrier ⁇ B0 , the semiconductor band gap E G , the intrinsic carrier concentration n i of the semiconductor, and the impurity concentration N.
  • Equation (1) by reducing the impurity concentration N in the semiconductor at the contact surface, the diffusion potential V B is reduced from equation (3), and the internal electric field is derived from equation (2). E decreases, and the junction leakage current decreases from Equation (1).
  • the semiconductor device according to the above embodiment can be applied to a semiconductor device having MISFETs of both N-type MISFET and P-type MISFET.
  • the N type and the P type are separately formed by the structure described in the background art, for example.
  • an impurity to be introduced into the semiconductor substrate 11 (well region 20) in the case of an N-type MISFET, an acceptor-type impurity such as B, Al, In, or Ga is introduced, and in the case of a P-type MISFET. May be activated by introducing a donor-type impurity such as P, As, or Sb.
  • the gate electrode 14 may be manufactured so that the work function is optimal for each conductivity type.
  • the gate electrode 14 has a gate length on the gate insulating film 13 of a predetermined length or less, and the effect of the present invention is particularly great for a structure having a gate length of 300 nm or less.
  • it is suitable for a fine MISFET in which an impurity having a high concentration of 5 ⁇ 10 16 cm ⁇ 3 or more is introduced into the well region 20.
  • the upper limit of the impurity in the well region 20 is not limited, but in general, if the impurity is too high, the mobility of minority carriers is significantly deteriorated, so that it is preferably 5 ⁇ 10 19 cm ⁇ 3 or less.
  • the present invention is not limited to the gate length and the impurity concentration of the well region, and can be applied to any structure.
  • the source electrode 16a and the drain electrode 16b are made of a metal that forms a Schottky contact with the semiconductor substrate or a compound of a metal and a semiconductor.
  • a metal that forms a Schottky contact with the semiconductor substrate or a compound of a metal and a semiconductor.
  • Er silicide or Yb silicide is preferable for the N-type MISFET.
  • Pt silicide and Ir silicide are preferable for the P-type MISFET.
  • Pb silicide, Ni silicide, Co silicide, Ti silicide, and W silicide are also applicable.
  • a material obtained by mixing a metal such as Au, Ag, Al, or Ru into the above-described silicide material may be used.
  • the impurity concentration in the well region 20 and in the channel region inside the well region 20, particularly below the gate insulating film In order to reduce the junction leakage current in the Schottky junction of the source and drain electrodes, the impurity concentration of the low concentration region 19 at the bottom of the source and drain electrodes is lowered. Further, the short channel effect is suppressed by setting the impurity concentration of the other well regions 20 sufficiently high. Furthermore, in order to strengthen the suppression of the short channel effect, it is possible to partially increase the impurity concentration of the channel region.
  • the low concentration region 19 is formed so that the bottom thereof is in contact with the well region 20 below the source electrode 16a and the drain electrode 16b.
  • the boundary in the depth direction of the low-concentration region 19 is desirably a position that does not exceed the bottom of the element isolation region 12 even in the deepest case in order to maintain insulation with other semiconductor elements.
  • a bulk substrate having a low substrate manufacturing cost is used as a semiconductor substrate, not an SOI substrate or an SGOI (SiGe-on-Insulator) substrate.
  • it may be an SOI substrate or an SGOI substrate.
  • the effect of the present invention is remarkable by providing the low concentration region 19. Is obtained.
  • the semiconductor substrate which is the low concentration region 19 is etched once in a self-aligned manner after the impurities are introduced into the well region 20. Thereafter, a method of crystal growth of Si using an epitaxial growth technique is used.
  • a well region 20 is formed by introducing a first conductivity type impurity at a depth of 500 nm from the surface of the Si substrate 11 by using an ion implantation technique and performing a heat treatment for activating the impurity. .
  • This state is shown in FIG.
  • the impurity distribution in the well region 20 is substantially uniform, and the impurity concentration is 5 ⁇ 10 17 cm ⁇ 3 on average.
  • a gate insulating film 13 is formed.
  • a silicon oxide film, a silicon oxynitride film, or a high-k film can be used.
  • an example using a silicon oxide film will be described.
  • the silicon oxide film is formed using a thermal oxidation method and has a thickness of 10 nm or less, for example, 3 nm.
  • a gate electrode 14 is formed on the gate insulating film 13.
  • the material of the gate electrode 14 polycrystalline silicon or a metal material can be used. An example using polycrystalline silicon will be described.
  • LPCVD low pressure chemical vapor deposition
  • a protective film 21 of a silicon oxide film is formed using LPCVD. This film is necessary for forming the low concentration region 19 described later.
  • the thickness of the protective film 21 is 15 nm.
  • the pattern of the gate electrode is transferred to the resist film using a photolithography technique, and the protective film 21 and the polycrystalline silicon film are etched using a dry etching technique.
  • the gate electrode 14 is formed through the above steps.
  • the gate length is 50 nm.
  • an impurity of the first conductivity type is implanted using an ion implantation technique, and a heat treatment for impurity activation is performed.
  • This implantation is called so-called pocket implantation, and the effective impurity concentration of the channel region becomes, for example, 5 ⁇ 10 18 cm ⁇ 3 by this implantation.
  • a sidewall film 15 is formed on the side surface of the gate electrode 14.
  • the sidewall film 15 is formed by performing highly anisotropic dry etching after forming a 15 nm silicon oxide film, for example, by LPCVD.
  • the silicon substrate is etched from the surface to a depth of, for example, 150 nm using a dry etching growth technique.
  • a condition that the etching rate of the silicon substrate is sufficiently higher than the etching rate of the silicon oxide film (protective film 21) is used so that the gate electrode 14 is not etched.
  • a silicon crystal is grown on the etched Si substrate 11 using an epitaxial growth technique to form a low concentration region 19. Since crystal growth is sensitive to the surface state, it is preferable to perform acid cleaning, APM cleaning, or DHF cleaning immediately before this step. By this cleaning, the sidewall film 15 and the protective film 21 are etched to a thickness of about 10 nm.
  • a crystal growth condition a condition for growing an intrinsic silicon crystal or a condition for introducing an impurity may be used. At this time, a condition is adopted in which the impurity concentration is lower than that of the well region 20.
  • the height of the upper surface of the crystal-grown silicon crystal is preferably substantially the same as the height of the lower surface of the gate insulating film 13.
  • the protective film 21 is removed if necessary.
  • DHF cleaning is performed.
  • the side wall film 15 is also completely removed, but it is necessary to maintain insulation with respect to the gate electrode 14 in the formation of a source electrode 16a and a drain electrode 16b described later. For this reason, the sidewall film 15 is formed again by using the same method as described above. At this time, the thickness of the sidewall film 15 is, for example, 10 nm.
  • a pretreatment for forming the source electrode 16a and the drain electrode 16b cleaning such as DHF cleaning is performed to clean and expose the surface of the Si substrate.
  • cleaning such as DHF cleaning is performed to clean and expose the surface of the Si substrate.
  • the sidewall film 15 is not completely removed.
  • the thickness of the sidewall film 15 after this pretreatment is, for example, 5 nm.
  • a physical vapor deposition (PVD) method is used to deposit a metal film that will later become a source electrode and a drain electrode to a thickness of 10 nm.
  • PVD physical vapor deposition
  • Er is used for the N-type MISFET and Pt is used for the P-type MISFET.
  • a TiN film may be further sputtered by about 10 nm continuously while maintaining a high degree of vacuum.
  • the material of the metal film one or more metals selected from the group of Er, Yb, Pt, Ir, Pb, Ni, Co, Ti, and W can be used.
  • a heat treatment for causing a silicidation reaction is performed, and a metal film and silicon react to form a silicide film of approximately 20 nm.
  • the heat treatment for the silicidation reaction is preferably performed at a temperature of 150 ° C. or higher and 700 ° C. or lower. In this embodiment, this heat treatment is performed for 5 minutes at a substrate temperature of 500 ° C., for example, in a nitrogen atmosphere. Thereafter, the unreacted surplus metal is removed by acid cleaning, whereby the source electrode 16a and the drain electrode 16b are formed.
  • acid cleaning for example, aqua regia is used for Pt and nitric acid is used for erbium.
  • the upper portion of the gate electrode may be silicided at the same time. Since the silicide films of the source electrode 16a and the drain electrode 16b are grown under the sidewall film 15, the source and drain electrodes reach a part below the gate electrode. This state is preferable from the viewpoint of reducing parasitic resistance.
  • a silicon oxide film is formed at a low temperature of 450 ° C. or lower by using a plasma CVD method or an atmospheric pressure CVD method to form an interlayer insulating film 17.
  • the contact hole pattern is transferred to the resist film using a photolithography technique, and the interlayer insulating film 17 is etched using a dry etching technique to form a contact hole.
  • the resist film is peeled off, and a TiN / Al film, for example, is sequentially deposited on the interlayer insulating film 17 and in the contact hole by the PVD method.
  • a TiN / Al film for example, is sequentially deposited on the interlayer insulating film 17 and in the contact hole by the PVD method.
  • the wiring pattern is patterned into a resist film, and the deposited TiN / Al film is dry-etched to form the wiring / contact 18.
  • the manufacturing method of the first embodiment realizes a high-performance SSD-MISFET with low cost, low power consumption, excellent short channel characteristics. Further, in the manufacturing method of the first embodiment, by using the epitaxial growth technique, the low concentration region 19 is provided at the bottom of the source and drain electrodes forming the Schottky barrier with respect to the substrate, so that the electric field inside the Schottky junction can be increased. Relaxing and achieving a reduction in junction leakage current even in a fine MISFET structure. At the same time, the impurity concentration of the well region 20 and the channel region is increased, and the short channel effect can be suppressed.
  • the above-mentioned effect was confirmed, and in particular, when the gate length is 50 nm which is 300 nm or less, the influence of the short channel effect is significantly reduced. The effect was obtained. Note that the gate length is not limited to 300 nm or less.
  • the manufacturing method of the second embodiment differs from the manufacturing method of the first embodiment in that an ion implantation technique is used to form the low concentration region 19. Specifically, in order to reduce the net impurity concentration while maintaining the low concentration region 19 in the first conductivity type, a method of introducing the second conductivity type impurity within a range not exceeding the impurity concentration before ion implantation. Is used.
  • the other manufacturing steps have many parts in common with the first embodiment, and the different process parts will be mainly described below.
  • FIG. 3A the steps from forming the element isolation region 12 on the surface portion of the Si substrate 11 to the step of forming the sidewall film 15 are performed in the same steps as in the first embodiment.
  • the second embodiment it is not necessary to form the protective film 21 on the gate electrode, and the process of forming the protective film 21 and the process of etching the protective film 21 may not be performed.
  • an impurity of the second conductivity type is implanted into a region having a depth of 150 nm from the surface of the silicon substrate using an ion implantation technique.
  • the impurity concentration of the first conductivity type that is not exceeded the concentration of the first conductivity type existing before the ion implantation is activated, and the impurity is activated by heat treatment to reduce the net impurity concentration.
  • a low concentration region 19 is formed.
  • the wiring / contact 18 is formed from the step of forming the source electrode 16a and the drain electrode 16b on the low concentration region 19 in the same process as in the first embodiment. Perform up to the process.
  • a low-cost, low power consumption, excellent short channel characteristic and high-performance SSD-MISFET can be manufactured.
  • an ion implantation technique is used to provide the low concentration region 19 at the bottom of the source and drain electrodes forming a Schottky barrier with respect to the substrate.
  • the electric field inside the Schottky junction is relaxed, and the junction leakage current is reduced even in a fine MISFET structure.
  • the impurity concentration of the well region 20 and the channel region is increased, and the short channel effect can be suppressed.
  • the above-mentioned effect was confirmed.
  • the gate length is 50 nm which is 300 nm or less, the influence of the short channel effect is significantly reduced. The effect was obtained. Also in this embodiment, the gate length is not limited to 300 nm or less.

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Abstract

L'invention porte sur un dispositif à semi-conducteur comportant une région de puits d'un premier type de conductivité, qui est formée dans la partie de surface d'un substrat semi-conducteur, un film isolant de grille formé sur la région de puits, une électrode de grille formée sur le film isolant de grille, une paire de régions de diffusion à faible concentration du premier type de conductivité, qui sont respectivement formées dans des parties de surface de la région de puits prenant en sandwich l'électrode de grille et qui présentent une concentration en impureté inférieure à celle de la région de puits, et une électrode de source et une électrode de drain respectivement formées dans les parties de surface des régions de diffusion à faible concentration et composées d'un métal ou d'un composé d'un métal et d'un semi-conducteur. L'électrode de source et l'électrode de drain forment une jonction Schottky avec le substrat semi-conducteur.
PCT/JP2009/050417 2008-01-16 2009-01-15 Dispositif à semi-conducteur et son procédé de fabrication WO2009090974A1 (fr)

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JPH10116983A (ja) * 1996-10-11 1998-05-06 Sanyo Electric Co Ltd 半導体装置とその製造方法
JPH1168096A (ja) * 1997-08-12 1999-03-09 Nec Corp 半導体装置及びその製造方法
JPH11289089A (ja) * 1998-02-06 1999-10-19 Toshiba Corp 半導体装置及びその製造方法
JP2000133819A (ja) * 1998-10-27 2000-05-12 Fuji Electric Co Ltd 炭化けい素ショットキーバリアダイオードおよびその製造方法
JP2000299462A (ja) * 1999-04-15 2000-10-24 Toshiba Corp 半導体装置及びその製造方法
JP2001068689A (ja) * 1999-08-26 2001-03-16 Fuji Electric Co Ltd ショットキーバリアダイオードの製造方法
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JP2004039982A (ja) * 2002-07-05 2004-02-05 Mitsubishi Electric Corp 半導体装置
JP2006100403A (ja) * 2004-09-28 2006-04-13 Fujitsu Ltd 電界効果型トランジスタおよびその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09102619A (ja) * 1995-07-21 1997-04-15 Deutsche Itt Ind Gmbh 半導体装置
JPH10116983A (ja) * 1996-10-11 1998-05-06 Sanyo Electric Co Ltd 半導体装置とその製造方法
JPH1168096A (ja) * 1997-08-12 1999-03-09 Nec Corp 半導体装置及びその製造方法
JPH11289089A (ja) * 1998-02-06 1999-10-19 Toshiba Corp 半導体装置及びその製造方法
JP2000133819A (ja) * 1998-10-27 2000-05-12 Fuji Electric Co Ltd 炭化けい素ショットキーバリアダイオードおよびその製造方法
JP2000299462A (ja) * 1999-04-15 2000-10-24 Toshiba Corp 半導体装置及びその製造方法
JP2001068689A (ja) * 1999-08-26 2001-03-16 Fuji Electric Co Ltd ショットキーバリアダイオードの製造方法
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JP2004039982A (ja) * 2002-07-05 2004-02-05 Mitsubishi Electric Corp 半導体装置
JP2006100403A (ja) * 2004-09-28 2006-04-13 Fujitsu Ltd 電界効果型トランジスタおよびその製造方法

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Title
WANG C. ET AL.: "Sub-40nm PtSi Schottky source/ drain metal-oxide-semiconductor field-effect transistors", APPLIED PHYSICS LETTERS, vol. 74, no. 8, 22 February 1999 (1999-02-22), pages 1174 - 1176 *

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