WO2009047840A1 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

Info

Publication number
WO2009047840A1
WO2009047840A1 PCT/JP2007/069705 JP2007069705W WO2009047840A1 WO 2009047840 A1 WO2009047840 A1 WO 2009047840A1 JP 2007069705 W JP2007069705 W JP 2007069705W WO 2009047840 A1 WO2009047840 A1 WO 2009047840A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
logical circuits
units
Prior art date
Application number
PCT/JP2007/069705
Other languages
English (en)
French (fr)
Inventor
Yasuhide Sosogi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to CN200780100951A priority Critical patent/CN101816067A/zh
Priority to AT07829443T priority patent/ATE541310T1/de
Priority to EP07829443A priority patent/EP2200078B1/en
Priority to PCT/JP2007/069705 priority patent/WO2009047840A1/ja
Priority to KR1020107007012A priority patent/KR101379519B1/ko
Priority to JP2009536881A priority patent/JP5201148B2/ja
Publication of WO2009047840A1 publication Critical patent/WO2009047840A1/ja
Priority to US12/659,462 priority patent/US8674501B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1206—Location of test circuitry on chip or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

　各々が論理回路の集合からなる単位を複数含む半導体集積回路装置であって、論理回路の集合からなる単位の各々は互いに共通する実装設計のパターンを有し、又当該半導体集積回路装置に対し外部から電源を供給するための電源端子間の間隔の偶数倍のサイズを有する。
PCT/JP2007/069705 2007-10-09 2007-10-09 半導体集積回路装置 WO2009047840A1 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN200780100951A CN101816067A (zh) 2007-10-09 2007-10-09 半导体集成电路装置
AT07829443T ATE541310T1 (de) 2007-10-09 2007-10-09 Integriertes halbleiterschaltungsbauelement
EP07829443A EP2200078B1 (en) 2007-10-09 2007-10-09 Semiconductor integrated circuit device
PCT/JP2007/069705 WO2009047840A1 (ja) 2007-10-09 2007-10-09 半導体集積回路装置
KR1020107007012A KR101379519B1 (ko) 2007-10-09 2007-10-09 반도체 집적 회로 장치
JP2009536881A JP5201148B2 (ja) 2007-10-09 2007-10-09 半導体集積回路装置
US12/659,462 US8674501B2 (en) 2007-10-09 2010-03-09 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/069705 WO2009047840A1 (ja) 2007-10-09 2007-10-09 半導体集積回路装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/659,462 Continuation US8674501B2 (en) 2007-10-09 2010-03-09 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
WO2009047840A1 true WO2009047840A1 (ja) 2009-04-16

Family

ID=40548995

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/069705 WO2009047840A1 (ja) 2007-10-09 2007-10-09 半導体集積回路装置

Country Status (7)

Country Link
US (1) US8674501B2 (ja)
EP (1) EP2200078B1 (ja)
JP (1) JP5201148B2 (ja)
KR (1) KR101379519B1 (ja)
CN (1) CN101816067A (ja)
AT (1) ATE541310T1 (ja)
WO (1) WO2009047840A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102333446B1 (ko) 2015-11-09 2021-11-30 삼성전자주식회사 반도체 장치 및 반도체 시스템

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722510A (ja) * 1993-07-01 1995-01-24 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置
JPH11250700A (ja) 1998-02-27 1999-09-17 Toshiba Corp メモリ混載半導体集積回路
JP2002170826A (ja) * 2000-11-30 2002-06-14 Hitachi Ltd 半導体装置およびその製造方法
JP2003264256A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 半導体装置
US20060267706A1 (en) 2005-05-25 2006-11-30 Satoru Takase System and method for configuring conductors within an integrated circuit to reduce impedance variation caused by connection bumps

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2976357B2 (ja) * 1991-08-20 1999-11-10 富士通株式会社 半導体集積回路装置
JPH0964191A (ja) * 1995-06-15 1997-03-07 Hitachi Ltd 半導体集積回路装置
JP3177464B2 (ja) * 1996-12-12 2001-06-18 株式会社日立製作所 入出力回路セル及び半導体集積回路装置
JP3535804B2 (ja) * 2000-04-28 2004-06-07 Ｎｅｃマイクロシステム株式会社 フリップチップ型半導体装置の設計方法
US7424696B2 (en) * 2004-12-03 2008-09-09 Lsi Corporation Power mesh for multiple frequency operation of semiconductor products
WO2007099579A1 (ja) * 2006-02-28 2007-09-07 Fujitsu Limited Ｒａｍマクロ、そのタイミング生成回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722510A (ja) * 1993-07-01 1995-01-24 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置
JPH11250700A (ja) 1998-02-27 1999-09-17 Toshiba Corp メモリ混載半導体集積回路
JP2002170826A (ja) * 2000-11-30 2002-06-14 Hitachi Ltd 半導体装置およびその製造方法
JP2003264256A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 半導体装置
US20060267706A1 (en) 2005-05-25 2006-11-30 Satoru Takase System and method for configuring conductors within an integrated circuit to reduce impedance variation caused by connection bumps

Also Published As

Publication number Publication date
CN101816067A (zh) 2010-08-25
JPWO2009047840A1 (ja) 2011-02-17
JP5201148B2 (ja) 2013-06-05
KR20100063762A (ko) 2010-06-11
KR101379519B1 (ko) 2014-03-28
EP2200078A1 (en) 2010-06-23
US20100164099A1 (en) 2010-07-01
EP2200078B1 (en) 2012-01-11
US8674501B2 (en) 2014-03-18
ATE541310T1 (de) 2012-01-15
EP2200078A4 (en) 2010-11-10

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