WO2009034881A1 - 位相比較器およびフェーズロックドループ - Google Patents

位相比較器およびフェーズロックドループ Download PDF

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Publication number
WO2009034881A1
WO2009034881A1 PCT/JP2008/065754 JP2008065754W WO2009034881A1 WO 2009034881 A1 WO2009034881 A1 WO 2009034881A1 JP 2008065754 W JP2008065754 W JP 2008065754W WO 2009034881 A1 WO2009034881 A1 WO 2009034881A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
vco
input terminal
signal supplied
locked loop
Prior art date
Application number
PCT/JP2008/065754
Other languages
English (en)
French (fr)
Inventor
Tadashi Maeda
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/676,221 priority Critical patent/US8248104B2/en
Priority to JP2009532147A priority patent/JP5206682B2/ja
Publication of WO2009034881A1 publication Critical patent/WO2009034881A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

　高い精度でＶＣＯの制御を行うことができないという問題を解決する位相比較器を提供する。 　分周部は、入力端子１０に入力されたＶＣＯ信号を段階的に分周し、各段階のＶＣＯ信号のそれぞれを出力する。ラッチ部は、入力端子１０に入力されたＶＣＯ信号と、分周部から出力された各ＶＣＯ信号を、入力端子１１に入力された基準信号に基づいてラッチする。出力部は、ラッチ部によるラッチ結果を、基準信号およびＶＣＯ信号の位相差を示す位相差信号として出力する。
PCT/JP2008/065754 2007-09-14 2008-09-02 位相比較器およびフェーズロックドループ WO2009034881A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/676,221 US8248104B2 (en) 2007-09-14 2008-09-02 Phase comparator and phase-locked loop
JP2009532147A JP5206682B2 (ja) 2007-09-14 2008-09-02 位相比較器およびフェーズロックドループ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007238621 2007-09-14
JP2007-238621 2007-09-14

Publications (1)

Publication Number Publication Date
WO2009034881A1 true WO2009034881A1 (ja) 2009-03-19

Family

ID=40451890

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/065754 WO2009034881A1 (ja) 2007-09-14 2008-09-02 位相比較器およびフェーズロックドループ

Country Status (3)

Country Link
US (1) US8248104B2 (ja)
JP (1) JP5206682B2 (ja)
WO (1) WO2009034881A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010143241A1 (ja) * 2009-06-10 2010-12-16 パナソニック株式会社 デジタルｐｌｌ回路、半導体集積回路、表示装置
JP2012060431A (ja) * 2010-09-09 2012-03-22 Toshiba Corp 時間計測回路およびデジタル位相同期回路

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8736323B2 (en) * 2007-01-11 2014-05-27 International Business Machines Corporation Method and apparatus for on-chip phase error measurement to determine jitter in phase-locked loops
JP5028524B2 (ja) * 2008-04-11 2012-09-19 株式会社アドバンテスト ループ型クロック調整回路および試験装置
US8638896B2 (en) * 2010-03-19 2014-01-28 Netlogic Microsystems, Inc. Repeate architecture with single clock multiplier unit
US20120033772A1 (en) * 2010-08-08 2012-02-09 Freescale Semiconductor, Inc Synchroniser circuit and method
US9130575B2 (en) 2013-03-14 2015-09-08 Samsung Electronics Co., Ltd. Communication system with charge pump mechanism and method of operation thereof
US10868547B2 (en) * 2018-09-25 2020-12-15 Stmicroelectronics (Grenoble 2) Sas Device for determining a propagation time
US10965442B2 (en) * 2018-10-02 2021-03-30 Qualcomm Incorporated Low-power, low-latency time-to-digital-converter-based serial link

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076886A (ja) * 2000-06-30 2002-03-15 Texas Instruments Inc デジタル小位相検出器
JP2007110370A (ja) * 2005-10-13 2007-04-26 Fujitsu Ltd デジタル位相検出器

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JP2816038B2 (ja) 1991-10-28 1998-10-27 三洋電機株式会社 Ｐｌｌ周波数シンセサイザ回路
JP3302513B2 (ja) 1994-08-22 2002-07-15 沖電気工業株式会社 位相同期回路の異常検出方式
JPH08213900A (ja) 1995-02-07 1996-08-20 Oki Electric Ind Co Ltd 位相比較回路とそれを用いたｐｌｌ回路
CA2201695C (en) * 1997-04-03 2004-08-10 Gennum Corporation Phase detector for high speed clock recovery from random binary signals
US6606004B2 (en) * 2000-04-20 2003-08-12 Texas Instruments Incorporated System and method for time dithering a digitally-controlled oscillator tuning input
US6580376B2 (en) * 2000-07-10 2003-06-17 Silicon Laboratories, Inc. Apparatus and method for decimating a digital input signal
US6868504B1 (en) 2000-08-31 2005-03-15 Micron Technology, Inc. Interleaved delay line for phase locked and delay locked loops
JP3630092B2 (ja) 2000-10-19 2005-03-16 日本電気株式会社 位相周波数比較回路
JP3674850B2 (ja) 2001-12-11 2005-07-27 ソニー株式会社 電圧制御発振器の自走周波数の自動調整機能を有する位相ロックループ回路
JP2004180125A (ja) 2002-11-28 2004-06-24 Renesas Technology Corp 半導体装置
JP2005020221A (ja) 2003-06-25 2005-01-20 Matsushita Electric Ind Co Ltd Ｐｌｌ回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076886A (ja) * 2000-06-30 2002-03-15 Texas Instruments Inc デジタル小位相検出器
JP2007110370A (ja) * 2005-10-13 2007-04-26 Fujitsu Ltd デジタル位相検出器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010143241A1 (ja) * 2009-06-10 2010-12-16 パナソニック株式会社 デジタルｐｌｌ回路、半導体集積回路、表示装置
US8648632B2 (en) 2009-06-10 2014-02-11 Panasonic Corporation Digital PLL circuit, semiconductor integrated circuit, and display apparatus
JP2012060431A (ja) * 2010-09-09 2012-03-22 Toshiba Corp 時間計測回路およびデジタル位相同期回路
US8446302B2 (en) 2010-09-09 2013-05-21 Kabushiki Kaisha Toshiba Time to digital converter and all digital phase-locked-loop

Also Published As

Publication number Publication date
US8248104B2 (en) 2012-08-21
US20100171527A1 (en) 2010-07-08
JP5206682B2 (ja) 2013-06-12
JPWO2009034881A1 (ja) 2010-12-24

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