WO2009034653A1 - 回路、その制御方法、処理装置及び処理装置の制御方法 - Google Patents

回路、その制御方法、処理装置及び処理装置の制御方法 Download PDF

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Publication number
WO2009034653A1
WO2009034653A1 PCT/JP2007/067988 JP2007067988W WO2009034653A1 WO 2009034653 A1 WO2009034653 A1 WO 2009034653A1 JP 2007067988 W JP2007067988 W JP 2007067988W WO 2009034653 A1 WO2009034653 A1 WO 2009034653A1
Authority
WO
WIPO (PCT)
Prior art keywords
processing device
circuit
bus
prevented
slave device
Prior art date
Application number
PCT/JP2007/067988
Other languages
English (en)
French (fr)
Inventor
Atsushi Uchida
Hirotoshi Inoue
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009532032A priority Critical patent/JP5035349B2/ja
Priority to PCT/JP2007/067988 priority patent/WO2009034653A1/ja
Publication of WO2009034653A1 publication Critical patent/WO2009034653A1/ja
Priority to US12/719,944 priority patent/US8203361B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

　回路において、マスタ装置からスレーブ装置に双方向バス制御信号を二重化して出力し、さらに、双方向バス制御信号が一致しなかった場合、マスタ装置をデータの送信側、スレーブ装置をデータの受信側に制御する。そのため、バス上にて出力が衝突してしまうことやバスが中間電位状態となってしまうことを防ぐことができる。また、少なくともスレーブ装置を受信側とすることができ、バスファイトが発生してしまうことは防ぐことができる。
PCT/JP2007/067988 2007-09-14 2007-09-14 回路、その制御方法、処理装置及び処理装置の制御方法 WO2009034653A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009532032A JP5035349B2 (ja) 2007-09-14 2007-09-14 回路、その制御方法
PCT/JP2007/067988 WO2009034653A1 (ja) 2007-09-14 2007-09-14 回路、その制御方法、処理装置及び処理装置の制御方法
US12/719,944 US8203361B2 (en) 2007-09-14 2010-03-09 Circuit system including first circuit sub-system, second circuit sub-system and bidirectional bus, circuit sub-system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/067988 WO2009034653A1 (ja) 2007-09-14 2007-09-14 回路、その制御方法、処理装置及び処理装置の制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/719,944 Continuation US8203361B2 (en) 2007-09-14 2010-03-09 Circuit system including first circuit sub-system, second circuit sub-system and bidirectional bus, circuit sub-system and method

Publications (1)

Publication Number Publication Date
WO2009034653A1 true WO2009034653A1 (ja) 2009-03-19

Family

ID=40451677

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/067988 WO2009034653A1 (ja) 2007-09-14 2007-09-14 回路、その制御方法、処理装置及び処理装置の制御方法

Country Status (3)

Country Link
US (1) US8203361B2 (ja)
JP (1) JP5035349B2 (ja)
WO (1) WO2009034653A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100020220A (ko) * 2008-08-12 2010-02-22 한국전자통신연구원 메모리 공유 제어장치 및 메모리 공유 제어방법, 그리고 공유 메모리 접근방법
CN102483697B (zh) * 2009-07-21 2015-06-10 中村维男 无存储器瓶颈的低能耗高速计算机
US9520878B1 (en) * 2014-10-30 2016-12-13 Altera Corporation Methods and apparatus for transmitting a signal in a single direction using bidirectional driver circuits
KR102599277B1 (ko) * 2018-12-13 2023-11-07 엘지디스플레이 주식회사 터치 센서 디스플레이 장치 및 인터페이스 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5824925A (ja) * 1981-08-06 1983-02-15 Fujitsu Ltd 双方向性バスの制御方式
JPH0863431A (ja) * 1994-08-19 1996-03-08 Fujitsu Ltd バスファイト防止装置
JPH0954752A (ja) * 1995-08-16 1997-02-25 Nec Eng Ltd 双方向バスの制御方式

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123598A (ja) * 1985-11-25 1987-06-04 松下電工株式会社 伝送方式
JPH02194748A (ja) * 1989-01-24 1990-08-01 Nec Corp データ通信方式
JPH10340101A (ja) * 1997-06-09 1998-12-22 East Japan Railway Co フェールセーフ出力装置
JP3815702B2 (ja) * 1997-06-17 2006-08-30 Ｎｅｃインフロンティア株式会社 伝送路延長方式
JP2000250770A (ja) * 1999-03-02 2000-09-14 Babcock Hitachi Kk 多重化計装システム
US6639423B2 (en) * 2002-03-12 2003-10-28 Intel Corporation Current mode driver with variable termination
JP5008058B2 (ja) * 2006-06-22 2012-08-22 ルネサスエレクトロニクス株式会社 出力インピーダンス調整回路、半導体装置及び出力インピーダンス調整方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5824925A (ja) * 1981-08-06 1983-02-15 Fujitsu Ltd 双方向性バスの制御方式
JPH0863431A (ja) * 1994-08-19 1996-03-08 Fujitsu Ltd バスファイト防止装置
JPH0954752A (ja) * 1995-08-16 1997-02-25 Nec Eng Ltd 双方向バスの制御方式

Also Published As

Publication number Publication date
US8203361B2 (en) 2012-06-19
JPWO2009034653A1 (ja) 2010-12-16
US20100164546A1 (en) 2010-07-01
JP5035349B2 (ja) 2012-09-26

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