WO2009028399A1 - Semiconductor wafer and method for manufacturing the same - Google Patents

Semiconductor wafer and method for manufacturing the same Download PDF

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Publication number
WO2009028399A1
WO2009028399A1 PCT/JP2008/064945 JP2008064945W WO2009028399A1 WO 2009028399 A1 WO2009028399 A1 WO 2009028399A1 JP 2008064945 W JP2008064945 W JP 2008064945W WO 2009028399 A1 WO2009028399 A1 WO 2009028399A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon wafer
small silicon
wafer pieces
diameter
manufacturing
Prior art date
Application number
PCT/JP2008/064945
Other languages
French (fr)
Japanese (ja)
Inventor
Kazushige Takaishi
Seiji Sugimoto
Original Assignee
Sumco Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corporation filed Critical Sumco Corporation
Priority to JP2009530076A priority Critical patent/JP5294087B2/en
Publication of WO2009028399A1 publication Critical patent/WO2009028399A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A large diameter wafer having a diameter of 450mm or more is manufactured at high yield and low cost. On a circular quartz glass substrate having a diameter of 450mm or more to be a base material substrate, a plurality of rectangular small silicon wafer pieces are bonded by annealing or the like. After bonding, gaps between the small silicon wafer pieces are filled with polysilicon by depositing the polysilicon by CVD. Furthermore, the surfaces of the small silicon wafer pieces are polished to be a device forming surface. Alternately, a device surface is formed by forming an epitaxial layer on the surfaces of the small silicon wafer pieces.
PCT/JP2008/064945 2007-08-24 2008-08-21 Semiconductor wafer and method for manufacturing the same WO2009028399A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009530076A JP5294087B2 (en) 2007-08-24 2008-08-21 Semiconductor wafer and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-218956 2007-08-24
JP2007218956 2007-08-24

Publications (1)

Publication Number Publication Date
WO2009028399A1 true WO2009028399A1 (en) 2009-03-05

Family

ID=40387121

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/064945 WO2009028399A1 (en) 2007-08-24 2008-08-21 Semiconductor wafer and method for manufacturing the same

Country Status (3)

Country Link
JP (1) JP5294087B2 (en)
TW (1) TW200914653A (en)
WO (1) WO2009028399A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012060430A1 (en) * 2010-11-05 2012-05-10 シャープ株式会社 Semiconductor substrate, method for manufacturing semiconductor substrate, thin-film transistor, semiconductor circuit, liquid crystal display device, electroluminescent device, wireless communication device, and light-emitting device
WO2014020906A1 (en) * 2012-07-30 2014-02-06 住友化学株式会社 Method for manufacturing composite substrate and method for manufacturing semiconductor crystal layer formation substrate
WO2019017398A1 (en) * 2017-07-19 2019-01-24 株式会社テンシックス Compound-semiconductor substrate and production method therefor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0832038A (en) * 1994-07-15 1996-02-02 Komatsu Electron Metals Co Ltd Manufacture of stuck soi substrate and stuck soi substrate
JP2000082643A (en) * 1999-07-30 2000-03-21 Canon Inc Semiconductor substrate and manufacture thereof
JP2003068592A (en) * 2001-08-22 2003-03-07 Toshiba Corp Method for producing epitaxial substrate, method for fabricating semiconductor element, and epitaxial substrate
JP2003324188A (en) * 2002-04-30 2003-11-14 Ishikawajima Harima Heavy Ind Co Ltd Method for manufacturing large-area single-crystal silicon substrate
WO2006114999A1 (en) * 2005-04-18 2006-11-02 Kyoto University Compound semiconductor device and method for fabricating compound semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0832038A (en) * 1994-07-15 1996-02-02 Komatsu Electron Metals Co Ltd Manufacture of stuck soi substrate and stuck soi substrate
JP2000082643A (en) * 1999-07-30 2000-03-21 Canon Inc Semiconductor substrate and manufacture thereof
JP2003068592A (en) * 2001-08-22 2003-03-07 Toshiba Corp Method for producing epitaxial substrate, method for fabricating semiconductor element, and epitaxial substrate
JP2003324188A (en) * 2002-04-30 2003-11-14 Ishikawajima Harima Heavy Ind Co Ltd Method for manufacturing large-area single-crystal silicon substrate
WO2006114999A1 (en) * 2005-04-18 2006-11-02 Kyoto University Compound semiconductor device and method for fabricating compound semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012060430A1 (en) * 2010-11-05 2012-05-10 シャープ株式会社 Semiconductor substrate, method for manufacturing semiconductor substrate, thin-film transistor, semiconductor circuit, liquid crystal display device, electroluminescent device, wireless communication device, and light-emitting device
WO2014020906A1 (en) * 2012-07-30 2014-02-06 住友化学株式会社 Method for manufacturing composite substrate and method for manufacturing semiconductor crystal layer formation substrate
WO2019017398A1 (en) * 2017-07-19 2019-01-24 株式会社テンシックス Compound-semiconductor substrate and production method therefor
CN110663096A (en) * 2017-07-19 2020-01-07 X-Vi株式会社 Compound semiconductor substrate and method for manufacturing same
CN110663096B (en) * 2017-07-19 2023-06-06 X-Vi株式会社 Compound semiconductor substrate and method for producing same

Also Published As

Publication number Publication date
JPWO2009028399A1 (en) 2010-12-02
JP5294087B2 (en) 2013-09-18
TW200914653A (en) 2009-04-01

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