JPH0832038A - Manufacture of stuck soi substrate and stuck soi substrate - Google Patents

Manufacture of stuck soi substrate and stuck soi substrate

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Publication number
JPH0832038A
JPH0832038A JP18651694A JP18651694A JPH0832038A JP H0832038 A JPH0832038 A JP H0832038A JP 18651694 A JP18651694 A JP 18651694A JP 18651694 A JP18651694 A JP 18651694A JP H0832038 A JPH0832038 A JP H0832038A
Authority
JP
Japan
Prior art keywords
single crystal
crystal silicon
substrate
wafer
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18651694A
Other languages
Japanese (ja)
Inventor
Mitsuo Kono
光雄 河野
Junsuke Tomioka
純輔 冨岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
Original Assignee
Sumco Techxiv Corp
Komatsu Electronic Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Techxiv Corp, Komatsu Electronic Metals Co Ltd filed Critical Sumco Techxiv Corp
Priority to JP18651694A priority Critical patent/JPH0832038A/en
Priority to TW084113188A priority patent/TW330303B/en
Publication of JPH0832038A publication Critical patent/JPH0832038A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To provide a manufacturing method of a stuck SOI substrate having a diameter equal to or larger than the large caliber of a single crystal wafer which can not be manufactured by techniques. CONSTITUTION:Polycrystalline silicon is fused by using a quartz crucible having a large caliber, and a polycrystalline silicon rod is obtained by cooling. The rod is sliced and subjected to mirror polishing, and a retaining substrate 5 is formed. When the crystal orientation of a single crystal silicon rod grown by a CZ method is <111>, the rod is worked into a regular hexagonal pole, sliced, and subjected to mirror polishing, and a single crystal silicon wafer 7 is formed. The wafer 7 is subjected to oxidation treatment, and stuck on the retaining substrate 5 without generating a gap, and an SOI substrate is constituted. The upper surface of the wafer 7 is polished to obtain a specified thickness. Glass, ceramics, etc., may be used as a retaining substrate. By sticking a single crystal silicon wafer 8, which is worked into an equilateral triangle, on the periphery of the single crystal silicon wafer 7, the area of the retaining substrate 5 can be effectively used.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、貼り合わせSOI基板
の製造方法および貼り合わせSOI基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bonded SOI substrate and a bonded SOI substrate.

【0002】[0002]

【従来の技術】バルク状の半導体基板に集積回路を作り
込むよりも、絶縁材料上に設けられた薄い半導体層に各
種の素子を形成するほうが、素子特性や素子間分離の点
で有利である。このような見地から、単結晶シリコン基
板にSiO2 の絶縁膜を介して素子形成のための単結晶
シリコン層を設けたSOI(silicon on i
nsulator)構造が用いられている。前記SOI
構造を得る方法のうち、単結晶シリコンウェーハの貼り
合わせによるものは、高い結晶性のSOI活性層が得ら
れ、活性層の厚さをある程度任意に設定することができ
るとともに、埋め込み酸化膜の厚さを任意に設定するこ
とができるなどの利点を持っている。
2. Description of the Related Art It is advantageous to form various elements in a thin semiconductor layer provided on an insulating material in terms of element characteristics and element isolation, rather than forming an integrated circuit on a bulk semiconductor substrate. . From this point of view, an SOI (silicon on i) structure in which a single crystal silicon layer for forming an element is provided on a single crystal silicon substrate through an insulating film of SiO 2 is provided.
nsulator) structure is used. The SOI
Among the methods for obtaining the structure, the method of sticking a single crystal silicon wafer provides an SOI active layer with high crystallinity, the thickness of the active layer can be set to some extent, and the thickness of the buried oxide film can be set. It has the advantage that it can be set arbitrarily.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、貼り合
わせ技術によって製作されるSOI基板においては、下
記の問題点がある。 (1)貼り合わせSOI基板は、貼り合わせ時に接合界
面に欠陥を生じやすい。前記欠陥の代表的なものとし
て、接合不良領域であるボイドの発生があり、貼り合わ
せるウェーハの直径が大きくなるにつれて良品率が低下
している。 (2)支持基板に単結晶シリコンを用いると、その世代
の技術で製造可能な単結晶の直径によってSOI基板の
直径が制約されるとともに、コスト的にも非常に高価で
ある。また、電子機器製造の最終工程においては、SO
I基板を用いてCPU、メモリなどのチップを個別に製
作した後、これらのチップを所定の位置に配設してシス
テムを構成している。
However, the SOI substrate manufactured by the bonding technique has the following problems. (1) Bonded SOI substrates are likely to have defects at the bonding interface during bonding. A typical defect is the occurrence of voids, which are defective bonding regions, and the non-defective rate decreases as the diameter of a bonded wafer increases. (2) When single crystal silicon is used for the supporting substrate, the diameter of the SOI substrate is restricted by the diameter of the single crystal that can be manufactured by the technology of the generation, and the cost is very high. In the final process of manufacturing electronic equipment, SO
After the chips such as CPU and memory are individually manufactured using the I substrate, these chips are arranged at predetermined positions to form a system.

【0004】本発明は上記従来の問題点に着目してなさ
れたもので、その世代の技術では製造不可能な大口径の
単結晶ウェーハと同等以上の直径を有する貼り合わせS
OI基板の製造方法および貼り合わせSOI基板の提供
と、更には一つの貼り合わせSOI基板に複数種類のデ
バイスを形成することができるようなシステムオンチッ
プ用の貼り合わせSOI基板を提供することを目的とし
ている。
The present invention has been made in view of the above-mentioned conventional problems, and the bonding S having a diameter equal to or larger than that of a large-diameter single crystal wafer which cannot be manufactured by the technology of the generation.
An object is to provide a method for manufacturing an OI substrate and a bonded SOI substrate, and further to provide a bonded SOI substrate for a system-on-chip capable of forming a plurality of types of devices on one bonded SOI substrate. I am trying.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、本発明に係る貼り合わせSOI基板の製造方法は、
鏡面加工ならびに酸化処理を行った特定の形状の無転位
単結晶シリコンウェーハを、鏡面加工を施した大口径の
多結晶シリコン、ガラス、セラミックスまたは金属から
なる支持基板に貼り合わせた後、前記無転位単結晶シリ
コンウェーハを所定の厚さに研磨する構成とし、このよ
うな構成において、前記特定の形状が、正六角形、正四
角形、長方形または正三角形であることを特徴としてい
る。また、前記製造方法による貼り合わせSOI基板
は、その世代の技術では製造不可能な大口径の単結晶シ
リコンウェーハと同等以上の直径を有する多結晶シリコ
ン、ガラス、セラミックスまたは金属からなる支持基板
に、特定の形状に加工した複数個の無転位単結晶シリコ
ンウェーハを酸化膜を介して貼り合わせたもの、あるい
は、前記支持基板に、エレクトロニクス・システムを構
成するために必要な複数種類の無転位単結晶シリコンウ
ェーハをそれぞれ所定の位置に貼り合わせる構成とし
た。
In order to achieve the above object, a method for manufacturing a bonded SOI substrate according to the present invention comprises:
After bonding a dislocation-free single crystal silicon wafer with a specific shape that has been mirror-finished and oxidized to a support substrate made of large-diameter polycrystalline silicon, glass, ceramics, or metal that has been mirror-finished, A single crystal silicon wafer is polished to a predetermined thickness, and in such a configuration, the specific shape is a regular hexagon, a regular square, a rectangle, or a regular triangle. Further, the bonded SOI substrate according to the above-mentioned manufacturing method is a supporting substrate made of polycrystalline silicon, glass, ceramics or metal having a diameter equal to or larger than that of a large-diameter single crystal silicon wafer which cannot be manufactured by the technology of the generation. A plurality of dislocation-free single crystal silicon wafers processed into a specific shape, which are bonded together via an oxide film, or a plurality of dislocation-free single crystals necessary for constructing an electronic system on the supporting substrate. The silicon wafers were each bonded to a predetermined position.

【0006】[0006]

【作用】特定の形状に加工された単結晶シリコンウェー
ハの面積は、大口径の多結晶シリコンウェーハなどから
なる支持基板の面積に対して十分に小さい。上記構成に
よれば、あらかじめ正六角形、正四角形、長方形あるい
は正三角形などに加工して酸化処理を施した単結晶シリ
コンウェーハをSOIウェーハとして用いることにした
ので、大口径の支持基板にこれと同径のSOIウェーハ
を貼り合わせる場合に比べて貼り合わせが容易となり、
ボイドの発生が低減する。また、支持基板に多結晶シリ
コン、ガラス、セラミックスまたは金属を用いることに
より、単結晶シリコンでは得られないような大口径の支
持基板上に前記SOIウェーハを隙間なく貼り合わせる
ことができ、支持基板の面積を有効に利用することがで
きる。更に、大口径の支持基板に複数種類の無転位単結
晶シリコンウェーハをそれぞれ所定の位置に貼り合わせ
ることにより、システムオンチップ用のSOI基板が得
られる。
The area of the single crystal silicon wafer processed into a specific shape is sufficiently smaller than the area of the supporting substrate made of a large-diameter polycrystalline silicon wafer or the like. According to the above configuration, since a single crystal silicon wafer which has been processed into a regular hexagon, a regular square, a rectangle, or a regular triangle and subjected to an oxidation treatment in advance is used as an SOI wafer, the same is applied to a large-diameter support substrate. Bonding is easier than when bonding large diameter SOI wafers,
Generation of voids is reduced. Further, by using polycrystalline silicon, glass, ceramics, or metal for the supporting substrate, the SOI wafer can be bonded to a supporting substrate having a large diameter which cannot be obtained with single crystal silicon without any gaps. The area can be effectively used. Furthermore, a system-on-chip SOI substrate can be obtained by bonding a plurality of types of dislocation-free single crystal silicon wafers to predetermined positions on a large-diameter support substrate.

【0007】[0007]

【実施例】以下に、本発明に係る貼り合わせSOI基板
の製造方法の実施例について、図面を参照して説明す
る。図1は支持基板の製造工程を示す説明図である。ま
ず図1(a)において、大口径たとえば24インチの石
英るつぼ1に多結晶シリコン2を充填し、ヒータ3で溶
解する。これを冷却して石英るつぼ1から取り出すと、
図1(b)に示す24インチの多結晶シリコンロッド4
が得られる。この多結晶シリコンロッド4をスライス
し、鏡面仕上げを施すと、図1(c)に示す24インチ
の支持基板5となる。前記支持基板5の厚さは1mm、
平坦度(TTV)は1μm未満とする。なお、前記多結
晶シリコンロッドの製造方法として、CZ法、ブリッジ
マン法、カイロポーラス法、ペディスタル法を用いても
よい。
EXAMPLES Examples of a method for manufacturing a bonded SOI substrate according to the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory view showing a manufacturing process of a support substrate. First, in FIG. 1A, a quartz crucible 1 having a large diameter such as 24 inches is filled with polycrystalline silicon 2 and melted by a heater 3. When this is cooled and taken out from the quartz crucible 1,
24-inch polycrystalline silicon rod 4 shown in FIG.
Is obtained. When this polycrystalline silicon rod 4 is sliced and mirror-finished, a 24-inch supporting substrate 5 shown in FIG. 1C is obtained. The thickness of the support substrate 5 is 1 mm,
The flatness (TTV) is less than 1 μm. As the method for manufacturing the polycrystalline silicon rod, the CZ method, Bridgman method, cairoporous method, or pedestal method may be used.

【0008】図2はSOIウェーハの製造工程を示す説
明図である。図2(a)はCZ法による単結晶シリコン
の育成で、石英るつぼ1に充填した多結晶シリコンをヒ
ータ3で溶解し、融液に種子結晶を浸漬してたとえば6
インチの単結晶シリコンロッド6を育成する。この単結
晶シリコンロッドを、結晶方位に基づいて正六角柱、正
四角柱などに加工する。図2(b)は結晶方位が〈11
1〉の単結晶シリコンロッド6を正六角柱に加工した状
態を示す。結晶方位が〈100〉のロッドであれば正四
角柱に加工すればよい。このように、単結晶シリコンロ
ッドを特定の形状に加工することにより、オリエンテー
ションフラットまたはノッチの加工は不要となる。この
ロッドをスライスし、鏡面仕上げを施すと、図2(c)
に示すように厚さが500μmで正六角形の単結晶シリ
コンウェーハ7が得られる。このウェーハ7に酸化処理
を施し、厚さ1000Åの酸化膜(SiO2 )を形成さ
せる。
FIG. 2 is an explanatory view showing a manufacturing process of an SOI wafer. FIG. 2 (a) shows the growth of single crystal silicon by the CZ method. The polycrystalline silicon filled in the quartz crucible 1 is melted by the heater 3 and the seed crystal is immersed in the melt to form, for example, 6
An inch single crystal silicon rod 6 is grown. This single crystal silicon rod is processed into a regular hexagonal column, a regular square column or the like based on the crystal orientation. In FIG. 2B, the crystal orientation is <11.
The state which processed the single crystal silicon rod 6 of 1> into the regular hexagonal column is shown. If the rod has a crystal orientation of <100>, it may be processed into a regular square pole. Thus, by processing the single crystal silicon rod into a specific shape, it is not necessary to process the orientation flat or notch. When this rod is sliced and mirror-finished, it is shown in Fig. 2 (c).
A regular hexagonal single crystal silicon wafer 7 having a thickness of 500 μm is obtained as shown in FIG. The wafer 7 is subjected to an oxidation treatment to form an oxide film (SiO 2 ) having a thickness of 1000Å.

【0009】上記単結晶シリコンウェーハを、図3およ
び図4に示すように支持基板5に貼り合わせる。図3は
支持基板5に正六角形の単結晶シリコンウェーハ7を隙
間なく貼り合わせた上、周囲の余った部分に正三角形の
単結晶シリコンウェーハ8を隙間なく貼り合わせた状態
を示している。図4において、7aは単結晶シリコン、
7bは酸化膜である。これを図5に示すように単結晶シ
リコンウェーハ7,8の活性層の厚さが20μmになる
まで研削する。次に、単結晶シリコンウェーハ7,8の
活性層の厚さが1μmになるまで研磨して貼り合わせS
OI基板を完成させた。なお、支持基板5に単結晶シリ
コンウェーハを貼り合わせる際、前記ウェーハ相互の間
に隙間を設けてもよい。また、活性層の厚さを0.1μ
m程度に仕上げる場合は、活性層表面にプラズマエッチ
ングを施す。
The single crystal silicon wafer is attached to a supporting substrate 5 as shown in FIGS. FIG. 3 shows a state in which a regular hexagonal single crystal silicon wafer 7 is bonded to the support substrate 5 without any space, and an equilateral triangular single crystal silicon wafer 8 is bonded to the remaining peripheral part without any space. In FIG. 4, 7a is single crystal silicon,
7b is an oxide film. As shown in FIG. 5, this is ground until the thickness of the active layer of the single crystal silicon wafers 7 and 8 becomes 20 μm. Next, the active layers of the single crystal silicon wafers 7 and 8 are ground to a thickness of 1 μm and bonded S
The OI substrate was completed. When a single crystal silicon wafer is attached to the support substrate 5, a gap may be provided between the wafers. In addition, the thickness of the active layer is 0.1μ.
When finishing to about m, plasma etching is performed on the surface of the active layer.

【0010】図6はシステムオンチップ用SOI基板の
説明図で、支持基板5に酸化膜を介して複数種類の単結
晶シリコンウェーハが貼り合わされている。たとえば、
単結晶シリコンウェーハ9はCPU用として抵抗率1〜
2Ωcmのもの、単結晶シリコンウェーハ10はメモリ
用として抵抗率10〜15Ωcmのものである。これら
のウェーハはいずれもチップサイズに形成されていて、
エレクトロニクス・システムとして最終的に配置される
位置にそれぞれ貼り合わされているので、一対のウェー
ハ11または一群のウェーハによって前記システムが完
成する。このような貼り合わせSOI基板では従来の配
線は一部を除いて不要となる。
FIG. 6 is an explanatory diagram of a system-on-chip SOI substrate, in which a plurality of types of single crystal silicon wafers are bonded to a supporting substrate 5 via an oxide film. For example,
The single crystal silicon wafer 9 has a resistivity of 1 to 1 for CPU.
The resistivity of the single crystal silicon wafer 10 is 2 Ωcm and the resistivity of the single crystal silicon wafer 10 is 10 to 15 Ωcm. All of these wafers are chip-sized,
Since the electronic systems are bonded to the final positions, the system is completed by a pair of wafers 11 or a group of wafers. In such a bonded SOI substrate, conventional wiring is unnecessary except for a part.

【0011】本実施例では支持基板として直径が24イ
ンチの多結晶シリコンウェーハを用いたが、これに限る
ものではなく、たとえば32インチの多結晶シリコンウ
ェーハあるいはガラス板、セラミックス板または金属板
など、その世代において利用可能な大口径のウェーハを
用いることができる。また、酸化処理を施さない単結晶
シリコンウェーハと前記支持基板との貼り合わせに際し
て本発明による製造方法を応用してもよい。
In this embodiment, a polycrystalline silicon wafer having a diameter of 24 inches is used as the supporting substrate, but the supporting substrate is not limited to this, and for example, a polycrystalline silicon wafer having a diameter of 32 inches, a glass plate, a ceramic plate or a metal plate can be used. Large diameter wafers available in that generation can be used. Further, the manufacturing method according to the present invention may be applied when the single crystal silicon wafer not subjected to the oxidation treatment and the supporting substrate are bonded together.

【0012】[0012]

【発明の効果】以上説明したように本発明によれば、貼
り合わせSOI基板の支持基板に多結晶シリコン、ガラ
ス、セラミックスまたは金属を用い、この上に特定の形
状に加工された単結晶シリコンウェーハを複数個貼り合
わせることにしたので、単結晶シリコンを支持基板とし
ていたときには実現不可能な大口径のSOI基板を、高
い良品率で得ることができる。また、前記方法を利用し
てシステムオンチップ用SOI基板を製造することによ
り、エレクトロニクス・システムの生産性向上が可能と
なる。
As described above, according to the present invention, a single crystal silicon wafer is used which is made of polycrystalline silicon, glass, ceramics or metal for a supporting substrate of a bonded SOI substrate and which is processed into a specific shape. Since a plurality of substrates are bonded together, a large-diameter SOI substrate, which cannot be realized when single crystal silicon is used as the supporting substrate, can be obtained with a high yield rate. Further, by manufacturing the system-on-chip SOI substrate using the above method, the productivity of the electronic system can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】支持基板の製造工程を示す説明図である。FIG. 1 is an explanatory diagram showing a manufacturing process of a support substrate.

【図2】SOIウェーハの製造工程を示す説明図であ
る。
FIG. 2 is an explanatory diagram showing a manufacturing process of an SOI wafer.

【図3】支持基板にSOIウェーハを貼り合わせた状態
を示す説明図である。
FIG. 3 is an explanatory diagram showing a state where an SOI wafer is attached to a supporting substrate.

【図4】貼り合わせSOI基板の断面説明図である。FIG. 4 is a cross-sectional explanatory diagram of a bonded SOI substrate.

【図5】SOI基板の活性層を研削した状態を示す説明
図である。
FIG. 5 is an explanatory diagram showing a state in which an active layer of an SOI substrate is ground.

【図6】システムオンチップ用SOI基板の説明図であ
る。
FIG. 6 is an explanatory diagram of a system-on-chip SOI substrate.

【符号の説明】[Explanation of symbols]

4 多結晶シリコンロッド 5 支持基板 6 単結晶シリコンロッド 7,8,9,10 単結晶シリコンウェーハ 7b 酸化膜 4 Polycrystalline silicon rod 5 Support substrate 6 Single crystalline silicon rod 7,8,9,10 Single crystalline silicon wafer 7b Oxide film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 鏡面加工ならびに酸化処理を行った特定
の形状の無転位単結晶シリコンウェーハを、鏡面加工を
施した大口径の多結晶シリコン、ガラス、セラミックス
または金属からなる支持基板に貼り合わせた後、前記無
転位単結晶シリコンウェーハを所定の厚さに研磨するこ
とを特徴とする貼り合わせSOI基板の製造方法。
1. A dislocation-free single crystal silicon wafer having a specific shape that has been mirror-finished and oxidized is bonded to a support substrate made of mirror-finished large-diameter polycrystalline silicon, glass, ceramics or metal. Then, the method for manufacturing a bonded SOI substrate, which comprises polishing the dislocation-free single crystal silicon wafer to a predetermined thickness.
【請求項2】 前記特定の形状が、正六角形、正四角
形、長方形または正三角形であることを特徴とする請求
項1の貼り合わせSOI基板の製造方法。
2. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the specific shape is a regular hexagon, a regular square, a rectangle or a regular triangle.
【請求項3】 その世代の技術では製造不可能な大口径
の単結晶シリコンウェーハと同等以上の直径を有する多
結晶シリコン、ガラス、セラミックスまたは金属からな
る支持基板に、特定の形状に加工した複数個の無転位単
結晶シリコンウェーハを酸化膜を介して貼り合わせたこ
とを特徴とする貼り合わせSOI基板。
3. A support substrate made of polycrystalline silicon, glass, ceramics, or metal having a diameter equal to or larger than that of a large-diameter single crystal silicon wafer that cannot be manufactured by the technology of the generation, and a plurality of substrates are processed into a specific shape. A bonded SOI substrate in which individual dislocation-free single crystal silicon wafers are bonded via an oxide film.
【請求項4】 前記支持基板に、エレクトロニクス・シ
ステムを構成するために必要な複数種類の無転位単結晶
シリコンウェーハをそれぞれ所定の位置に貼り合わせた
ことを特徴とする請求項3の貼り合わせSOI基板。
4. The bonded SOI according to claim 3, wherein a plurality of types of dislocation-free single crystal silicon wafers necessary for constructing an electronic system are bonded to predetermined positions on the supporting substrate, respectively. substrate.
JP18651694A 1994-07-15 1994-07-15 Manufacture of stuck soi substrate and stuck soi substrate Pending JPH0832038A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP18651694A JPH0832038A (en) 1994-07-15 1994-07-15 Manufacture of stuck soi substrate and stuck soi substrate
TW084113188A TW330303B (en) 1994-07-15 1995-12-11 Manufacturing method of bonding SOI substrate and bonding SOI substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18651694A JPH0832038A (en) 1994-07-15 1994-07-15 Manufacture of stuck soi substrate and stuck soi substrate

Publications (1)

Publication Number Publication Date
JPH0832038A true JPH0832038A (en) 1996-02-02

Family

ID=16189870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18651694A Pending JPH0832038A (en) 1994-07-15 1994-07-15 Manufacture of stuck soi substrate and stuck soi substrate

Country Status (2)

Country Link
JP (1) JPH0832038A (en)
TW (1) TW330303B (en)

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US6843848B2 (en) * 2000-03-24 2005-01-18 Siltronic Ag Semiconductor wafer made from silicon and method for producing the semiconductor wafer
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US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
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