WO2009025368A1 - 半導体記憶装置及び半導体記憶装置の製造方法 - Google Patents

半導体記憶装置及び半導体記憶装置の製造方法 Download PDF

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Publication number
WO2009025368A1
WO2009025368A1 PCT/JP2008/065039 JP2008065039W WO2009025368A1 WO 2009025368 A1 WO2009025368 A1 WO 2009025368A1 JP 2008065039 W JP2008065039 W JP 2008065039W WO 2009025368 A1 WO2009025368 A1 WO 2009025368A1
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WIPO (PCT)
Prior art keywords
storage device
semiconductor storage
conductivity type
semiconductor substrate
semiconductor
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Application number
PCT/JP2008/065039
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English (en)
French (fr)
Inventor
Makoto Mizukami
Hideyuki Funaki
Original Assignee
Kabushiki Kaisha Toshiba
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Kabushiki Kaisha Toshiba filed Critical Kabushiki Kaisha Toshiba
Priority to JP2009529080A priority Critical patent/JPWO2009025368A1/ja
Publication of WO2009025368A1 publication Critical patent/WO2009025368A1/ja
Priority to US12/710,172 priority patent/US8410545B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

　本発明の半導体記憶装置は、半導体基板と、半導体基板の上面の一部に配置された埋め込み絶縁膜と、半導体基板の上面の他の一部に配置された半導体層５とを備え、メモリセルトランジスタＭＴ１１，ＭＴ１２，ＭＴ１ｎ，ＭＴ２１，ＭＴ２２，ＭＴ２ｎ，ＭＴ３１，ＭＴ３２，ＭＴ３ｎ，・・・，ＭＴｍ１，ＭＴｍ２，ＭＴｍｎのそれぞれは、半導体層５に列方向に規定された第１導電型のソース領域、第１導電型のドレイン領域及び第１導電型のチャネル領域と、チャネル領域の行方向の側面に配置されたゲート部とを備える。
PCT/JP2008/065039 2007-08-22 2008-08-22 半導体記憶装置及び半導体記憶装置の製造方法 WO2009025368A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009529080A JPWO2009025368A1 (ja) 2007-08-22 2008-08-22 半導体記憶装置及び半導体記憶装置の製造方法
US12/710,172 US8410545B2 (en) 2007-08-22 2010-02-22 Semiconductor memory and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007216323 2007-08-22
JP2007-216323 2007-08-22

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/710,172 Continuation US8410545B2 (en) 2007-08-22 2010-02-22 Semiconductor memory and method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2009025368A1 true WO2009025368A1 (ja) 2009-02-26

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Country Status (3)

Country Link
US (1) US8410545B2 (ja)
JP (1) JPWO2009025368A1 (ja)
WO (1) WO2009025368A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012109564A (ja) * 2010-11-08 2012-06-07 Imec フローティングゲートメモリ構造の製造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009107241A1 (ja) 2008-02-29 2009-09-03 株式会社 東芝 マルチドットフラッシュメモリ
US9941271B2 (en) * 2013-10-04 2018-04-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Fin-shaped field effect transistor and capacitor structures

Citations (5)

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JPH04113655A (ja) * 1990-09-03 1992-04-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2006155750A (ja) * 2004-11-29 2006-06-15 Sony Corp 半導体記憶装置
JP2007110029A (ja) * 2005-10-17 2007-04-26 Toshiba Corp 半導体記憶装置及びその製造方法
JP2007158232A (ja) * 2005-12-08 2007-06-21 Toshiba Corp 不揮発性半導体メモリとその製造方法
JP2007180389A (ja) * 2005-12-28 2007-07-12 Toshiba Corp 半導体記憶装置及びその製造方法

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JPH07245340A (ja) * 1994-03-04 1995-09-19 Toshiba Corp 半導体装置
JP2000174241A (ja) 1998-12-10 2000-06-23 Toshiba Corp 不揮発性半導体記憶装置
IT1308074B1 (it) 1999-06-04 2001-11-29 Pro Cord Srl Sedia con sedile e schienale oscillanti in modo sincronizzato
US6969656B2 (en) * 2003-12-05 2005-11-29 Freescale Semiconductor, Inc. Method and circuit for multiplying signals with a transistor having more than one independent gate structure
KR100574340B1 (ko) * 2004-02-02 2006-04-26 삼성전자주식회사 반도체 장치 및 이의 형성 방법
JP2005243709A (ja) * 2004-02-24 2005-09-08 Toshiba Corp 半導体装置およびその製造方法
JP4354892B2 (ja) 2004-09-21 2009-10-28 株式会社東芝 不揮発性半導体記憶装置の製造方法
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JP4592580B2 (ja) * 2005-12-19 2010-12-01 株式会社東芝 不揮発性半導体記憶装置
JP2007201244A (ja) * 2006-01-27 2007-08-09 Renesas Technology Corp 半導体装置
JP2008053361A (ja) * 2006-08-23 2008-03-06 Toshiba Corp 半導体記憶装置及び半導体記憶装置の製造方法
WO2009107241A1 (ja) 2008-02-29 2009-09-03 株式会社 東芝 マルチドットフラッシュメモリ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04113655A (ja) * 1990-09-03 1992-04-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2006155750A (ja) * 2004-11-29 2006-06-15 Sony Corp 半導体記憶装置
JP2007110029A (ja) * 2005-10-17 2007-04-26 Toshiba Corp 半導体記憶装置及びその製造方法
JP2007158232A (ja) * 2005-12-08 2007-06-21 Toshiba Corp 不揮発性半導体メモリとその製造方法
JP2007180389A (ja) * 2005-12-28 2007-07-12 Toshiba Corp 半導体記憶装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012109564A (ja) * 2010-11-08 2012-06-07 Imec フローティングゲートメモリ構造の製造方法

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US20100187594A1 (en) 2010-07-29
JPWO2009025368A1 (ja) 2010-11-25
US8410545B2 (en) 2013-04-02

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