Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Definitions

• This invention relates generally to automatic test equipment for electronics, and, more particularly, to techniques for generating periodic signals for testing electronic devices.
• ATE automatic test equipment
• ATE One of the basic functions of ATE is to generate signals of predetermined frequency. These signals may include, for example, digital clocks, analog waveforms, and RF waveforms. Often, particular testing scenarios require a test system to produce multiple signals of different frequency. Commonly, frequency and phase differences between different signals must be precisely controlled. Phase-locked loops are commonly used in ATE systems to produce signals with precisely controlled frequency and phase.
• Fig. 1 shows a block diagram of a conventional phase-locked loop (PLL) 100.
• the PLL 100 receives an input signal, F IN , and generates an output signal, F O u ⁇ -
• the PLL 100 includes a phase detector 1 10, a loop filter 1 12, and a voltage-controlled oscillator (VCO) 1 14. It also includes an output frequency divider 1 18 and a feedback frequency divider 1 16.
• the input signal, Fm may be supplied by any suitable source, such as a crystal oscillator
• the conventional PLL 100 is a closed loop feedback system that operates essentially as follows.
• the phase detector 1 10 compares the input signal F
• the loop filter 1 12 smoothes the error signal and generally helps to stabilize the feedback loop
• the VCO 1 14 converts the filter's output signal into an oscillatory signal, Fvco, which has a frequency that vanes in relation to the filter's output signal.
• the feedback divider 1 16 (generally a counter) divides the frequency of Fvco by an integer, M, to produce the feedback signal, F FB .
• the output divider 1 18 divides the frequency of Fvco by an integer, N, to produce FOUT AS the feedback tends to d ⁇ ve the difference between F
• the conventional PLL 100 provides many benefits. For example, output frequency FOUT can be varied, through approp ⁇ ate selection of N and M, over a wide range of values In addition, phase noise in the PLL can generally be reduced by setting the bandwidth of the loop filter 1 12 to arbitrarily low values. Nevertheless, we have recognized certain shortcomings in the PLL 100, which limits its usefulness in many ATE applications High frequency applications, such as RF signal generation, require high frequency VCOs. The speed of the VCOs in these applications often greatly exceeds the speed of the phase detectors. This problem is conventionally addressed by making the value of M in the feedback divider 1 16 very large.
• the frequency divider 1 16 also adds noise directly Frequency dividers are commonly implemented as counters, which are known to create spu ⁇ ous noise at their outputs. Although this noise can be attenuated by the loop filter 1 12, attenuation cannot generally be achieved without setting the bandwidth of the loop filter to a much lower frequency than the offending noise components of the divider 1 16. Reducing bandwidth to this degree, however, has the effect of reducing programming speed of the PLL 100, which can negatively impact ATE system performance and throughput.
• phase-locking circuit that can produce high frequency signals with low phase noise, without sacrificing programming speed.
• a phase-locking circuit employs a sampler for producing aliased feedback signals, upon which a circuit is caused to lock.
• Fig. 1 is a block diagram of a conventional phase-locked loop that is operable to produce a wide range of frequencies
• Fig. 2 is a block diagram of phase-locking circuitry according to an illustrative embodiment of the invention
• Fig. 3 is a frequency plot showing how frequencies higher than the Nyquist rate can alias to frequencies lower than the Nyquist rate in the circuit of Fig. 2;
• Fig. 4 is a frequency plot showing how a band of frequencies higher than the Nyquist rate can alias to a band of frequencies lower than the Nyquist rate in the circuit of Fig. 2;
• Fig. 5 is a simplified schematic of an illustrative embodiment of phase-locking circuitry, wherein harmonics of the VCO output signal are employed to improve precision;
• Fig. 6 is a frequency plot showing how various bands of harmonics are created in the circuit of Fig. 5, wherein one or more of the harmonic bands are aliased to frequencies lower than the Nyquist rate;
• Fig. 7 is a block diagram showing an illustrative embodiment of phase-locking circuitry that employs a digital phase detector and a digital loop filter;
• Fig. 8 is a simplified block diagram of automatic test equipment that includes phase locking circuitry according to one or more embodiments of the invention
• Fig. 9 is a block diagram of a digital phase detector that is suitable for use with the phase-locking circuitry of Fig. 7;
• Fig. 10 is a block diagram of another digital phase detector that is suitable for use with the phase-locking circuitry of Fig. 7.
• Fig. 2 shows an illustrative embodiment of a phase-locking circuit 200.
• the phase-locking circuit 200 receives an input signal, FIN, and produces an output signal, FOUT.
• the circuit 200 includes a sampler 202, a phase detector 210, a loop filter 212, and a controllable oscillator, such as a VCO (voltage-controlled oscillator) 214.
• the sampler 202 receives a feedback signal, FFB, at its input and provides a sampled feedback signal, SFFB, at its output.
• the phase detector 210 has 2 inputs and an output.
• the first input receives the input signal FJ N
• the second input receives the sampled feedback signal, SFFB-
• the loop filter 212 and the VCO 214 each have an input and an output.
• the circuit 200 also includes a circuit path 220, coupled from the output of the
• F F B- Bandpass filters 230a - 230n are preferably provided in the circuit path 220. These bandpass filters are preferably individually selectable via switches 240a - 24On. Each filter preferably has a different center frequency.
• the sampler 202 is made to sample the feedback signal, FFB, at a sampling rate Fs.
• the phase detector 210 receives the sampled feedback signal, SFFB, and outputs an error signal, ⁇ -Err.
• the error signal varies in response to the difference between SFFB and FIN.
• the loop filter 212 filters the error signal and helps to stabilize the loop.
• the VCO 214 converts the filtered error signal into an oscillatory waveform, Fvco- The frequency of Fvco varies in response to the level of the filtered error signal.
• One of the bandpass filters 230a - 230n is selected for filtering noise from Fvco-
• the selected filter is preferably the one having the center frequency that is closest to the expected frequency of the Fvco.
• the desired filter is selected by closing its associated switch (one of 240a - 24On) and opening the remaining switches.
• the circuit 200 behaves in an essentially normal manner when the frequency of
• Fvco is less than the Nyquist rate (Fs/2) of the sampler. However, significant differences arise when the frequency of Fvco is greater than the Nyquist rate.
• aliasing arises in discrete-time systems when a signal being sampled at a rate Fs contains frequency components greater than Fs/2. Aliasing causes out-of-band frequencies, e.g., those above the Nyquist rate, to appear as images within the system's bandwidth. These images are normally regarded as errors. However, we have recognized that these aliased images can be used to improve performance.
• Fig. 3 shows a frequency plot of a discrete-time system that is sampled at a rate Fs. The horizontal line represents frequency, with zero frequency (DC) appearing at the left and increasing frequencies extending to the right. Frequencies are represented in multiples of the Nyquist rate, Fs/2.
• frequencies above the Nyquist rate produce aliased images within the system bandwidth (i.e., below the Nyquist rate).
• any component that is an increment ⁇ greater than any multiple of the Nyquist rate produces an aliased image at a frequency ⁇ within the system bandwidth.
• aliased images has significant consequences in the phase-locking circuit of Fig. 2.
• the frequency of Fvro exceeds Fs/2, an aliased image of that frequency appears within the sampler's bandwidth and the circuit is made to lock on that image.
• the phase-locking circuit 200 can be operated with substantial gain without requiring a frequency divider in its feedback path.
• the circuit 200 can be made to produce arbitrarily high frequencies, limited only by its analog characteristics.
• Output frequency ambiguity can arise if the VCO 214 operates over too large a frequency range. For instance, if the output range (maximum frequency minus minimum frequency) exceeds Fs/2, then the phase-locking circuit may be able to satisfy its feedback conditions at two or more different VCO frequencies. Preferably, this condition is avoided by limiting the bandwidth of each of the bandpass filters 230a - 23On to less than Fs/2. Alternatively, it may be avoided by selecting a VCO 214 that has an output range less than Fs/2.
• Fig. 4 is a frequency plot that shows the effect of aliasing on a band of frequencies.
• a band or range of frequencies 410 above the Nyquist rate is aliased to create a mirror image 412 within the system bandwidth.
• the width of the bands 410 and 412 are identical. If the band 410 is 1 kHz wide, the band 412 will be 1 kHz wide. If it is assumed that the band 410 represents the frequencies produced by the VCO 214, then the width of the band 410 can be regarded as the phase noise (or equivalently, timing jitter) in FVC ⁇ - In the conventional phase-locked loop of Fig.
• the feedback divider would reduce the width of the band 410, effectively reducing loop gain and sensitivity, hi the phase-locking circuit of Fig. 2, however, loop gain and sensitivity are preserved.
• the phase noise around Fvco is aliased back into the system's bandwidth without compression or attenuation.
• the use of aliased signals therefore allows the phase-locking circuit 200 to be operated at high gain (where FOUT is much greater than F ⁇ M) without the need for feedback dividers. It allows open loop gain and therefore precision to be kept high. Since feedback dividers are not required, the noise spurs normally introduced by these devices are avoided. Therefore, the need to slow down the loop filter and suffer the consequent reduction in programming speed is also avoided.
• a phase-locking circuit 500 includes a sampler 502, a phase detector 510, a loop filter 512, a controllable oscillator, such as a VCO 514, and a bank of bandpass filters 530. These are similar to the sampler 202, phase detector 210, loop filter 212, VCO 214, and bandpass bank of Fig. 2. However, the circuit 500 also includes a harmonic generator 540.
• the harmonic generator 540 receives a filtered version of Fvco and generates one or more harmonics of that signal. These harmonics, or overtones, have frequencies that are integer multiples of the frequency of Fvco. i.e., the fundamental frequency.
• a second bandpass bank 550 is optionally coupled to the output of the harmonic generator 540.
• the second bandpass bank 550 may be used to select one or more specific harmonics to be presented to the sampler 502. Selection of particular harmonics is not required, however.
• the harmonic generator 540 effectively multiplies the width of noise bands fed back to the sampler 502. It therefore further increases open loop gain and sensitivity of the phase-locking circuit 500.
• Fig. 6 is a frequency plot that shows the mechanism by which phase noise is multiplied.
• Fvco and its harmonics create aliased images within the system's bandwidth.
• a width of a band of phase noise around each harmonic of Fvco can be seen to vary in proportion to the order of the harmonic.
• the band of noise around the 3Fvco is three times as wide as the band around Fvco-
• Each of these bands is aliased back into the bandwidth of the system. Absent a bandpass bank 550, all of these aliased bands appear simultaneously at the input of the sampler 502.
• the elements of the phase-locking circuits 200/500 can be implemented in a wide variety of ways.
• the phase detector 210/510 can be either an analog phase detector or a digital phase detector.
• the loop filter 212/512 can be either an analog loop filter or a digital loop filter. Analog and digital phase detectors and loop filters are well- known in the art. If an analog phase detector is used, the sampler 202/502 is implemented as an analog sampling circuit, such as a sample-and-hold circuit or a track-and-hold circuit. These devices are well-known and readily available off the shelf.
• the input signal FI N is preferably an analog signal, such as the output of a crystal oscillator.
• the sampler 202/502 preferably includes an analog sampling circuit (described above) coupled to an analog-to-digital converter (ADC).
• ADC analog-to-digital converter
• the analog sampling circuit and ADC are both clocked at Fs.
• a sampling ADC is used, i.e., one which includes both an analog sampling circuit and an ADC in a single device package. Digital values are thus provided to the phase detector at a rate Fs.
• FIN is preferably a digital signal.
• the VCO 214/514 is preferably a conventional type. VCOs are well-known and are commercially available off the shelf.
• the harmonic generator 540 is preferably implemented as a non-linear analog circuit, such as a clipping circuit or a commercially available RF comb generator. As is known, clipping circuits flatten the positive and negative peaks of a sinusoid, thus introducing harmonics of the sinusoid's fundamental frequency. Optionally, the harmonic generator 540 may be equipped with an amplifier for boosting low amplitude harmonics.
• Fig. 7 shows a largely digital embodiment of a phase-locking circuit 700 with a particular arrangement of elements. The circuit includes a digital phase detector 710 and a sampling ADC 712.
• the digital phase detector 710 receives input data, FREF, ⁇ R£F, which is indicative of a reference frequency and a reference phase.
• the digital phase detector 710 compares this reference frequency and phase with a sampled feedback signal from the sampling ADC 712 to produce a digital phase error.
• a digital loop filter 714 filters the digital phase error, and a digital-to-analog converter (DAC) converts the filtered phase error into an analog signal.
• An analog filter smoothes the output of the DAC 716, and a VCO 720 converts the smoothed DAC output into an oscillatory signal.
• a first bandpass filter bank 722, a harmonic generator 730, and an optional second bandpass bank 740 operate essentially as described above in connection with the first bandpass bank 530, the harmonic generator 540, and the optional second bandpass bank 550 of Fig. 5.
• the digital loop filter 714 offers a particular advantage in the circuit 700. If any of the circuit elements, such as the ADC 712 or DAC 716, are found to repeatably generate noise at known frequencies, or if noise at certain known frequencies is injected into circuit from its environment, the digital loop filter 714 can be programmed to have low gain, or a "zero,” at each offending noise frequency. Designing the loop filter 714 in this fashion reduces noise in the output signal, Fou ⁇ » and contributes to the overall precision of the circuit.
• Fig. 9 shows an example of a digital phase detector that is particularly suitable for the phase-locking circuit 700.
• the first input of the digital phase detector is coupled to a digital oscillator 914, and the second input of the digital phase detector is coupled to a down-converter 910.
• the digital oscillator 914 Based upon the input data (FREF, ⁇ PREF), the digital oscillator 914 synthesizes a digital reference signal having frequency a Fosc and a phase ⁇ osc- Fosc is preferably equal to F REF , and ⁇ osc is preferably equal to ⁇ REF-
• the digital reference signal is preferably a quadrature reference signal, i.e., it is provided in two parts that represent two sinusoids separated by a phase difference of 90- degrees.
• a first part of the quadrature reference signal is designated as a cosine and a second part is designated as a sine. Therefore, the first part of the quadrature reference signal has the form Cos(2 ⁇ Fosd + ⁇ osc) and the second part has the form Sin(2 ⁇ Fosct + ⁇ osc)-
• the quadrature reference signal is provided to the down-converter 910, whereupon it is mixed with the feedback signal.
• the feedback signal can be regarded more generally as a sampled periodic signal having the form Cos(2 ⁇ F !N t + ⁇ ).
• the down-converter 910 produces a difference signal in response to the sampled periodic signal and quadrature reference signal.
• the difference signal is preferably a quadrature signal having two parts: one part having substantially the form Cos [2 ⁇ (FM - Fosc)t + ⁇ i N - ⁇ osc], and the other part having substantially the form Sin[2 ⁇ (F ⁇ - Foscjt + ⁇ IN - ⁇ osc]- Therefore, the frequency of the quadrature difference signal equals the difference between the input and oscillator frequencies, F
• the quadrature difference signal is provided to a phase extractor 916.
• the phase extractor 916 generates a cumulative phase difference represented by the quadrature difference signal.
• the phase extractor 916 performs an ATAN2 function.
• ATAN2 generates a 4-quadrant inverse tangent of a quotient of two inputs. Where the two inputs to ATAN2 are a sine and a cosine of the same angle, ⁇ , ATAN2 [sin( ⁇ ), cos( ⁇ )] is simply the angle, ⁇ .
• ATAN2 of the two parts of the quadrature difference signal evaluates to [2 ⁇ (FIN - Fosc)t + ⁇ M - ⁇ osc ]- This value corresponds to the cumulative phase difference between the output of the digital oscillator 914 and the sampled periodic signal. IfFnM, Fosc, ⁇ N and ⁇ osc are constant, the values described by the cumulative phase difference take the form of a straight line over time.
• the cumulative phase difference produced by the phase extractor 916 provides a digital phase error.
• a phase ⁇ A DJ may be added to or subtracted from the cumulative phase difference, via a summer 920, to adjust the phase error passed to other components of the phase-locking circuit 700. Adding or subtracting phase via the summer 920 has the effect of shifting the phase of the synthesizer's output signal, Four-
• the digital oscillator 914 should be able to generate the quadrature reference signal with precision.
• Fosc should substantially equal the frequency specified by FREF (nominally, Fosc and FREF are equal) and ⁇ osc must substantially equal the phase specified by ⁇ R £F (nominally, ⁇ osc and q> R£F are equal).
• FREF frequency specified by FREF
• ⁇ osc phase specified by ⁇ R £F (nominally, ⁇ osc and q> R£F are equal).
• the digital oscillator 914 can employ a look-up table for generating the quadrature reference signal.
• the look-up table associates pre-stored values of the quadrature reference signal with successive cycles of the sample clock.
• the digital oscillator can thus generate the quadrature reference signal simply by cycling through values stored its look-up table.
• Fig. 10 shows another example of a suitable digital phase detector 710.
• the down-converter 1010, phase extractor 1016, and summer 1020 of Fig. 10 are substantially the same as the down-converter 910, phase extractor 916, and summer 920 of Fig. 9.
• Fig. 10 also includes a calculation unit 1012, an accumulator 1018, and a second summer 1022.
• the calculation unit 1012 divides the input data (F REF> ⁇ REF ) into two parts, a primary part and a secondary part.
• the primary part (Fosc, ⁇ osc) represents an approximation of the reference signal (F REF , ⁇ REF ) that the digital oscillator 1014 can readily generate, such as by using a look-up table.
• the secondary part ( ⁇ RES ) represents a residual phase value, i.e., the error in the above approximation.
• the accumulator 1018 accumulates (i.e., adds to its own contents) values of ⁇ RES on each cycle of Fs.
• the values held by the accumulator 1018 when viewed over time, thus take the form of a straight line.
• the output of the phase extractor 1016 does not account for the secondary part of the input data.
• the summer 1022 corrects this output by subtracting the output of the accumulator 1018 from the output of the phase extractor 1016.
• the output of the summer 1022 thus accounts for both the primary and secondary parts of the input data, and produces an accurate representation of phase error between the sampled periodic signal and the reference (i.e., F REF , ⁇ REF )-
• the reference data (F REF , ⁇ REF ) is preferably variable.
• the reference data is preferably programmable for establishing different output frequencies.
• the values of the integers K and L are preferably updated each time a new value of reference data is programmed. To minimize the size of the residue, K is preferably made as large as practicable. K and L may be computed manually, or may be generated by software, firmware, or hardware based upon the desired output frequency and the sampling rate.
• phase error is updated at a high frequency, such as once per cycle of the sample clock.
• phase error is provided with exceedingly high resolution. Because the phase residue, ⁇ R ES, is managed independently of the primary part of the reference frequency, a large number of bits of numerical precision can be applied to (P KES - Also, the contribution of ⁇ RES to the overall phase error can be made exceedingly small by increasing the number of cycles of Fosc (i.e., the value of K) that are stored in the look-up table used to implement the digital oscillator 1014.
• Fig. 8 shows an application of phase-locking circuits of the types shown in Figs. 2, 5, and 7.
• an automatic test system 812 is controlled by a host computer 810 for testing a UUT (unit under test) 840.
• the UUT may be any type of device or assembly to be tested.
• the automatic test system 812 includes instruments, such as an analog instrument 820, a digitizer 822, and an arbitrary waveform generator (AWG) 824.
• the automatic test system 812 also includes a plurality of digital electronic channels, shown generally as digital pins 826, 828, and 830. The digital electronic channels are arranged for sourcing and sensing digital signals.
• the automatic test system 812 includes a plurality of phase-locking circuits 816a-g.
• phase-locking circuits are of the same general type shown in any of Figs. 2, 5, and 7.
• the phase- locking circuits 816a-g each receive a clock signal, Fs, from a system clock 814. They each also receive respective input signals (or data) from the host computer 810 for specifying desired output frequencies and phases. In response to the clock and respective input, the phase-locking circuits 816a-g each generate a respective periodic output signal.
• the output signals are provided to the instruments 820, 822, and 824, which can use frequency references or clocks for their normal operation.
• the output signals also provide clocks for controlling the digital pins 826, 828, and 830. They may further be used to provide a frequency reference for a pattern generator 818.
• the pattern generator 818 operates in conjunction the with phase-locking circuits for causing the digital pins to source and/or sense digital signals with specified formatting and at precisely controlled instants of time.
• phase- locking circuits shown and described preferably include a bank of bandpass filters (230, 530, and 722) coupled to the output of the VCO, these filters are not strictly required.
• bandpass filters are preferably implemented as analog filters that precede the sampler (202, 502) or the sampling ADC (712), they can alternatively be implemented as digital filters provided at the output of the sampler or sampling ADC.
• a particular advantage of the phase-locking circuits disclosed is that they provide closed loop frequency gain without requiring frequency dividers (such as counters) in their feedback paths. This should not be taken to mean, however, that feedback dividers are prohibited.
• the sampling rate Fs with which the sampler (202, 502) or sampling ADC (712) is operated, is preferably fixed. However, this is not required. It may also be variable. According to one variant, Fs may be derived from the output of the VCO.
• the VCO is made to operate at frequencies higher than the Nyquist rate (Fs/2); however, this is not required, either. Aliasing can occur with VCO frequencies below the Nyquist rate if a harmonic generator (540, 730) produces harmonics above the Nyquist rate.

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• 2007
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