WO2009008031A1 - 半導体メモリおよびシステム - Google Patents

半導体メモリおよびシステム Download PDF

Info

Publication number
WO2009008031A1
WO2009008031A1 PCT/JP2007/000753 JP2007000753W WO2009008031A1 WO 2009008031 A1 WO2009008031 A1 WO 2009008031A1 JP 2007000753 W JP2007000753 W JP 2007000753W WO 2009008031 A1 WO2009008031 A1 WO 2009008031A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
pair
access control
control circuits
logic
Prior art date
Application number
PCT/JP2007/000753
Other languages
English (en)
French (fr)
Inventor
Hiroyuki Kobayashi
Daisuke Kitayama
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to JP2009522424A priority Critical patent/JP4473943B2/ja
Priority to KR1020107002809A priority patent/KR101102130B1/ko
Priority to PCT/JP2007/000753 priority patent/WO2009008031A1/ja
Publication of WO2009008031A1 publication Critical patent/WO2009008031A1/ja
Priority to US12/684,502 priority patent/US8116114B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1806—Address conversion or mapping, i.e. logical to physical address

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

　ビット線対が配線された一対のアクセス制御回路は、同じデータ端子に対応し、かつ異なるアドレスが割り当てられる。データスワップ回路は、テストモード中に、アクセス制御回路の一方を使用するときに、一対のデータ端子と一対のデータ線との接続の入れ替えを禁止し、アクセス制御回路の他方を使用するときに一対のデータ端子と一対のデータ線との接続を入れ替える。これにより、データ端子に供給するデータ信号の論理を変更することなく、論理が互いに異なるビット線に同じ論理レベルのデータ信号を与えることができる。一対のアクセス制御回路の間に配置されるコンタクトと、このコンタクトに両側に隣接するビット線との間にストレスを与えることができる。この結果、テストパターンの設計を容易にでき、テストの効率を向上できる。
PCT/JP2007/000753 2007-07-11 2007-07-11 半導体メモリおよびシステム WO2009008031A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009522424A JP4473943B2 (ja) 2007-07-11 2007-07-11 半導体メモリおよびシステム
KR1020107002809A KR101102130B1 (ko) 2007-07-11 2007-07-11 반도체 메모리 및 시스템
PCT/JP2007/000753 WO2009008031A1 (ja) 2007-07-11 2007-07-11 半導体メモリおよびシステム
US12/684,502 US8116114B2 (en) 2007-07-11 2010-01-08 Semiconductor memory and system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000753 WO2009008031A1 (ja) 2007-07-11 2007-07-11 半導体メモリおよびシステム

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/684,502 Continuation US8116114B2 (en) 2007-07-11 2010-01-08 Semiconductor memory and system

Publications (1)

Publication Number Publication Date
WO2009008031A1 true WO2009008031A1 (ja) 2009-01-15

Family

ID=40228228

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000753 WO2009008031A1 (ja) 2007-07-11 2007-07-11 半導体メモリおよびシステム

Country Status (4)

Country Link
US (1) US8116114B2 (ja)
JP (1) JP4473943B2 (ja)
KR (1) KR101102130B1 (ja)
WO (1) WO2009008031A1 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5606883B2 (ja) * 2010-11-22 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
KR102125568B1 (ko) * 2014-02-19 2020-06-23 에스케이하이닉스 주식회사 반도체 장치 및 그 테스트 방법
JP6383637B2 (ja) * 2014-10-27 2018-08-29 ルネサスエレクトロニクス株式会社 半導体装置
KR20180021510A (ko) * 2016-08-22 2018-03-05 삼성전자주식회사 메모리 장치 및 중앙 처리 장치
US10811057B1 (en) 2019-03-26 2020-10-20 Micron Technology, Inc. Centralized placement of command and address in memory devices
US10978117B2 (en) 2019-03-26 2021-04-13 Micron Technology, Inc. Centralized placement of command and address swapping in memory devices
US10811059B1 (en) 2019-03-27 2020-10-20 Micron Technology, Inc. Routing for power signals including a redistribution layer
US11031335B2 (en) 2019-04-03 2021-06-08 Micron Technology, Inc. Semiconductor devices including redistribution layers
US10937481B1 (en) * 2019-08-07 2021-03-02 Arm Limited Polarity swapping circuitry

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285248A (ja) * 2004-03-30 2005-10-13 Renesas Technology Corp 半導体記憶装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2646972B2 (ja) 1993-11-01 1997-08-27 日本電気株式会社 多ビットメモリ
US5745420A (en) * 1995-07-31 1998-04-28 Sgs-Thomson Microelectronics, Inc. Integrated memory circuit with sequenced bitlines for stress test
JP2001084797A (ja) * 1999-09-14 2001-03-30 Mitsubishi Electric Corp 半導体記憶装置
JP2002319299A (ja) 2001-04-24 2002-10-31 Mitsubishi Electric Corp 半導体記憶装置
US7768840B1 (en) * 2007-08-29 2010-08-03 Virage Logic Corporation Memory modeling using an intermediate level structural description

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285248A (ja) * 2004-03-30 2005-10-13 Renesas Technology Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR101102130B1 (ko) 2012-01-02
JP4473943B2 (ja) 2010-06-02
JPWO2009008031A1 (ja) 2010-08-26
US20100142250A1 (en) 2010-06-10
KR20100034033A (ko) 2010-03-31
US8116114B2 (en) 2012-02-14

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