WO2009006284A3 - Dé semi-conducteur doté d'une couche de redistribution - Google Patents

Dé semi-conducteur doté d'une couche de redistribution Download PDF

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Publication number
WO2009006284A3
WO2009006284A3 PCT/US2008/068542 US2008068542W WO2009006284A3 WO 2009006284 A3 WO2009006284 A3 WO 2009006284A3 US 2008068542 W US2008068542 W US 2008068542W WO 2009006284 A3 WO2009006284 A3 WO 2009006284A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor die
redistribution layer
tape
assembly
wafer
Prior art date
Application number
PCT/US2008/068542
Other languages
English (en)
Other versions
WO2009006284A2 (fr
Inventor
Chien-Ko Liao
Chin-Tien Chiu
Jack Chang Chien
Cheemen Yu
Hem Takiar
Original Assignee
Sandisk Corp
Chien-Ko Liao
Chin-Tien Chiu
Jack Chang Chien
Cheemen Yu
Hem Takiar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/769,937 external-priority patent/US7763980B2/en
Priority claimed from US11/769,927 external-priority patent/US7772047B2/en
Application filed by Sandisk Corp, Chien-Ko Liao, Chin-Tien Chiu, Jack Chang Chien, Cheemen Yu, Hem Takiar filed Critical Sandisk Corp
Priority to CN2008800224541A priority Critical patent/CN101765911B/zh
Priority to EP08796037.3A priority patent/EP2179442A4/fr
Publication of WO2009006284A2 publication Critical patent/WO2009006284A2/fr
Publication of WO2009006284A3 publication Critical patent/WO2009006284A3/fr

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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention a trait à un dispositif à semi-conducteur doté d'une couche de redistribution et à ses procédés de formation. Après la fabrication d'un dé semi-conducteur sur une tranche, un assemblage de bande est appliqué sur une surface de la tranche, en contact avec les surfaces de chaque dé semi-conducteur sur la tranche. L'assemblage de bande inclut une bande d'affûtage arrière en tant que couche de base et un assemblage de film collé à la bande d'affûtage arrière. L'assemblage de film inclut à son tour un film adhésif sur lequel est déposée une couche mince de matériau conducteur. Le motif de la couche de redistribution est tracé dans l'assemblage de bande, à l'aide par exemple d'un laser. Par la suite, les parties non chauffées de l'assemblage de bande peuvent être supprimées, ce qui laisse le motif de la couche de redistribution chauffé sur chaque dé semi-conducteur.
PCT/US2008/068542 2007-06-28 2008-06-27 Dé semi-conducteur doté d'une couche de redistribution WO2009006284A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2008800224541A CN101765911B (zh) 2007-06-28 2008-06-27 具有重新分布层的半导体芯片
EP08796037.3A EP2179442A4 (fr) 2007-06-28 2008-06-27 Dé semi-conducteur doté d'une couche de redistribution

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/769,937 US7763980B2 (en) 2007-06-28 2007-06-28 Semiconductor die having a distribution layer
US11/769,937 2007-06-28
US11/769,927 US7772047B2 (en) 2007-06-28 2007-06-28 Method of fabricating a semiconductor die having a redistribution layer
US11/769,927 2007-06-28

Publications (2)

Publication Number Publication Date
WO2009006284A2 WO2009006284A2 (fr) 2009-01-08
WO2009006284A3 true WO2009006284A3 (fr) 2009-04-09

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EP (1) EP2179442A4 (fr)
KR (1) KR101475467B1 (fr)
CN (1) CN101765911B (fr)
TW (1) TWI371807B (fr)
WO (1) WO2009006284A2 (fr)

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US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9196509B2 (en) 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US10672624B2 (en) 2011-12-30 2020-06-02 Deca Technologies Inc. Method of making fully molded peripheral package on package device
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
AT515443B1 (de) * 2014-02-28 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte
WO2015138359A1 (fr) * 2014-03-10 2015-09-17 Deca Technologies Inc. Dispositif semi-conducteur et procédé comprenant des couches de redistribution épaissies
CN106469657B (zh) * 2015-08-14 2020-03-31 晟碟半导体（上海）有限公司 具有间隔体层的半导体装置、其形成方法和间隔体层带
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects

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US6706557B2 (en) * 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
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Also Published As

Publication number Publication date
KR20100034756A (ko) 2010-04-01
EP2179442A4 (fr) 2013-08-07
WO2009006284A2 (fr) 2009-01-08
EP2179442A2 (fr) 2010-04-28
CN101765911B (zh) 2012-06-27
TWI371807B (en) 2012-09-01
KR101475467B1 (ko) 2014-12-22
TW200910474A (en) 2009-03-01
CN101765911A (zh) 2010-06-30

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