TWI371807B - Semiconductor die having a redistribution layer and the method for fabricating the same - Google Patents

Semiconductor die having a redistribution layer and the method for fabricating the same

Info

Publication number
TWI371807B
TWI371807B TW097124363A TW97124363A TWI371807B TW I371807 B TWI371807 B TW I371807B TW 097124363 A TW097124363 A TW 097124363A TW 97124363 A TW97124363 A TW 97124363A TW I371807 B TWI371807 B TW I371807B
Authority
TW
Taiwan
Prior art keywords
fabricating
same
semiconductor die
redistribution layer
redistribution
Prior art date
Application number
TW097124363A
Other languages
English (en)
Other versions
TW200910474A (en
Inventor
Chien Ko Liao
Chin Tien Chiu
Jack Chang Chien
Cheemen Yu
Hem Takiar
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/769,927 external-priority patent/US7772047B2/en
Priority claimed from US11/769,937 external-priority patent/US7763980B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200910474A publication Critical patent/TW200910474A/zh
Application granted granted Critical
Publication of TWI371807B publication Critical patent/TWI371807B/zh

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
TW097124363A 2007-06-28 2008-06-27 Semiconductor die having a redistribution layer and the method for fabricating the same TWI371807B (en)

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US11/769,927 US7772047B2 (en) 2007-06-28 2007-06-28 Method of fabricating a semiconductor die having a redistribution layer
US11/769,937 US7763980B2 (en) 2007-06-28 2007-06-28 Semiconductor die having a distribution layer

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US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US10672624B2 (en) 2011-12-30 2020-06-02 Deca Technologies Inc. Method of making fully molded peripheral package on package device
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
AT515443B1 (de) * 2014-02-28 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte
WO2015138359A1 (en) * 2014-03-10 2015-09-17 Deca Technologies Inc. Semiconductor device and method comprising thickened redistribution layers
CN106469657B (zh) * 2015-08-14 2020-03-31 晟碟半导体（上海）有限公司 具有间隔体层的半导体装置、其形成方法和间隔体层带
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects

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US6011314A (en) * 1999-02-01 2000-01-04 Hewlett-Packard Company Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
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JP2001323228A (ja) * 2000-05-15 2001-11-22 Nitto Denko Corp 加熱剥離型粘着シート
JP2002076576A (ja) * 2000-08-23 2002-03-15 Nec Corp 配線パターン形成方法およびその方法に用いられる原版
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US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
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EP2179442A2 (en) 2010-04-28
CN101765911A (zh) 2010-06-30
EP2179442A4 (en) 2013-08-07
KR101475467B1 (ko) 2014-12-22
KR20100034756A (ko) 2010-04-01
TW200910474A (en) 2009-03-01
WO2009006284A2 (en) 2009-01-08
CN101765911B (zh) 2012-06-27

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