TW200910474A - Semiconductor die having a redistribution layer and the method for fabricating the same - Google Patents

Semiconductor die having a redistribution layer and the method for fabricating the same Download PDF

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Publication number
TW200910474A
TW200910474A TW097124363A TW97124363A TW200910474A TW 200910474 A TW200910474 A TW 200910474A TW 097124363 A TW097124363 A TW 097124363A TW 97124363 A TW97124363 A TW 97124363A TW 200910474 A TW200910474 A TW 200910474A
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TW
Taiwan
Prior art keywords
die
semiconductor
semiconductor die
adhesive layer
pattern
Prior art date
Application number
TW097124363A
Other languages
Chinese (zh)
Other versions
TWI371807B (en
Inventor
Chien-Ko Liao
Chin-Tien Chiu
Jack-Chang Chien
Cheemen Yu
Hem Takiar
Original Assignee
Sandisk Corp
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Publication date
Priority claimed from US11/769,937 external-priority patent/US7763980B2/en
Priority claimed from US11/769,927 external-priority patent/US7772047B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200910474A publication Critical patent/TW200910474A/en
Application granted granted Critical
Publication of TWI371807B publication Critical patent/TWI371807B/en

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Description

200910474 九、發明說明： 【發明所屬之技術領域】 本發明之實施例係關於半導體裝置之重分布層及其形成 方法。 以下申請案經交又參考且其全部内容以引用的方式併入 本文中： 與本文在同一日期申請的Andrew Liao等人的題為 "Method of Fabricating a Semiconductor Die Having Redistribution Layer"之美國專利申請案第號[代 理人案號 SAND-0 1257US0]。 【先前技術】 對於攜帶型消費電子設備之需求的強烈增長驅動對於高 容量儲存裝置之需要。諸如快閃記憶體儲存卡之非揮發性 半導體記憶體裝置日益廣泛地用以滿足對數位資訊儲存及 交換之不斷增長之需求。該等非揮發性半導體記憶體裝置 之可攜性、通用性及耐用設計連同其高可靠性及大容量已 使此等記憶體裝置理想地用於包括（例如）數位相機、數位 音樂播放機、視訊遊戲控制台、pDA及蜂巢式電話之廣泛 多種電子裝置中。 儘官已知廣泛多種封裝組態，但大體上可將快閃記憶體 儲存卡製ie為系統級封裝（system_in_a_package, 或多 晶片模組(MCM)’丨中複數個晶粒安裝於及互連於具小佔 據面積之基板上。該基板可大體上包括一具有一在一側或 兩側上被蝕刻之導電層之剛性、介電基底。電連接形成於 132484.doc 200910474 晶粒與該（等）導電層之間’且該（等）導電層提供一用於將 晶粒連接至主機裝置的電引線結構…旦在晶粒與基板之 間進行電連接，則通常接著以模製化合物來包封該總成， 以提供保護性封裝。 在圖it展示習知半導體封裝20(無模製化合物）之俯視 圖。典型封裝包括黏附至基板26之複數個半導體晶粒，諸 如晶粒2 2及2 4。在晶粒製造過程期間可在半導體晶粒2 2、 24上形成複數個晶粒結合襯墊28。類似地，可在基板％上 形成複數個接觸襯墊30。可將晶粒22黏附至基板％，且接 者可將晶粒24安裝於晶粒22上。接著藉由在各別晶粒結合 襯塾28與接觸襯塾30對之間黏附導線結合32來將兩個晶粒 電耦接至基板。 非常需要半導體封裝内之間隔。諸如圖i中之晶粒24上 所展不，半導體晶粒經常係沿著兩個鄰近側與結合襯墊一 起形成。然而，由於顯著之地產限制，在基板上可能僅存 在供沿著晶粒之一邊緣的導線結合連接所用的空間。因 此，在圖1中，不存在沿著基板26之邊緣34的用於與晶粒 結合襯墊28a連接的接觸襯墊。 一處理此情況之已知方法為經由使用形成於半導體晶粒 上之重分布層。在製造一半導體晶粒且將其自晶圓分割 (singulate)後，晶粒可經受在晶粒之頂面上形成導電跡線 及結合襯墊（跡線38及結合襯墊40，圖丨）的過程。一旦跡線 38及結合襯墊28a形成，則可用絕緣體來覆蓋跡線38及結 合襯墊28a，從而僅使新近形成之晶粒結合襯塾4〇暴露。 132484.doc 200910474 跡線38將現有晶粒結合襯墊28a與新近形成之晶粒結合襯 墊40連接以將該等晶粒結合襯墊有效地重定位至具有至美 板之引出腳（pin-out)連接的晶粒之一邊緣。可在基板上形 成額外接觸襯墊30以允許基板與結合襯墊28a之間的電連 接。如圖1之先前技術中所示’該等額外接觸襯墊3〇可與 剩餘之接觸襯墊30成行地形成。或者，在存在可用空間 時’如圖2之先前技術中所示，額外接觸襯^^可 之接觸襯墊交錯。 、200910474 IX. Description of the Invention: TECHNICAL FIELD Embodiments of the present invention relate to a redistribution layer of a semiconductor device and a method of forming the same. The following application is hereby incorporated by reference in its entirety by reference in its entirety in its entirety the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all Case No. [Agent Case No. SAND-0 1257US0]. [Prior Art] The strong growth in demand for portable consumer electronic devices drives the need for high capacity storage devices. Non-volatile semiconductor memory devices such as flash memory cards are increasingly being used to meet the growing demand for digital information storage and exchange. The portability, versatility and robust design of such non-volatile semiconductor memory devices, along with their high reliability and large capacity, have made such memory devices ideal for use, for example, in digital cameras, digital music players, Video game consoles, pDA and cellular phones are available in a wide variety of electronic devices. A wide variety of package configurations are known, but in general the flash memory card can be installed and interconnected in a system-in-package (system_in_a_package, or multi-chip module (MCM)' On a substrate having a small footprint, the substrate can generally comprise a rigid, dielectric substrate having a conductive layer etched on one or both sides. The electrical connection is formed at 132484.doc 200910474. And the conductive layer between the conductive layers and the electrical lead structure for connecting the die to the host device...to be electrically connected between the die and the substrate, usually followed by a molding compound The assembly is encapsulated to provide a protective package. Figure 4 shows a top view of a conventional semiconductor package 20 (moldless compound). A typical package includes a plurality of semiconductor dies adhered to substrate 26, such as die 2 2 and A plurality of die bond pads 28 may be formed over the semiconductor die 2, 24 during the die fabrication process. Similarly, a plurality of contact pads 30 may be formed on the substrate %. Adhesion to substrate% The die 24 can be mounted on the die 22. The two die are then electrically coupled to the substrate by bonding the wire bonds 32 between the respective die bond pads 28 and the pair of contact pads 30. There is a great need for spacing within the semiconductor package. Such as shown on the die 24 in Figure i, the semiconductor die is often formed along with the adjacent pads along the two adjacent sides. However, due to significant real estate limitations, the substrate There may be only space for the wire bond connection along one edge of the die. Thus, in Figure 1, there is no contact liner for the die bond pad 28a along the edge 34 of the substrate 26. A known method of treating this condition is by using a redistribution layer formed on a semiconductor die. After a semiconductor die is fabricated and singulated from the wafer, the die can be subjected to the die A process of forming conductive traces and bonding pads (trace 38 and bond pads 40, top) on the top surface. Once traces 38 and bond pads 28a are formed, the traces 38 and bond pads can be covered with an insulator. 28a, thus only newly formed crystal The lining 4 〇 exposure is exposed. 132484.doc 200910474 Trace 38 connects the existing die bond pad 28a with the newly formed die bond pad 40 to effectively reposition the die bond pads to have a beautiful One of the edges of the die-connected die of the board. An additional contact pad 30 can be formed on the substrate to allow electrical connection between the substrate and the bond pad 28a. As shown in the prior art of FIG. 'These additional contact pads 3' may be formed in line with the remaining contact pads 30. Alternatively, when there is space available, as shown in the prior art of Figure 2, the contact pads of the additional contact pads may be staggered. ,

用於在半導體晶粒上形成重分布層的目前之缝影及其 他方法為繁瑣的，&而對製造過程添加大量方法步驟及費 用。因此，需要用於形成重分布層之流線式方法。 【發明内容】 ，發明之實施例係關於具有重分布層之半導體裝置及其 :成方法。在一實施例令，在晶圓上製造半導體晶粒後， 將-帶總成施加至晶圓之表面上，與晶圓上之每一半導體 :粒之表面接觸。該帶總成包括—作為基底層之背研帶 = 〜)，及點著至該背研帶之膜總成 又包括上面沈積有導電材料之一薄層的黏著膜。 將該帶總成施加至晶圓矣 使得膜總成之黏著層位 至晶圓之b-階黏著劑“至晶圓時’黏著劑為黏著 J但其為柔軟的且可移除。 在將帶總成施加至半導體晶圓之表面後，將聚 2自雷I)施加至帶總成與晶圓之間的界面。雷射絲程 將/、能量聚焦於黏著層與半導體晶圓之表面之；的 132484.doc 200910474 界面處。在沿著界面的施加雷射之位置處，黏著層經加熱 並固化至半導體晶圓之表面，以便沿著被施加熱量的由雷 射描繪之路徑而永久地黏附至半導體晶圓。 ^射之路彳二為爻電腦控制的以便在每一半導體晶粒上描 • 出待界疋於每—半導體晶粒上之重分布層之圖案。藉由選 擇！生地將熱量聚焦於帶總成與晶圓之間的界面處，可使帶 t成之黏著層丨著一細的且清晰地界定之路徑來炫合至每 —半導體晶粒之表面。在由聚焦熱界定之路徑的任一側上 t黏者層保持處於赠或者未經固化，或可自晶圓之表面 2離’而已溶合之彼等區域保留於晶圓表面上。因此，隨 者將帶總成自晶圓拉離，將膜總成之加熱區域自膜總成之 未加熱區域撕扯掉，且將膜總成之加熱區域留在每一半導 體曰曰粒之表面上以在每一半導體晶粒上界定一重分布層圖 案。 【實施方式】 Q 見將參看圖3至圖12來描述本發明之實施例，其係關於 用於半導體裝置之多個晶粒重分布層及其形成方法。應理 解，本發明可以許多不同形式具體化且不應視為限於本文 巾所Μ述之實施例。相反，提供此等實施例，使得本揭示 帛將為詳盡且完整的，且將本發明充分傳達給熟習此項技 術者。當然，本發明意欲涵蓋此等實施例之替代、修改及 等效物，其係包括於如由所附申請專利範圍界定的本發明 之範可及精神内。此外，在本發明之以下詳細描述中，閣 述眾多特定細節以提供對本發明之徹底理解。然而，一般 132484.doc 200910474 熟習此項技術者應清楚，可在無此等特定細節之情況 踐本發明。 現參看圖3 ’展示包括複數個半導體晶粒ι〇2(在圖3中僅 對其中-些進行編號）之半導體晶圓1〇〇的俯視圖。晶圓 1GG上之每-半導體晶粒1G2已經處理以包括如此項技術中 所知的能夠執行指定電子功能的積體電路。晶圓1〇〇上之 戶斤有半導體晶粒102可具有相同之積體電路，但預期在替 A實施例中不同晶粒可具有不同積體電路。如此項技術中 戶斤知’在晶圓製造期間可測試各別積體電路以識別有缺陷 或不良之晶粒。 在晶圓製造測試完成後，即通常將晶粒1〇2中之每一者 分割成個別晶粒且其後將其裝配至半導體封裝中。然而， 根據本發明之一實施例，如下文所解釋，每一半導體晶粒 可具有形成於其上之重分布層。圖3進一步展示包括用於 在晶圓100之各別晶粒1〇2上形成重分布層之帶總成1〇6的 〇 卷筒104。如圖3中所示，帶總成106可具有足以施加於晶 圓1 00之整個表面上的寬度。或者預期帶總成i〇6具有足以 僅覆蓋晶圓100上之單列半導體晶粒102或兩列或兩列以上 . 半導體晶粒102的寬度。 參看圖4之側視圖，帶總成106包括黏附膜總成11 〇的聚 醯亞胺帶1 08 ’如此項技術中所知其被稱作背研帶。如圖$ 中所示’膜總成110包括一上面沈積有一導電材料114之黏 著層116。黏著材料116可為多種已知電絕緣黏著膜中之任 一者’諸如自日本之Nitto Denko公司、加利福尼亞之Abel 132484.doc •10· 200910474Current stitching and other methods for forming redistribution layers on semiconductor dies are cumbersome, and add a large number of method steps and costs to the fabrication process. Therefore, a streamlined method for forming a redistribution layer is needed. SUMMARY OF THE INVENTION Embodiments of the invention relate to a semiconductor device having a redistribution layer and a method of forming the same. In one embodiment, after the semiconductor die is fabricated on the wafer, the tape assembly is applied to the surface of the wafer in contact with the surface of each semiconductor:particle on the wafer. The tape assembly includes - a backing tape as a base layer = ~), and a film assembly that is attached to the back tape and an adhesive film on which a thin layer of a conductive material is deposited. Applying the tape assembly to the wafer 矣 causes the film assembly to adhere to the b-stage adhesive of the wafer. The adhesive to the wafer is adhesive J but it is soft and removable. After the tape assembly is applied to the surface of the semiconductor wafer, the poly 2 is applied to the interface between the tape assembly and the wafer. The laser wire focuses the energy on the surface of the adhesive layer and the semiconductor wafer. 132484.doc 200910474 Interface. At the location where the laser is applied along the interface, the adhesive layer is heated and cured to the surface of the semiconductor wafer to be permanently along the path depicted by the laser to which the heat is applied. The ground is adhered to the semiconductor wafer. The second path is computer controlled to trace the pattern of the redistribution layer on each semiconductor die on each semiconductor die. The ground concentrates the heat at the interface between the tape assembly and the wafer, allowing the adhesive layer of the tape to be dazzled to the surface of each of the semiconductor grains by a thin and clearly defined path. Focusing on the side of the heat-defined path, the t-stick layer remains in the gift They are uncured, or they can remain on the surface of the wafer from the surface of the wafer. Therefore, the tape assembly is pulled away from the wafer to heat the film assembly. The unheated region of the film assembly is torn off, and the heated region of the film assembly is left on the surface of each of the semiconductor particles to define a redistribution layer pattern on each of the semiconductor grains. [Embodiment] Q See Embodiments of the present invention will be described with reference to Figures 3 through 12, which relate to a plurality of grain redistribution layers for semiconductor devices and methods of forming the same. It should be understood that the present invention may be embodied in many different forms and should not be considered The present invention is intended to be limited to the embodiments described herein. The embodiments are provided so that this disclosure will be thorough and complete. The alternatives, modifications, and equivalents of the embodiments are included in the scope of the invention as defined by the appended claims. In the following detailed description of the invention, numerous specific details are described. A thorough understanding of the present invention is provided. However, it is apparent to those skilled in the art that the present invention may be practiced without such specific details. Referring now to Figure 3 'the display includes a plurality of semiconductor grains ι 2 A top view of a semiconductor wafer 1 (only some of which are numbered in Figure 3.) Each semiconductor die 1G2 on wafer 1GG has been processed to include the ability to perform specified electronic functions as is known in the art. Integral circuit. The semiconductor die 102 can have the same integrated circuit, but it is expected that different die can have different integrated circuits in the A embodiment. Jin Zhizhi' can test individual integrated circuits during wafer fabrication to identify defective or defective grains. After the wafer fabrication test is completed, each of the crystal grains 1〇2 is usually divided into individual crystals. The particles are then assembled into a semiconductor package. However, in accordance with an embodiment of the present invention, as explained below, each semiconductor die may have a redistribution layer formed thereon. 3 further shows a crucible 104 including a tape assembly 1〇6 for forming a redistribution layer on the respective die 1〇2 of the wafer 100. As shown in Figure 3, the belt assembly 106 can have a width sufficient to apply to the entire surface of the wafer 100. Alternatively, it is contemplated that the tape assembly i 〇 6 has a width sufficient to cover only a single column of semiconductor dies 102 or two or more columns on the wafer 100. Referring to the side view of Fig. 4, the belt assembly 106 includes a polyimide belt 1 08' of the adhesive film assembly 11 ’ which is known in the art as a backing belt. The film assembly 110, as shown in Figure $, includes an adhesive layer 116 having a conductive material 114 deposited thereon. Adhesive material 116 can be any of a variety of known electrically insulating adhesive films' such as Nitto Denko Corporation of Japan, Abel 132484.doc • 10· 200910474

Stick公司或加利福尼亞之Henkel公司購得之彼等電絕緣黏 著膜。黏著材料116可（例如）為在施加至晶圓】〇〇之前及在 固化之前為有黏性且可彎的可固化b階黏著劑。 導電材料114可為多種電導體，諸如鋁、鈦或其合金。 可藉由多種已知方法將導電材料114施加至黏著層116之表 面，該等方法包括（例如）濺鍍、電鍍、絲網印刷、光微影 方法，或多種其他沈積方法。此等方法允許導電材料114 以非常小之厚度而施加，諸如在丨微米與5微米之間，且更 特定言之在1微米與3微米之間。應理解，在本發明之替代 實施例中，黏著層116上之導電材料114的厚度可小於1微 米且大於5微米。 旦膜總成110形成，則將該膜總成施加至背研帶i 08以 形成帶總成106。帶1〇8亦可具有用於將膜總成11〇之導電 材料114黏著至背研帶108的黏著表面。如圖3、圖4及圖6 中所見，將帶總成1 06施加至半導體晶圓1 〇〇上，使得將帶 總成106之黏著層ι16施加至晶圓1〇〇上之半導體晶粒1〇2的 表面。在黏著層116經施加至半導體晶圓1〇〇的狀態下，黏 著層116為有黏性的且黏著至晶圓1〇〇之表面。然而，黏著 層116尚未固化，且在此階段中，可將黏著層116自晶圓 1〇〇之表面拉離。 在實施例中，在將帶總成！ 〇6施加至晶圓後，可在背研 過程中使背研帶108變薄以使帶總成106變薄。在替代實施 例中，可省略背研過程。 現參看圖6之側視圖，在將帶總成1〇6施加至半導體晶圓 132484.doc 200910474 100之表面後，將聚焦熱施加至帶總成1〇6與晶圓1〇〇之間 的界面（且詳言之，黏著層116與晶圓100之表面之間的界 面）。在實施例中，可藉由多種雷射120中之一者來施加此 聚焦熱，該等雷射包括（例如）C02雷射、uv雷射、YB04 雷射、氬雷射等等。此等雷射（例如）由德國漢堡之Rofin_ Sinar技術公司製造。雷射經程式化以將其能量聚焦於黏著 層116與半導體晶圓1〇〇之表面之間的界面處。在沿著界面 的施加雷射之位置處，黏著層丨16經加熱並固化至半導體 b曰圓之表面，以便沿著被施加熱量的由雷射描繪之路徑而 永久地黏附至半導體晶圓。 雷射之路徑為受電腦控制的以便在每一半導體晶粒1〇2 上描出待界定於每一半導體晶粒1〇2上之重分布層之圖 案。舉例而言，如圖7中所示，可能希望將沿著半導體晶 粒102之頂部邊緣的第一對晶粒結合襯墊124重分布至沿著 半導體晶粒102之鄰近邊緣的一對晶粒結合襯墊126。因 此，如圖7中之虛線所示，雷射12〇將在帶總成1〇6上描出 包括路徑130及132之重分布層圖案。應理解，路徑13〇及 132僅作為實例，且可由雷射12〇描出廣泛多種重分布層圖 案以將晶粒結合襯墊自半導體晶粒1〇2中之每一者上的第 一位置重分布至半導體晶粒1〇2中之每一者上的第二位 置。儘管在圖6中展示了單一雷射12〇，但應理解，可使用 複數個雷射120來在複數個半導體晶粒上同時描出重分布 層圖案。 藉由選擇性地將熱量聚焦於帶總成丨〇 6與晶圓丨〇 〇之間的 132484.doc -12- 200910474 界面處（例如藉由雷射120)，可使帶總成106之黏著層〗16沿 著一細的且清晰地界定之路徑來熔合至每一半導體晶粒 102之表面。值得注意地，在由聚焦熱界定之路徑的任一 側上之黏著層116保持處階或另外未經固化，或可如圖 8所不自晶圓1 〇〇之表面剥離，而已熔合之彼等區域保留於 晶圓表面上。 在帶總成106之未由雷射12〇加熱的彼等區域中，膜總成 110與帶總成106之背研帶108之間的吸引力超過臈總成11〇 G 與半導體晶圓ι〇0之表面之間的吸引力。因此，在剝離背 研帶108後，膜總成11 〇之未加熱區域即與帶總成丨一起 被拉離。相反’對於由雷射加熱之彼等區域而言，膜總成 110與帶108之間的吸引力被膜總成n〇與半導體晶圓1〇〇之 表面之間的吸引力超過。因此，如圖8所示，隨著將帶總 成106自晶圓100拉離，將膜總成110之加熱區域自膜總成 之未加熱區域撕扯掉，且將膜總成之加熱區域留在每一半 ( 導體晶粒102之表面上以在每一半導體晶粒1〇2上界定一重 " 分布層圖案136。 現參看圖9及圖10 ’在自半導體晶圓ι〇〇移除帶總成1〇6 之未固化部分後’將晶圓1〇〇分割成個別半導體晶粒1〇2， 其中各晶粒包括由熱源界定之重分布層圖案136。圖1〇為 經分割之半導體晶粒1 〇2之俯視圖’經分割之半導體晶 粒102包括用於將該晶粒之頂部處的晶粒結合襯墊124重分 布至沿著晶粒之鄰近邊緣的晶粒結合襯墊丨26的重分布層 圖案136。在實施例中’半導體晶粒之表面上的黏著層116 132484.doc -13- 200910474 2電絕緣體。因此，接下來執行將導電材料114電福接至 晶粒結合襯墊124及126的另外步驟。已知有各種方法可用 於將重分布層圖案136之導電材料電麵接至晶粒結合襯塾 124及126。在將圖案電耦接至晶粒結合襯墊及us後， 如所知的可在半導體晶粒102之表面上形成一鈍化層以覆 蓋所露出之重分布層圖案136及(視情況地)覆蓋晶粒結合襯 墊124。晶粒結合襯墊126保持為露出。 圖11說明用於在晶粒102上形成—重分布層之替代方 法。將帶總成106施加至晶圓100,且如上所述，諸如雷射 之熱源在各半導體晶粒102上描出重分布層圖案136。然 而，在圖11所示之實施例中，在施加帶總成1〇6之前或之 後的某時，將半導體晶圓100翻轉且由晶圓夾盤或其類似 物上之帶總成106支撐。根據圖i丨之實施例，分割晶粒丨〇2 但其仍與帶總成1〇6接觸。其後，機器人裝置14〇(諸如， 取放機器人）夾持每一半導體晶粒丨〇 2之背面且將各別晶粒 102自帶總成1〇6拉離。如上所述，將膜總成11〇之已加熱 且熔合至各別半導體晶粒102之表面的彼等區域自背研帶 108撕扯掉，且當機器人裝置14〇將經分割之晶粒ι〇2自帶 總成106拉離時，彼等區域維持與半導體晶粒i 〇2接觸。膜 總成11〇之未加熱部分保留於晶圓夾盤上於帶總成1〇6上。 應理解，使用上述重分布層方法步驟，可藉由跨越於晶 圓級處形成之晶粒的重分布層將一或多個晶粒結合襯墊自 半導體晶粒102上之任何第一位置重分布至任何第二位 置。現參看圖12，在上述步驟完成時，可將晶粒1〇2安裝 132484.doc • 14· 200910474 於基板160上。晶粒1〇2可為安裝於基板ι6〇上之唯一晶 粒，或如圖12所示，晶粒1〇2可連同一或多個額外晶粒162 及被動組件164—起安裝於基板16〇上。其後，可以已知導 線結合方法使用導線結合166來將晶粒1〇2及任何其他晶粒 上之晶粒結合襯墊導線結合至基板160上之接觸襯墊。在 實施例中，晶粒及基板一起可充當快閃記憶體裝置17〇 , 其中晶粒102可為控制器（諸如ASIC)或快閃記憶體晶粒。They have their electrically insulating adhesive films available from Stick or California's Henkel. Adhesive material 116 can be, for example, a viscous and bendable curable b-stage adhesive prior to application to the wafer and prior to curing. Conductive material 114 can be a variety of electrical conductors such as aluminum, titanium, or alloys thereof. Conductive material 114 can be applied to the surface of adhesive layer 116 by a variety of known methods including, for example, sputtering, electroplating, screen printing, photolithography, or a variety of other deposition methods. These methods allow the conductive material 114 to be applied in very small thicknesses, such as between 丨 microns and 5 microns, and more specifically between 1 and 3 microns. It should be understood that in alternative embodiments of the invention, the thickness of the electrically conductive material 114 on the adhesive layer 116 can be less than 1 micrometer and greater than 5 microns. Once the film assembly 110 is formed, the film assembly is applied to the backing tape i 08 to form the tape assembly 106. The belt 1 〇 8 may also have an adhesive surface for adhering the conductive material 114 of the film assembly to the backing tape 108. As seen in Figures 3, 4 and 6, the tape assembly 106 is applied to the semiconductor wafer 1 such that the adhesive layer ι 16 of the tape assembly 106 is applied to the semiconductor die on the wafer 1 1 〇 2 surface. In a state where the adhesive layer 116 is applied to the semiconductor wafer 1 , the adhesive layer 116 is viscous and adheres to the surface of the wafer 1 . However, the adhesive layer 116 has not yet cured, and at this stage, the adhesive layer 116 can be pulled away from the surface of the wafer. In an embodiment, the belt assembly will be in place! After the crucible 6 is applied to the wafer, the backing tape 108 can be thinned during the back grinding process to thin the tape assembly 106. In an alternative embodiment, the back grinding process can be omitted. Referring now to the side view of FIG. 6, after applying the tape assembly 1〇6 to the surface of the semiconductor wafer 132484.doc 200910474 100, focus heat is applied between the tape assembly 1〇6 and the wafer 1〇〇. Interface (and in particular, the interface between the adhesive layer 116 and the surface of the wafer 100). In an embodiment, the focused heat may be applied by one of a plurality of lasers 120 including, for example, a CO 2 laser, a uv laser, a YB04 laser, an argon laser, and the like. Such lasers are for example manufactured by Rofin_ Sinar Technologies, Hamburg, Germany. The laser is programmed to focus its energy at the interface between the adhesive layer 116 and the surface of the semiconductor wafer. At the location where the laser is applied along the interface, the adhesive layer 16 is heated and cured to the surface of the semiconductor b-circle to permanently adhere to the semiconductor wafer along the path of the laser-drawn heat applied. The path of the laser is computer controlled to trace the pattern of redistribution layers to be defined on each of the semiconductor dies 1 在 2 on each of the semiconductor dies 1 〇 2 . For example, as shown in FIG. 7, it may be desirable to redistribute a first pair of die bond pads 124 along the top edge of semiconductor die 102 to a pair of die along adjacent edges of semiconductor die 102. The pad 126 is bonded. Therefore, as shown by the dashed line in Fig. 7, the laser 12 〇 will trace the redistribution layer pattern including the paths 130 and 132 on the belt assembly 1 〇 6. It should be understood that the paths 13A and 132 are merely examples, and a wide variety of redistribution layer patterns may be traced by the laser 12 to weight the die bond pads from the first location on each of the semiconductor die 1〇2 Distributed to a second location on each of the semiconductor dies 1 〇 2 . Although a single laser 12 展示 is shown in Figure 6, it should be understood that a plurality of lasers 120 can be used to simultaneously pattern the redistribution layer pattern across a plurality of semiconductor dies. The tape assembly 106 can be adhered by selectively focusing heat at the 132484.doc -12-200910474 interface between the tape assembly 与6 and the wafer cassette (e.g., by laser 120). Layer 16 is fused to the surface of each semiconductor die 102 along a thin and clearly defined path. Notably, the adhesive layer 116 on either side of the path defined by the focus heat remains at the step or otherwise uncured, or may not be peeled off from the surface of the wafer 1 as shown in Figure 8, but has been fused The area remains on the wafer surface. In those regions of the belt assembly 106 that are not heated by the laser 12 ,, the attraction between the film assembly 110 and the backing strip 108 of the belt assembly 106 exceeds the 臈 assembly 11 〇 G and the semiconductor wafer ι The attraction between the surfaces of 〇0. Therefore, after the backing tape 108 is peeled off, the unheated region of the film assembly 11 is pulled away together with the belt assembly. Conversely, for the regions heated by the laser, the attractive force between the film assembly 110 and the belt 108 is exceeded by the attraction between the film assembly n〇 and the surface of the semiconductor wafer 1〇〇. Thus, as shown in FIG. 8, as the tape assembly 106 is pulled away from the wafer 100, the heated region of the film assembly 110 is torn from the unheated region of the film assembly and the heated region of the film assembly is left On each surface (the surface of the conductor die 102 to define a " distribution layer pattern 136 on each semiconductor die 1〇2. Referring now to Figures 9 and 10, the tape is removed from the semiconductor wafer. After the uncured portion of the assembly 1〇6, the wafer 1〇〇 is divided into individual semiconductor grains 1〇2, wherein each of the crystal grains includes a redistribution layer pattern 136 defined by a heat source. FIG. 1 is a divided semiconductor. Top view of the die 1 〇 2 'The split semiconductor die 102 includes a die bond pad 26 for redistributing the die bond pads 124 at the top of the die to adjacent edges along the die The redistribution layer pattern 136. In the embodiment, the adhesive layer 116 132484.doc -13 - 200910474 2 on the surface of the semiconductor die is electrically insulated. Therefore, the conductive material 114 is subsequently electrically connected to the die bond liner. Additional steps of pads 124 and 126. Various methods are known for redistribution The conductive material of layer pattern 136 is electrically connected to die bond pads 124 and 126. After the pattern is electrically coupled to the die bond pads and us, a surface can be formed on the surface of semiconductor die 102 as is known. The passivation layer covers the exposed redistribution layer pattern 136 and (optionally) the die bond pad 124. The die bond pad 126 remains exposed. Figure 11 illustrates the formation of redistribution on the die 102. An alternative method of the layer. The tape assembly 106 is applied to the wafer 100, and as described above, a heat source such as a laser traces the redistribution layer pattern 136 on each of the semiconductor dies 102. However, the embodiment shown in FIG. At some point before or after the application of the tape assembly 1〇6, the semiconductor wafer 100 is flipped over and supported by the tape assembly 106 on the wafer chuck or the like. According to the embodiment of the figure, the segmentation The die 丨〇 2 is still in contact with the tape assembly 1 。 6. Thereafter, a robotic device 14 (such as a pick-and-place robot) holds the back side of each of the semiconductor dies 2 and separates the respective dies 102. Pull the self-contained assembly 1〇6. As described above, the film assembly 11〇 is heated and fused to each The regions of the surface of the semiconductor die 102 are torn from the backing tape 108, and when the robotic device 14 pulls the divided die ι 2 from the tape assembly 106, the regions remain with the semiconductor die i 〇 2 contact. The unheated portion of the film assembly 11 保留 remains on the wafer chuck on the tape assembly 1 〇 6. It should be understood that the above-described redistribution layer method step can be used across the wafer level The redistribution layer of the formed die redistributes one or more die bond pads from any first location on the semiconductor die 102 to any second location. Referring now to Figure 12, upon completion of the above steps, The die 1〇2 is mounted 132484.doc • 14·200910474 on the substrate 160. The die 1〇2 may be the only die mounted on the substrate ι6〇, or as shown in FIG. 12, the die 1〇2 may be connected to the substrate 16 by the same or a plurality of additional dies 162 and passive components 164. 〇上. Thereafter, wire bonding 166 can be used to bond the die bond wires of the die 1 〇 2 and any other die to the contact pads on the substrate 160 using wire bonding 166. In an embodiment, the die and the substrate together can function as a flash memory device 17 , wherein the die 102 can be a controller (such as an ASIC) or a flash memory die.

在替代實施例巾，晶粒1〇2可不同於控制器或快閃記憶體 晶粒’且在替代實施例中，該晶粒及該基板—起可不同於 一快閃記憶體裝置。在快閃記憶體裝置17〇為攜帶型記憶 體裝置的實施例巾，可在基板16m步提供接觸指狀 物168以用於在裝置17〇與裝置17〇所插入於之主機裝置之 間交換信號。 v 如本發明之先前技術中所解釋，在-些封裝組態中，存 在用於僅著半導體晶粒之單—邊緣的引出腳位置的空 間。施加至半導體晶粒1()2之重分布層有效地將晶粒⑽之 表面上的結合襯塾重分布至其可容易地結合至基板160的 位置K 12中所示之半導體晶粒1〇2、半導體晶粒⑹及基 板160的相對長度及相對寬度僅作為實例且在本發明之替 代實施例中可廣泛地變化。 ^圖2所不，在形成根據上述實施例之堆疊晶粒組態 後可將個別半導體封裝包封於模製化合物1 68内以形成 完成之半導體晶粒封裝17〇。模製化合物168可為（諸如）可 自U均设於日本之Sumit_公司及Nitt。Denk。公司購得 132484.doc 15 200910474 。圖12所示之封裝17〇可為完成之攜帶型 可將封裝1 7 0包封於一蓋内以形成該完成 已為了達成說明及描述之目的而呈現本發明之前述詳細 描述。其並不意欲為詳盡的或將本發日月限於所揭示之精確 形式。依據上述教示，許多修改及變化&可能㈣。選擇所 描述之實施例以便最佳地解釋本發明之原理及其實踐應In an alternative embodiment, the die 1 2 may be different from the controller or flash memory die' and in an alternative embodiment, the die and the substrate may be different than a flash memory device. In the embodiment of the flash memory device 17 being a portable memory device, contact fingers 168 may be provided on the substrate 16m for exchange between the device 17 and the host device into which the device 17 is inserted. signal. v As explained in the prior art of the present invention, in some package configurations, there is room for the pin-out position of the single-edge of only the semiconductor die. The redistribution layer applied to the semiconductor die 1(2) effectively redistributes the bonding underlayer on the surface of the die (10) to the semiconductor die 1 shown in the position K12 at which it can be easily bonded to the substrate 160. 2. The relative lengths and relative widths of the semiconductor die (6) and substrate 160 are merely examples and may vary widely in alternative embodiments of the invention. 2, after forming the stacked die configuration according to the above embodiment, individual semiconductor packages can be encapsulated in molding compound 168 to form a completed semiconductor die package 17A. Molding compound 168 can be, for example, Sumit Corporation and Nitt, both of which are available from Japan. Denk. The company purchased 132484.doc 15 200910474. The package 17 shown in Figure 12 can be a completed carrier. The package 170 can be enclosed in a cover to form the finish. The foregoing detailed description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the scope of the present invention to the precise form disclosed. Many modifications and variations are possible (4) in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and its practice.

用’以藉此使得其他熟習此項技術者能夠在各種實施例中一 最佳地利用本發明並以適於所涵蓋之特定用途的各種修改 來最佳地利用本發明。本發明之範疇意欲由附加至此之申 請專利範圍界定。 【圖式簡單說明】 圖1為包括一半導體晶粒之習知半導體封裝的俯視圖， 該半導體晶粒具有一將晶粒結合襯墊自該晶粒之一第一邊 緣重分布至一第二邊緣的重分布層。 ti 的已知環氧樹脂 記憶卡。或者， 之攜帶型記憶卡 圖2為具有替代基板接觸襯墊配置的包括具有如圖1中之 重分布層的晶粒的習知半導體封裝之俯視圖。 圖3為根據本發明之實施例的由來自一卷筒之帶總成覆 蓋的半導體晶圓的透視圖。 圖4為根據本發明之實施例的置放於半導體晶圓之半導 體晶粒上方的帶總成之側視圖。 圖5為根據本發明之實施例的包括一黏著層及導電材料 之膜總成的側視圖。 圖ό為黏附至半導體晶圓之半導體晶粒之帶總成的且進 132484.doc -16- 200910474 圖案的雷射 一步包括一描繪至該帶總成之表面中之重分布 的側視圖。 圖7為帶總成位於上面且重分布層_帛係、 帶總成中的半導體晶粒的俯視圖。 、田 圖8為自半導體晶圓移除帶總成留下由雷 布層圖案的側視圖。 刀 圖9展示自晶圓分割之複數個半導體晶粒。 圖⑺為包括根據本發明之實施例形成之重分 _ 割晶粒之俯視圖。 《的經分 圖11為將半導體晶粒與新的帶總成分離之替 視圖。 法的侧 =12為包括具有根據本發明之實施例形成之重 導體晶粒的半導體封裝之橫載面側視圖。 < 【主要元件符號說明】 20 半導體封裝 22 晶粒 24 晶粒 26 基板 28 晶粒結合概塾 28a 晶粒結合襯塾 30 接觸襯塾 32 導線結合 34 邊緣 38 跡線 132484.doc 晶粒結合襯墊 半導體晶圓 半導體晶粒 卷筒 帶總成 聚醯亞胺帶/背研帶 膜總成 導電材料 黏著層/黏著材料 雷射 晶粒結合襯墊 晶粒結合襯墊 路徑 路徑 重分布層圖案 機器人裝置 基板 半導體晶粒 被動組件 接觸指狀物/模製化合物 快閃記憶體裝置/半導體晶粒封裝 -18-The present invention may be utilized to advantage of the various embodiments of the present invention in the various embodiments. The scope of the invention is intended to be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top plan view of a conventional semiconductor package including a semiconductor die having a die bond pad re-distributed from a first edge of the die to a second edge Redistribution layer. Known epoxy resin memory card for ti. Alternatively, a portable memory card Figure 2 is a top plan view of a conventional semiconductor package including a die having a redistribution layer as in Figure 1 in an alternative substrate contact pad configuration. 3 is a perspective view of a semiconductor wafer covered by a tape assembly from a reel, in accordance with an embodiment of the present invention. 4 is a side elevational view of a tape assembly disposed over a semiconductor die of a semiconductor wafer in accordance with an embodiment of the present invention. Figure 5 is a side elevational view of a film assembly including an adhesive layer and a conductive material in accordance with an embodiment of the present invention. Figure 1 is a side view of a laser beam attached to a semiconductor die of a semiconductor wafer and having a pattern of 132484.doc -16 - 200910474 pattern including a redistribution of the redistribution into the surface of the tape assembly. Figure 7 is a top plan view of a semiconductor die with a tape assembly located above and in a redistribution layer, a lanthanide, tape assembly. Figure 8 is a side view of the strip removed from the semiconductor wafer removal strip assembly. Knife Figure 9 shows a plurality of semiconductor dies divided from a wafer. Figure (7) is a top plan view of a heavily-divided die formed in accordance with an embodiment of the present invention. Figure 11 is an alternative view of separating the semiconductor die from the new tape assembly. Side = 12 of the method is a side view of a cross-sectional surface of a semiconductor package including a conductor die formed in accordance with an embodiment of the present invention. < [Major component symbol description] 20 Semiconductor package 22 Die 24 Grain 26 Substrate 28 Die bonding 28a Grain bonded lining 30 Contact lining 32 Wire bonding 34 Edge 38 Trace 132484.doc Grain lining Pad semiconductor wafer semiconductor die reel tape assembly polyimine tape / back tape film assembly conductive material adhesive layer / adhesive material laser grain bonding pad die bonding pad path path redistribution layer pattern robot Device substrate semiconductor die passive component contact finger / molding compound flash memory device / semiconductor die package -18-

Claims (1)

200910474 十、申請專利範圍： 1· 一種自—半導體晶圓製造一半導體封裝之方法，該半導 體封裝包括-具有一重分布層之半導體晶粒，該方法包 含以下步驟： 匕 (a) 將一帶總成施加於該半導體晶圓之至少部分上，該 帶總成包括一帶、一黏著層及施加至該黏著層之導 電材料，該黏著層位於與該半導體晶圓鄰近處； Γ (b) 以一在該半導體晶粒之一晶粒結合襯墊之一第—位 置與重分布有該晶粒結合襯墊之—第二位置之間界 定—路徑的圖案而將該黏著層之部分黏著至該半導 體晶圓上之該半導體晶粒的一表面；及 ⑷移除該帶總成之部分’留下黏著至該半導體晶圓的 在該步驟（b)中界定之該黏著層之該圖案及施加至在 #步驟〇^中界定的該黏著層之該圖案的該導電材 料。 2’如明求項1之方法，其中將該黏著層之部分黏著至該半 :體晶粒之-表面的該步驟(b)包含沿著該在該第一位置 二二位置之間界定該路徑的圖案來加熱該黏著層與 導體晶粒之該表面之間的一界面的步驟。 3.如請求項2之方法，其中沪荖太吁埜y β 丹甲&者在该第一位置與該第二位 粒之^界疋該路徑的圖案來加熱該黏著層與該半導體晶 :::表面之間的一界面的該步驟包含用-雷射來加熱 該界面的步驟。 4· 如請求項1 法’其中移除該帶總成之部分的該步驟 132484.doc 200910474 (C)包含拉離該帶的步驟。 5·如請求項4之方法’其中移除該帶總成 ⑷進一步包含與該帶—起拉離在該步驟^❹驟 半導體晶粒之表面的該導電材料及該點著二:至一 驟。 部有層的部分的步 6.如請求項1之方法，发中移降哕罄婢孑 ⑷包人白h本、中移除該帶、‘成之部分的該步驟 ⑷包3自在該步驟（b)中未黏著至—半導 Γ 該黏著層之部分切斷在該步驟⑻中黏著至二= 之表面的該黏著層之部分的步驟。 曰曰 7·如請求項1之方法，其 總成： / L 3由以下步驟形成該帶 (句將該導電材料沈積於該黏著層上；及 ⑷將該黏著層及該導電材料施加至該帶。 8 項1之方法’其進一步包含將第-晶粒結合襯墊 驟⑺。至在該步驟⑷中留下之該導電材料之一末端的步 9·如請求項8之方法，Α ^ 去其進一步包含將在該步驟（c)_留下 之該導電材料的-第二末端電麵接至在該第二位置處之 第—晶粒結合襯墊的步驟（g)。 A长項1之n其進—步包含在該移除該帶總成之 p刀的步驟（e)後自該半導體晶圓分㈣半導體晶粒 驟（h)。 11. 一種半導體晶粒，其包含： 一積體電路；及 132484.doc 200910474 一形成於該積體電路上方之重分布圖案，該重分布圖 案包括： 一黏著材料，其以該重分布圖案之一圖案來黏著至 該半導體晶粒之一表面，及 沈積於該黏著材料上之導電材料。 12.如凊求項η之半導體晶粒，其中該導電材料為欽及結中 之至少一者。200910474 X. Patent application scope: 1. A method for manufacturing a semiconductor package from a semiconductor wafer, the semiconductor package comprising: a semiconductor die having a redistribution layer, the method comprising the steps of: 匕 (a) a tape assembly Applied to at least a portion of the semiconductor wafer, the tape assembly includes a tape, an adhesive layer, and a conductive material applied to the adhesive layer, the adhesive layer being located adjacent to the semiconductor wafer; Γ (b) One of the die-bonding pads of the semiconductor die is bonded to the semiconductor crystal by a pattern of a path defined between the die-bonding pad and the second position of the die-bonding pad a portion of the semiconductor die on the circle; and (4) removing the portion of the tape assembly - leaving the pattern adhered to the adhesive layer of the semiconductor wafer defined in the step (b) and applied to The conductive material of the pattern of the adhesive layer defined in #step〇. The method of claim 1, wherein the bonding of the portion of the adhesive layer to the half: the step (b) of the surface of the body grain comprises defining the relationship between the two positions along the first position A pattern of paths to heat an interface between the adhesive layer and the surface of the conductor die. 3. The method of claim 2, wherein the 荖 荖 野 野 y β 丹 甲 & at the first position and the second granule 疋 the pattern of the path to heat the adhesive layer and the semiconductor crystal The step of:: an interface between the surfaces comprises the step of heating the interface with a laser. 4. The step of claim 1 method in which the portion of the belt assembly is removed 132484.doc 200910474 (C) includes the step of pulling the belt away. 5. The method of claim 4, wherein removing the tape assembly (4) further comprises pulling the conductive material away from the tape at the surface of the semiconductor die and the point is two to one step . Step 6 of the layered portion, as in the method of claim 1, the transfer in the middle (4) of the package, the removal of the strip, the step of forming the portion (4), the package 3 is in this step. (b) is not adhered to - semi-conductive 部分 The portion of the adhesive layer cuts off the portion of the adhesive layer adhered to the surface of the second surface in the step (8).曰曰7. The method of claim 1, the assembly: / L 3 forming the strip by the following steps (the sentence is deposited on the adhesive layer; and (4) applying the adhesive layer and the conductive material to the The method of claim 1 further comprising the step of bonding the first die to the pad (7). To the end of one of the conductive materials left in the step (4), as in the method of claim 8, Α ^ And further comprising the step (g) of electrically connecting the second end of the conductive material left in the step (c) to the first die bond pad at the second position. The step of including the step (e) of removing the p-knife of the tape assembly comprises (4) semiconductor die (h) from the semiconductor wafer. 11. A semiconductor die comprising: An integrated circuit; and 132484.doc 200910474 a redistribution pattern formed over the integrated circuit, the redistribution pattern comprising: an adhesive material adhered to the semiconductor die in a pattern of the redistribution pattern a surface, and a conductive material deposited on the adhesive material. The semiconductor die of η items, wherein the conductive material is Chin and at least one of the junction. 如晴求項11之半導體晶粒’其巾該㈣材料在該黏著材 料上具有在1微米與5微米之間的一厚度。 ^晴求項11之半導體晶粒’其巾料電材料在該黏著材 料上具有在1微米與3微米之間的一厚度。 13. 14. 15. 如請求項1丨之半導體晶粒， 該重分布圖案之該圖案來加 重分布圖案之該圖案來黏著 16. 如請求項丨丨之半導體晶粒， 憶體電路。 如請求項丨丨之半導體晶粒， 快閃記憶體之控制器電路。 其中該黏著材料係藉由一以 熱該黏著材料的雷射而以該 至該半導體晶粒之該表面。 其中該積體電路為一快閃纪 其中該積體電路為一用於 132484.docThe semiconductor wafer of the item 11 has a thickness of between 1 μm and 5 μm on the adhesive material. The semiconductor die of the invention 11 has a thickness of between 1 micrometer and 3 micrometers on the adhesive material. 13. 14. 15. In the case of the semiconductor die of claim 1, the pattern of the redistribution pattern is applied to the pattern of the distribution pattern to be adhered. 16. The semiconductor die of the claim ,, the memory circuit. For example, the semiconductor die of the request item, the controller circuit of the flash memory. Wherein the adhesive material is applied to the surface of the semiconductor die by a laser that heats the adhesive material. Wherein the integrated circuit is a flash circuit, wherein the integrated circuit is used for one of 132484.doc
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