WO2009006284A2 - Dé semi-conducteur doté d'une couche de redistribution - Google Patents

Dé semi-conducteur doté d'une couche de redistribution Download PDF

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Publication number
WO2009006284A2
WO2009006284A2 PCT/US2008/068542 US2008068542W WO2009006284A2 WO 2009006284 A2 WO2009006284 A2 WO 2009006284A2 US 2008068542 W US2008068542 W US 2008068542W WO 2009006284 A2 WO2009006284 A2 WO 2009006284A2
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WO
WIPO (PCT)
Prior art keywords
semiconductor die
die
recited
adhesive layer
semiconductor
Prior art date
Application number
PCT/US2008/068542
Other languages
English (en)
Other versions
WO2009006284A3 (fr
Inventor
Chien-Ko Liao
Chin-Tien Chiu
Jack Chang Chien
Cheemen Yu
Hem Takiar
Original Assignee
Sandisk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/769,927 external-priority patent/US7772047B2/en
Priority claimed from US11/769,937 external-priority patent/US7763980B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Priority to EP08796037.3A priority Critical patent/EP2179442A4/fr
Priority to CN2008800224541A priority patent/CN101765911B/zh
Publication of WO2009006284A2 publication Critical patent/WO2009006284A2/fr
Publication of WO2009006284A3 publication Critical patent/WO2009006284A3/fr

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    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

La présente invention a trait à un dispositif à semi-conducteur doté d'une couche de redistribution et à ses procédés de formation. Après la fabrication d'un dé semi-conducteur sur une tranche, un assemblage de bande est appliqué sur une surface de la tranche, en contact avec les surfaces de chaque dé semi-conducteur sur la tranche. L'assemblage de bande inclut une bande d'affûtage arrière en tant que couche de base et un assemblage de film collé à la bande d'affûtage arrière. L'assemblage de film inclut à son tour un film adhésif sur lequel est déposée une couche mince de matériau conducteur. Le motif de la couche de redistribution est tracé dans l'assemblage de bande, à l'aide par exemple d'un laser. Par la suite, les parties non chauffées de l'assemblage de bande peuvent être supprimées, ce qui laisse le motif de la couche de redistribution chauffé sur chaque dé semi-conducteur.
PCT/US2008/068542 2007-06-28 2008-06-27 Dé semi-conducteur doté d'une couche de redistribution WO2009006284A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP08796037.3A EP2179442A4 (fr) 2007-06-28 2008-06-27 Dé semi-conducteur doté d'une couche de redistribution
CN2008800224541A CN101765911B (zh) 2007-06-28 2008-06-27 具有重新分布层的半导体芯片

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/769,927 US7772047B2 (en) 2007-06-28 2007-06-28 Method of fabricating a semiconductor die having a redistribution layer
US11/769,927 2007-06-28
US11/769,937 2007-06-28
US11/769,937 US7763980B2 (en) 2007-06-28 2007-06-28 Semiconductor die having a distribution layer

Publications (2)

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WO2009006284A2 true WO2009006284A2 (fr) 2009-01-08
WO2009006284A3 WO2009006284A3 (fr) 2009-04-09

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EP (1) EP2179442A4 (fr)
KR (1) KR101475467B1 (fr)
CN (1) CN101765911B (fr)
TW (1) TWI371807B (fr)
WO (1) WO2009006284A2 (fr)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015127486A1 (fr) * 2014-02-28 2015-09-03 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé de fabrication d'un circuit imprimé à puce de capteur incorporée ainsi que circuit imprimé
WO2015138359A1 (fr) * 2014-03-10 2015-09-17 Deca Technologies Inc. Dispositif semi-conducteur et procédé comprenant des couches de redistribution épaissies
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US9887103B2 (en) 2010-02-16 2018-02-06 Deca Technologies, Inc. Semiconductor device and method of adaptive patterning for panelized packaging
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10672624B2 (en) 2011-12-30 2020-06-02 Deca Technologies Inc. Method of making fully molded peripheral package on package device
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106469657B (zh) * 2015-08-14 2020-03-31 晟碟半导体（上海）有限公司 具有间隔体层的半导体装置、其形成方法和间隔体层带

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011314A (en) * 1999-02-01 2000-01-04 Hewlett-Packard Company Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
US6706557B2 (en) * 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US6897096B2 (en) * 2002-08-15 2005-05-24 Micron Technology, Inc. Method of packaging semiconductor dice employing at least one redistribution layer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN87107692A (zh) * 1986-11-13 1988-05-25 Mt化学公司 半导体器件的制造方法
US6036809A (en) * 1999-02-16 2000-03-14 International Business Machines Corporation Process for releasing a thin-film structure from a substrate
JP2001323228A (ja) * 2000-05-15 2001-11-22 Nitto Denko Corp 加熱剥離型粘着シート
JP2002076576A (ja) * 2000-08-23 2002-03-15 Nec Corp 配線パターン形成方法およびその方法に用いられる原版
JP2005085799A (ja) * 2003-09-04 2005-03-31 Seiko Epson Corp 成膜方法、配線パターンの形成方法、半導体装置の製造方法、電気光学装置、及び電子機器
US7410825B2 (en) * 2005-09-15 2008-08-12 Eastman Kodak Company Metal and electronically conductive polymer transfer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011314A (en) * 1999-02-01 2000-01-04 Hewlett-Packard Company Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
US6706557B2 (en) * 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
US6897096B2 (en) * 2002-08-15 2005-05-24 Micron Technology, Inc. Method of packaging semiconductor dice employing at least one redistribution layer
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2179442A2 *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9887103B2 (en) 2010-02-16 2018-02-06 Deca Technologies, Inc. Semiconductor device and method of adaptive patterning for panelized packaging
US10373870B2 (en) 2010-02-16 2019-08-06 Deca Technologies Inc. Semiconductor device and method of packaging
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
US9831170B2 (en) 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US9177926B2 (en) 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US10373902B2 (en) 2011-12-30 2019-08-06 Deca Technologies Inc. Fully molded miniaturized semiconductor module
US10672624B2 (en) 2011-12-30 2020-06-02 Deca Technologies Inc. Method of making fully molded peripheral package on package device
WO2015127486A1 (fr) * 2014-02-28 2015-09-03 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé de fabrication d'un circuit imprimé à puce de capteur incorporée ainsi que circuit imprimé
WO2015138359A1 (fr) * 2014-03-10 2015-09-17 Deca Technologies Inc. Dispositif semi-conducteur et procédé comprenant des couches de redistribution épaissies
US10050004B2 (en) 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects

Also Published As

Publication number Publication date
CN101765911B (zh) 2012-06-27
TWI371807B (en) 2012-09-01
WO2009006284A3 (fr) 2009-04-09
EP2179442A2 (fr) 2010-04-28
CN101765911A (zh) 2010-06-30
TW200910474A (en) 2009-03-01
KR20100034756A (ko) 2010-04-01
KR101475467B1 (ko) 2014-12-22
EP2179442A4 (fr) 2013-08-07

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