WO2008157084A1 - Activation de puce et adresse de puce programmables dans une mémoire à semi-conducteurs - Google Patents

Activation de puce et adresse de puce programmables dans une mémoire à semi-conducteurs Download PDF

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Publication number
WO2008157084A1
WO2008157084A1 PCT/US2008/066111 US2008066111W WO2008157084A1 WO 2008157084 A1 WO2008157084 A1 WO 2008157084A1 US 2008066111 W US2008066111 W US 2008066111W WO 2008157084 A1 WO2008157084 A1 WO 2008157084A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
memory
address
programmable circuits
memory chip
Prior art date
Application number
PCT/US2008/066111
Other languages
English (en)
Inventor
Loc Tu
Jian Chen
Alex Mak
Tien-Chien Kuo
Pham Long
Original Assignee
Sandisk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/763,287 external-priority patent/US7715255B2/en
Priority claimed from US11/763,292 external-priority patent/US7477545B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Priority to CN200880025636.4A priority Critical patent/CN101779249B/zh
Priority to KR1020107000810A priority patent/KR101440568B1/ko
Publication of WO2008157084A1 publication Critical patent/WO2008157084A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G11C29/886—Masking faults in memories by using spares or by reconfiguring with partially good memories combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Les matrices de mémoire sont pourvues d'éléments de circuit d'activation de puce programmables pour permettre la désactivation d'une puce de mémoire particulière après son conditionnement et/ou d'éléments de circuit d'adressage de puce programmables pour permettre le réadressage d'une matrice de mémoire particulière après son conditionnement. Dans un boîtier de mémoire multipuce, une matrice de mémoire qui échoue aux tests au niveau du boîtier peut être désactivée et isolée du boîtier de mémoire par un circuit programmable qui outrepasse le signal d'activation de puce maître reçu du contrôleur ou du dispositif hôte. Pour fournir une plage d'adresses continue, une ou plusieurs des matrices de mémoire non défectueuses peuvent être réadressées en utilisant un autre circuit programmable qui remplace l'adresse de puce unique fournie par les pastilles de connexion. Les puces de mémoire peuvent également être réadressées après leur conditionnement indépendamment de la détection d'une matrice de mémoire défaillante.
PCT/US2008/066111 2007-06-14 2008-06-06 Activation de puce et adresse de puce programmables dans une mémoire à semi-conducteurs WO2008157084A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200880025636.4A CN101779249B (zh) 2007-06-14 2008-06-06 半导体存储器中的可编程芯片使能和芯片地址
KR1020107000810A KR101440568B1 (ko) 2007-06-14 2008-06-06 반도체 메모리의 프로그램가능한 칩 인에이블 및 칩 어드레스

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/763,287 2007-06-14
US11/763,287 US7715255B2 (en) 2007-06-14 2007-06-14 Programmable chip enable and chip address in semiconductor memory
US11/763,292 2007-06-14
US11/763,292 US7477545B2 (en) 2007-06-14 2007-06-14 Systems for programmable chip enable and chip address in semiconductor memory

Publications (1)

Publication Number Publication Date
WO2008157084A1 true WO2008157084A1 (fr) 2008-12-24

Family

ID=40156586

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/066111 WO2008157084A1 (fr) 2007-06-14 2008-06-06 Activation de puce et adresse de puce programmables dans une mémoire à semi-conducteurs

Country Status (4)

Country Link
KR (1) KR101440568B1 (fr)
CN (1) CN101779249B (fr)
TW (1) TWI380165B (fr)
WO (1) WO2008157084A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021045799A1 (fr) * 2019-09-03 2021-03-11 Silicon Storage Technology, Inc. Procédé d'amélioration de la stabilité de courant de lecture dans une mémoire non volatile analogique au moyen d'une cuisson finale dans un état de programme prédéterminé

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KR101124331B1 (ko) 2010-04-30 2012-03-19 주식회사 하이닉스반도체 반도체 장치
KR101223540B1 (ko) 2011-01-14 2013-01-21 에스케이하이닉스 주식회사 반도체 장치, 그의 칩 아이디 부여 방법 및 그의 설정 방법
KR101178563B1 (ko) 2011-02-28 2012-08-31 에스케이하이닉스 주식회사 불휘발성 메모리 장치 및 그 동작방법
CN102543189A (zh) * 2012-02-28 2012-07-04 北京忆恒创源科技有限公司 半导体存储器、接口电路及其访问方法
KR20140008550A (ko) 2012-07-05 2014-01-22 에스케이하이닉스 주식회사 멀티 칩 패키지 메모리 장치의 제어 방법
JP2014082245A (ja) * 2012-10-15 2014-05-08 J Devices:Kk 半導体記憶装置及びその製造方法
CN105989899B (zh) * 2015-03-05 2019-04-02 旺宏电子股份有限公司 存储器修补方法及其应用元件
KR20180067846A (ko) * 2016-12-13 2018-06-21 에스케이하이닉스 주식회사 반도체 장치 및 그의 동작 방법
CN106844266B (zh) * 2017-02-06 2020-01-14 京信通信系统（中国）有限公司 一种硬件地址编址电路及其制作、使用方法
KR20190041071A (ko) 2017-10-12 2019-04-22 에스케이하이닉스 주식회사 메모리 칩, 이를 포함하는 패키지 장치 및 이의 동작 방법
CN110892483B (zh) * 2019-10-17 2021-01-29 长江存储科技有限责任公司 采用有限数量的测试引脚测试存储器件的方法以及利用该方法的存储器件
CN110993522A (zh) * 2019-12-19 2020-04-10 华天科技（西安）有限公司 一种次良品3d nand降容使用的方法
CN112331251A (zh) * 2020-12-03 2021-02-05 深圳市博业诚电子有限公司 一种半导体存储器的测试方法
CN114743585B (zh) * 2022-06-10 2022-08-30 芯天下技术股份有限公司 用于测试闪速存储器的编程方法、装置及闪速存储器

Citations (3)

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US5987623A (en) * 1996-04-11 1999-11-16 Oki Electric Industry Co., Ltd. Terminal mapping apparatus
US7149871B2 (en) * 2002-12-09 2006-12-12 Sandisk Corporation Zone boundary adjustment for defects in non-volatile memories
US7184306B2 (en) * 2000-02-17 2007-02-27 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

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US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
KR100555506B1 (ko) * 2003-07-11 2006-03-03 삼성전자주식회사 프로그램된 메모리 셀들과 프로그램 및 소거 가능한메모리 셀들을 포함하는 메모리 장치
US7269062B2 (en) * 2005-12-09 2007-09-11 Macronix International Co., Ltd. Gated diode nonvolatile memory cell

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987623A (en) * 1996-04-11 1999-11-16 Oki Electric Industry Co., Ltd. Terminal mapping apparatus
US7184306B2 (en) * 2000-02-17 2007-02-27 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US7149871B2 (en) * 2002-12-09 2006-12-12 Sandisk Corporation Zone boundary adjustment for defects in non-volatile memories

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021045799A1 (fr) * 2019-09-03 2021-03-11 Silicon Storage Technology, Inc. Procédé d'amélioration de la stabilité de courant de lecture dans une mémoire non volatile analogique au moyen d'une cuisson finale dans un état de programme prédéterminé
US11017866B2 (en) 2019-09-03 2021-05-25 Silicon Storage Technology, Inc. Method of improving read current stability in analog non-volatile memory using final bake in predetermined program state

Also Published As

Publication number Publication date
TWI380165B (en) 2012-12-21
CN101779249B (zh) 2013-03-27
CN101779249A (zh) 2010-07-14
TW200912632A (en) 2009-03-16
KR20100040288A (ko) 2010-04-19
KR101440568B1 (ko) 2014-09-15

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