WO2008155794A1 - 情報処理装置 - Google Patents

情報処理装置 Download PDF

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Publication number
WO2008155794A1
WO2008155794A1 PCT/JP2007/000646 JP2007000646W WO2008155794A1 WO 2008155794 A1 WO2008155794 A1 WO 2008155794A1 JP 2007000646 W JP2007000646 W JP 2007000646W WO 2008155794 A1 WO2008155794 A1 WO 2008155794A1
Authority
WO
WIPO (PCT)
Prior art keywords
strand
entry
information processor
release
branch
Prior art date
Application number
PCT/JP2007/000646
Other languages
English (en)
French (fr)
Inventor
Ryuichi Sunayama
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/000646 priority Critical patent/WO2008155794A1/ja
Priority to EP07790172.6A priority patent/EP2159686B1/en
Priority to CN2007800533663A priority patent/CN101715576B/zh
Priority to KR1020097025988A priority patent/KR101100144B1/ko
Priority to JP2009520135A priority patent/JP5104861B2/ja
Publication of WO2008155794A1 publication Critical patent/WO2008155794A1/ja
Priority to US12/631,143 priority patent/US8151097B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Abstract

　同時マルチスレッド（SMT）方式の情報処理装置において、たとえば、２つのスレッド（ストランド）を平行して実行する場合、命令制御装置の分岐リザベーションステーションのエントリを、ストランド０用のエントリと、ストランド１用のエントリに分けて使用する。ストランド０のデータとストランド１のデータをそれぞれのおエントリに振り分けるのは、セレクト回路を切り替えることによる。また、分岐リザベーションステーションからエントリを解放する場合には、１つのストランド内の分岐命令の解放がインオーダーとなるように、セレクト回路でストランドを切り替えて、エントリを解放するようにする。
PCT/JP2007/000646 2007-06-19 2007-06-19 情報処理装置 WO2008155794A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
PCT/JP2007/000646 WO2008155794A1 (ja) 2007-06-19 2007-06-19 情報処理装置
EP07790172.6A EP2159686B1 (en) 2007-06-19 2007-06-19 Information processor and method therefor
CN2007800533663A CN101715576B (zh) 2007-06-19 2007-06-19 运算处理装置
KR1020097025988A KR101100144B1 (ko) 2007-06-19 2007-06-19 정보처리장치
JP2009520135A JP5104861B2 (ja) 2007-06-19 2007-06-19 演算処理装置
US12/631,143 US8151097B2 (en) 2007-06-19 2009-12-04 Multi-threaded system with branch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000646 WO2008155794A1 (ja) 2007-06-19 2007-06-19 情報処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/631,143 Continuation US8151097B2 (en) 2007-06-19 2009-12-04 Multi-threaded system with branch

Publications (1)

Publication Number Publication Date
WO2008155794A1 true WO2008155794A1 (ja) 2008-12-24

Family

ID=40155959

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000646 WO2008155794A1 (ja) 2007-06-19 2007-06-19 情報処理装置

Country Status (6)

Country Link
US (1) US8151097B2 (ja)
EP (1) EP2159686B1 (ja)
JP (1) JP5104861B2 (ja)
KR (1) KR101100144B1 (ja)
CN (1) CN101715576B (ja)
WO (1) WO2008155794A1 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5861354B2 (ja) * 2011-09-22 2016-02-16 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US9280398B2 (en) 2012-01-31 2016-03-08 International Business Machines Corporation Major branch instructions
US9229722B2 (en) 2012-01-31 2016-01-05 International Business Machines Corporation Major branch instructions with transactional memory
JP2014137732A (ja) * 2013-01-17 2014-07-28 Fujitsu Ltd 情報処理システム及び情報処理システムの制御方法
CN107567614B (zh) * 2015-06-01 2022-05-24 英特尔公司 用于对根据关键度被分组的指令的缕程的执行的多核处理器
US10175985B2 (en) 2016-03-28 2019-01-08 International Business Machines Corporation Mechanism for using a reservation station as a scratch register
US10831607B2 (en) * 2018-07-30 2020-11-10 International Business Machines Corporation Dynamic transaction throttling in a data processing system supporting transactional memory

Citations (12)

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Publication number Priority date Publication date Assignee Title
JPH1097461A (ja) 1996-07-03 1998-04-14 Internatl Business Mach Corp <Ibm> メモリ用マルチ・スレッド・セル
US6233599B1 (en) 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
WO2001041530A2 (en) 1999-12-09 2001-06-14 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
WO2001048599A1 (en) 1999-12-28 2001-07-05 Intel Corporation Method and apparatus for managing resources in a multithreaded processor
JP2002108630A (ja) 2000-08-15 2002-04-12 Internatl Business Mach Corp <Ibm> スレッド能力を変更する方法、マルチスレッド・コンピュータ・システム、及びマルチスレッド・プロセッサ
JP2002123402A (ja) 2000-08-15 2002-04-26 Internatl Business Mach Corp <Ibm> 正常なコンピュータ処理を継続する方法、マルチスレッド・コンピュータ・システム、及びプログラム製品
US20040003214A1 (en) 2002-06-28 2004-01-01 Fujitsu Limited Instruction control method and processor
JP2005514698A (ja) 2001-12-31 2005-05-19 インテル コーポレイション マルチスレッドプロセッサのスレッドの実行のサスペンド処理
JP2005309762A (ja) 2004-04-21 2005-11-04 Fujitsu Ltd スレッド切替制御装置。
JP3716415B2 (ja) 2003-04-28 2005-11-16 インターナショナル・ビジネス・マシーンズ・コーポレーション 同時マルチスレッドのための分割分岐履歴テーブルおよびカウント・キャッシュ
EP1622005A1 (en) 2004-07-27 2006-02-01 Fujitsu Limited Branch instruction control apparatus and control method with a branch reservation station
WO2006114874A1 (ja) 2005-04-21 2006-11-02 Fujitsu Limited プロセッサ装置

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JPS6441530A (en) 1987-08-07 1989-02-13 Sumitomo Electric Industries Mobile communication system
US20010037447A1 (en) * 2000-04-19 2001-11-01 Mukherjee Shubhendu S. Simultaneous and redundantly threaded processor branch outcome queue
US6988186B2 (en) * 2001-06-28 2006-01-17 International Business Machines Corporation Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry
US20060168571A1 (en) * 2005-01-27 2006-07-27 International Business Machines Corporation System and method for optimized task scheduling in a heterogeneous data processing system
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Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1097461A (ja) 1996-07-03 1998-04-14 Internatl Business Mach Corp <Ibm> メモリ用マルチ・スレッド・セル
US6233599B1 (en) 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
JP2003516570A (ja) 1999-12-09 2003-05-13 インテル・コーポレーション マルチスレッド・プロセッサ内の複数のスレッドに入り、出る方法と装置
WO2001041530A2 (en) 1999-12-09 2001-06-14 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
WO2001048599A1 (en) 1999-12-28 2001-07-05 Intel Corporation Method and apparatus for managing resources in a multithreaded processor
JP2002123402A (ja) 2000-08-15 2002-04-26 Internatl Business Mach Corp <Ibm> 正常なコンピュータ処理を継続する方法、マルチスレッド・コンピュータ・システム、及びプログラム製品
JP2002108630A (ja) 2000-08-15 2002-04-12 Internatl Business Mach Corp <Ibm> スレッド能力を変更する方法、マルチスレッド・コンピュータ・システム、及びマルチスレッド・プロセッサ
JP2005514698A (ja) 2001-12-31 2005-05-19 インテル コーポレイション マルチスレッドプロセッサのスレッドの実行のサスペンド処理
US20040003214A1 (en) 2002-06-28 2004-01-01 Fujitsu Limited Instruction control method and processor
JP3716415B2 (ja) 2003-04-28 2005-11-16 インターナショナル・ビジネス・マシーンズ・コーポレーション 同時マルチスレッドのための分割分岐履歴テーブルおよびカウント・キャッシュ
JP2005309762A (ja) 2004-04-21 2005-11-04 Fujitsu Ltd スレッド切替制御装置。
EP1622005A1 (en) 2004-07-27 2006-02-01 Fujitsu Limited Branch instruction control apparatus and control method with a branch reservation station
WO2006114874A1 (ja) 2005-04-21 2006-11-02 Fujitsu Limited プロセッサ装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2159686A4

Also Published As

Publication number Publication date
EP2159686B1 (en) 2019-01-09
KR20100007996A (ko) 2010-01-22
KR101100144B1 (ko) 2011-12-29
EP2159686A1 (en) 2010-03-03
EP2159686A4 (en) 2011-11-30
CN101715576B (zh) 2013-04-17
CN101715576A (zh) 2010-05-26
JP5104861B2 (ja) 2012-12-19
US20100082952A1 (en) 2010-04-01
US8151097B2 (en) 2012-04-03
JPWO2008155794A1 (ja) 2010-08-26

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