ATE407403T1 - Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange - Google Patents

Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange

Info

Publication number
ATE407403T1
ATE407403T1 AT05802300T AT05802300T ATE407403T1 AT E407403 T1 ATE407403 T1 AT E407403T1 AT 05802300 T AT05802300 T AT 05802300T AT 05802300 T AT05802300 T AT 05802300T AT E407403 T1 ATE407403 T1 AT E407403T1
Authority
AT
Austria
Prior art keywords
forming
command
commands
dma
memory access
Prior art date
Application number
AT05802300T
Other languages
English (en)
Inventor
Michael Day
Charles Johns
Peichun Liu
Thuong Truong
Takeshi Yamazaki
Original Assignee
Sony Computer Entertainment Inc
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc, Ibm filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE407403T1 publication Critical patent/ATE407403T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Details Of Television Systems (AREA)
  • Communication Control (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT05802300T 2004-07-15 2005-07-06 Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange ATE407403T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/891,772 US7243200B2 (en) 2004-07-15 2004-07-15 Establishing command order in an out of order DMA command queue

Publications (1)

Publication Number Publication Date
ATE407403T1 true ATE407403T1 (de) 2008-09-15

Family

ID=35478627

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05802300T ATE407403T1 (de) 2004-07-15 2005-07-06 Bildung einer befehlsreihenfolge in einer nicht sequentiell dma-befehlswarteschlange

Country Status (9)

Country Link
US (1) US7243200B2 (de)
EP (1) EP1711899B1 (de)
JP (1) JP4553936B2 (de)
KR (1) KR100827510B1 (de)
CN (1) CN100504827C (de)
AT (1) ATE407403T1 (de)
DE (1) DE602005009494D1 (de)
TW (1) TWI294573B (de)
WO (1) WO2006006084A2 (de)

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CN111522511B (zh) * 2020-04-22 2022-04-22 杭州宏杉科技股份有限公司 命令处理方法及装置
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Also Published As

Publication number Publication date
WO2006006084A3 (en) 2006-07-20
WO2006006084A2 (en) 2006-01-19
TW200617680A (en) 2006-06-01
DE602005009494D1 (de) 2008-10-16
WO2006006084A8 (en) 2006-04-20
JP4553936B2 (ja) 2010-09-29
EP1711899A2 (de) 2006-10-18
KR100827510B1 (ko) 2008-05-06
CN101031897A (zh) 2007-09-05
KR20060132856A (ko) 2006-12-22
US7243200B2 (en) 2007-07-10
CN100504827C (zh) 2009-06-24
TWI294573B (en) 2008-03-11
EP1711899B1 (de) 2008-09-03
JP2007529833A (ja) 2007-10-25
US20060015652A1 (en) 2006-01-19

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