WO2008152724A1 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

Info

Publication number
WO2008152724A1
WO2008152724A1 PCT/JP2007/062018 JP2007062018W WO2008152724A1 WO 2008152724 A1 WO2008152724 A1 WO 2008152724A1 JP 2007062018 W JP2007062018 W JP 2007062018W WO 2008152724 A1 WO2008152724 A1 WO 2008152724A1
Authority
WO
WIPO (PCT)
Prior art keywords
column
predetermined number
bit lines
storage device
memory cell
Prior art date
Application number
PCT/JP2007/062018
Other languages
English (en)
French (fr)
Inventor
Koichi Yoshimi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/062018 priority Critical patent/WO2008152724A1/ja
Publication of WO2008152724A1 publication Critical patent/WO2008152724A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

　カラム選択型のＳＲＡＭは、複数のメモリセル１と、各々が予め定められた数のビット線ＢＬに対応して設けられた複数のセンスアンプ６と、カラム選択信号に基づいて、前記予め定められた数のビット線ＢＬの中から１本のビット線ＢＬを対応するセンスアンプ６に接続するカラム回路８と、カラム選択信号線ＳＥＬを介してカラム選択信号を対応するメモリセル１に供給するカラム活性回路９と、メモリセル１の内部に設けられ、カラム選択信号に基づいて対応するワード線ＷＬをメモリセル１に接続する複数のスイッチ回路とを備える。
PCT/JP2007/062018 2007-06-14 2007-06-14 半導体記憶装置 WO2008152724A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062018 WO2008152724A1 (ja) 2007-06-14 2007-06-14 半導体記憶装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062018 WO2008152724A1 (ja) 2007-06-14 2007-06-14 半導体記憶装置

Publications (1)

Publication Number Publication Date
WO2008152724A1 true WO2008152724A1 (ja) 2008-12-18

Family

ID=40129341

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062018 WO2008152724A1 (ja) 2007-06-14 2007-06-14 半導体記憶装置

Country Status (1)

Country Link
WO (1) WO2008152724A1 (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022713A (ja) * 1988-06-16 1990-01-08 Kawasaki Steel Corp 半導体集積回路
JPH10222985A (ja) * 1998-03-09 1998-08-21 Hitachi Ltd 半導体記憶装置
JP2000339971A (ja) * 1999-05-26 2000-12-08 Nec Corp 半導体記憶装置
JP2001167581A (ja) * 1999-12-09 2001-06-22 Mitsubishi Electric Corp 半導体メモリ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022713A (ja) * 1988-06-16 1990-01-08 Kawasaki Steel Corp 半導体集積回路
JPH10222985A (ja) * 1998-03-09 1998-08-21 Hitachi Ltd 半導体記憶装置
JP2000339971A (ja) * 1999-05-26 2000-12-08 Nec Corp 半導体記憶装置
JP2001167581A (ja) * 1999-12-09 2001-06-22 Mitsubishi Electric Corp 半導体メモリ

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