WO2008137315A1 - Power factor correction (pfc) controller and method using a finite state machine to adjust the duty cycle of a pwm control signal - Google Patents
Power factor correction (pfc) controller and method using a finite state machine to adjust the duty cycle of a pwm control signal Download PDFInfo
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- WO2008137315A1 WO2008137315A1 PCT/US2008/061155 US2008061155W WO2008137315A1 WO 2008137315 A1 WO2008137315 A1 WO 2008137315A1 US 2008061155 W US2008061155 W US 2008061155W WO 2008137315 A1 WO2008137315 A1 WO 2008137315A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/476—Non-linear conversion systems
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
Definitions
- the present invention relates in general to the field of signal processing, and, more specifically, to a power factor correction (PFC) controller and method using a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal.
- PFC power factor correction
- PWM pulse width modulation
- Power factor correctors often utilize a switch-mode boost stage to convert alternating current (AC) voltages (such as line/mains voltages) to direct current (DC) voltages or DC-to-DC wherein the input current is proportional to the input voltage.
- Power factor correctors provide power factor corrected (PFC) and regulated output voltages to many devices that utilize a regulated output voltage.
- FIG. 1 represents a typical exemplary power factor corrector 100, which includes a switch-mode boost stage 102.
- Voltage source 101 supplies an alternating current (AC) input voltage V m (t) to a full-wave diode bridge rectifier 103.
- the voltage source 101 e.g., voltage Vj n (O) is, for example, a public utility, such as a 60 Hz/120 V line (mains) voltage in the United States of America or a 50 Hz/230 V line (mains) voltage in Europe.
- the input rate associated with input v ⁇ llage Vj n (I) is the frequency of voltage source 101 (e.g., 60 Hz in the U.S. and 50 Hz. in Europe).
- the rectifier 103 rectifies the input voltage Vi n (O and supplies a rectified, time- varying, line input voltage V x (t) to the switch-mode boost stage 102.
- the actual voltage at any time t is referred to as the instantaneous input voltage.
- the term "line rate" is hereafter referred to and defined as the rectified input frequency associated with the rectified line voltage V x (t).
- the line rate is also equal to twice the input frequency associated with input voltage V m (t).
- the rectified line input voltage is measured and provided in tenns of Root Mean Square (RMS) voltage, e.g., V rm s.
- RMS Root Mean Square
- the switch-mode boost stage 102 includes a switch 108 (e.g., Field Effect Transistor (FET)) by which it is controlled and provides power factor correction (PFC) in accordance with how switch 108 is controlled.
- the switch-mode boost stage 102 is also controlled by switch 108 and regulates the transfer of energy from the rectified line input voltage V x (t) through inductor 110 to capacitor 106 via a diode 1 11.
- the inductor current iu ramps 'up' when the switch 108 conducts, i.e. is "ON”.
- the inductor current i L ramps down when switch 108 is nonconducttve, i.e. is "OFF", and supplies current i t to recharge capacitor 106.
- . ramps down is commonly referred to as the "inductor flyback time”.
- a sense resistor 109 is utilized effectively in series with inductor 1 10 .
- Power factor correction (PFC) controller 114 of power factor corrector 100 controls switch 108 and, thus, controls power factor correction and regulates output power of the switch-mode boost stage 102.
- the goal of power factor correction technology is to make the switch-mode boost stage 102 appear resistive to the voltage source 101.
- the PFC controller 114 attempts to control the inductor current i t so that the average inductor current i L is proportionate to the rectified line input voltage V x (t).
- the PFC 1 14 supplies a pulse width modulated (PWM) control signal CSo to control the conductivity of switch 108.
- PWM pulse width modulated
- DCM Discontinuous Conduction Mode
- CCM Continuous Conduction Mode
- the lower voltage swing also reduces Electro Magnetic Interference (EMl), and a smaller input filter can then be used. Since switch 108 is turned “OFF" when the inductor current iL is not equal to zero, diode 1 1 1 needs to be very fast in terms of reverse recovery in order to minimize losses.
- EMl Electro Magnetic Interference
- the switching rate for switch 108 is typically operated in the range of 20 kHz l ⁇ 100kHz. Slower switching frequeiicieb are avoided in ⁇ rder t ⁇ avoid the human audio frequency range as well as avoid increasing the size of inductor 110. Faster switching frequencies are typically avoided since they increase the switching losses and are more difficult to use in terms of meeting Radio Frequency Interference (RF 1 I) standards.
- RF 1 I Radio Frequency Interference
- Capacitor 106 supplies.stored energy to load 112.
- the capacitor 106 is sufficiently large so as to maintain a substantially constant link output voltage V c (t) through the cycle of the line rate.
- the link output voltage V c (t) remains substantially constant during constant load conditions. However, as load conditions change, the link output voltage V c (t) changes.
- the PFC controller 1 14 responds to the changes in link output voltage V c (t) and adjusts the control signal CS 0 to resume a substantially constant output voltage as quickly as possible.
- the PFC controller 114 includes a small capacitor 1 15 to prevent any high frequency switching signals from coupling to the line (mains) input voltage V in (t).
- PFC controller 1 14 receives two feedback signals, the rectified line input voltage V x (t) and the link output voltage V c (t), via a wide bandwidth current loop 1 16 and a slower voltage loop 118.
- the rectified hne input voltage V-(t) is sensed from node 120 between the diode rectifier 103 and inductor 1 10.
- the link output voltage V c (t) is sensed from node 122 between diode 11 1 and load 112.
- the current loop 1 16 operates at a frequency f c that is sufficient to allow the PFC controller 1 14 to respond to changes in the rectified line input voltage V x (Q and cause the inductor current i L to track the rectified line input voltage V x (t) to provide power factor correction.
- the inductor current ⁇ L controlled by the current loop 1 16 has a control bandwidth of 5 kHz to 10 kHz.
- the voltage loop 1 18 operates at a much slower frequency control bandwidth of about 5 Hz to 20 Hz. By operating at 5 Hz to 20 Hz, the voltage loop 1 18 functions as a low pass filter to filter a harmonic ripple component of the link output voltage V c (t).
- a power factor corrector 100 may typically comprise of two Proportional-Integral (PI) controllers, one Pl controller associated with the current loop 1 16 and another Pl controller associated with the voltage loop 1 18. It would be desired and would simplify the circuitry for the power factor corrector 100 if the PI controller associated with the current loop 1 16 could be eliminated.
- typical power factor corrector 100 does not primarily comprise of digital circuitry. Thus, it is needed and desired to have a power factor corrector which is primarily made up of digital circuitry. It is needed and desired to also minimize the number of external components outside of a PFC controller for a power factor corrector.
- the present invention provides a power factor correction (PFC) controller and method using a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal.
- PFC power factor correction
- PWM pulse width modulation
- a power factor currector includes a switch-mode boost stage, a target current generator, a comparator, and a finite state machine.
- the switch-mode boost stage has a switch and an inductor coupled to the switch.
- the switch-mode boost stage receives a rectified line input voltage and provides a link output voltage.
- a sensed current is observed from the switch-mode boost stage.
- a target current generator receives the link output voltage and generates a target current proportionate to the rectified line input voltage.
- a comparator receives a target current value representative of the target current and a sensed current value representative of the sensed current.
- the comparator outputs a two-level current comparison result signal.
- a finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
- a power factor corrector includes a switch-mode boost stage, a target current generator, a comparator, and a finite state machine.
- the switch-mode boost stage has a switch and an inductor coupled to the switch.
- the switch-mode boost stage receives a rectified line input voltage and provides a link output voltage.
- a sensed current is observed from the switch-mode boost stage.
- a target current generator receives the link output voltage and generates a target current proportionate to the rectified line input voltage.
- a ripple current estimator generates a ripple current that estimates a peak-to-peak inductor ripple current.
- a comparator responsive to the target current, the ripple current, and the sensed current, outputs a two-level current comparison result signal.
- a finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
- the target current generator, the comparator, and the finite state machine can be taken together to make up a power factor correction (PFC) controller.
- the PFC controller can be implemented on a single integrated circuit, and the rectified line input voltage and the link output voltage can be correspondingly scaled for operational use by the integrated circuit.
- Figure 2A depicts a preferred embodiment uf a power factor corrector having a switch-mode boost stage and a finite state machine that utilizes a sensed current and a target current in order to adjust the duty cycle of a PWM control signal that controls a switch of the switch-mode boost stage.
- Figure 2B depicts another preferred embodiment of a power factor corrector having a switch-mode boost stage and a finite state machine that utilizes a sensed current and a target current in order to adjust the duty cycle of a PWM control signal that controls a switch of the switch-mode boost stage.
- Figure 3 depicts details of an exemplary PFC controller shown in Figures 2A and 2B.
- Figure 4 depicts an exemplary finite state machine of Figure 3 that shows details of a digital implementation of a time-based controller.
- Figure 5 depicts a high level logical flowchart of the operation of a digital implementation of the time-based controller shown in Figure 4.
- Figure 6A depicts exemplary current waveforms of rectified line input current (e.g., average boost inductor current J L ) and target current (e.g., itarget) for the power factor correctors of Figures 2 A and 2B shown at a time scale of 10 milliseconds.
- V L average boost inductor current
- itarget target current
- Figure 6B depicts exemplary current waveforms ofrectified line input current (e.g., average boost inductor current J L ) and target current (e.g., itarget) for the power factor correctors of Figures 2 A and 2B shown at a time scale of 10 microseconds.
- line input current e.g., average boost inductor current J L
- target current e.g., itarget
- Figure 6C depicts exemplary parameters fed into a representative voltage V x function generator for generating an off-time that is a function of line input voltage
- Figures 7 ⁇ depicts a transfer function of the representative voltage V x function generator of Figure 6C showing the off-time-to-minimum off-time ratio (Wto Rm i n ) being mapped against values of line input voltage (V x ).
- Figures 7B depicts a 10 millisecond cycle of line input voltage V x (t) when the input voltage V; n (t) is operated at a 120 Volt (RMS) Input Voltage Source.
- Figure 7C depicts the 10 millisecond cycle of Figure 7B showing the resulting off-time-to-minimum off-time ratios when the transfer function of Figure 7A is applied over the 10 millisecond cycle of line input voltage V x (t) shown in Figure 7B.
- Figures 8A depicts a 10 millisecond cycle of a line input voltage V x (t) when the input voltage V 1n (I) is operated at a 240 V ⁇ lt (RJMS) Input Voltage Source.
- Figure 8B depicts the 10 millisecond cycle of Figure 8A showing the resulting off-time-to-minimum off-time ratios when the transfer function of Figure 7A is applied over the 10 millisecond cycle of line input voltage Vx(t) shown in Figure 8A.
- Figure 9A depicts exemplary current waveforms for a preferred switch control algorithm for the power factor corrector shown in Figure 2A in which the switch current during its on-times is 50% above and 50% below the target current.
- Figure 9B depicts exemplary current waveforms for another preferred switch control algorithm for the power factor corrector shown in Figure 2B in which the boost inductor current is 50% above and 50% below the target current.
- Figure 10 depicts a state diagram for implementing by the finite state machine shown in Figures 3 and 4 either the preferred switch control algorithm as characterized by the exemplary current waveforms of Figure 9A or the other preferred switch control algorithm as characterized by the exemplary current waveforms of Figure 9B.
- Figure 1 1 depicts exemplary curient vvavefoims foi a still further preferred switch control algorithm for the power factor corrector shown in Figure 2A in which on-time of the switch current is determined when the switch current reaches a peak current that is determined by a taiget current and a ripple current.
- Figure 12 depicts a state diagram for implementing by the finite state machine shown in Figures 3 and 4 the preferred switch control algorithm as characterized by the exemplary current waveforms of Figure 1 1.
- Figure 13 depicts a power factor corrector of Figure 2A coupled to a memory.
- Figures HA to 1-iJ depict Mathematica code for an exemplary implementation of the functions of the switch control algorithm as depicted by Figures 9A, 9B, and 10.
- Figures 15A to 15J depict Mathematics code for an exemplary implementation of the functions of the switch control technique algorithm as depicted by Figures 11 and 12.
- a power factor corrector includes a switch-mode boost stage and a.power factor correction (PFC) controller that includes a finite state machine which adjusts the duty cycle of a Pulse Width Modulation (PWM) switching control signal for controlling a control switch of a switch-mode boost stage in accordance with the principles of the present invention.
- PFC power factor correction
- PWM Pulse Width Modulation
- the embodiment of power factor corrector 200A in Figure 2A only observes sensed current i sense (e.g., switch current i sen se A ) when.switch 208 is on.
- the embodiment of power factor corrector 200B in Figure 2B observes sensed current 'sense (e.g., boost inductor current isc ⁇ se ⁇ ) all of the time (e.g., whether switch 208 is on or off).
- FIG. 2 A depicts power factor corrector 200A, and power factor corrector 200A includes a switch-mode boost stage 202A and a PFC controller 214.
- PFC controller 214 uses a finite state machine to adjust the duty cycle of a PWM switching control signal CSo in accordance with the principles of the present invention.
- Power factor corrector 202A comprises full-wave diode bridge rectifier 203; capacitor 215; switch-mode boost stage 202A; and PFC controller 214.
- Switch-mode boost stage 202A further includes inductor 210, diode 21 1, switch 208, and capacitor 206.
- Power factor corrector 200A implements a high bandwidth current loop 216 and a slower voltage loop 218.
- a line (mains) voltage source 201 can couple to the input of power factor corrector 200A, and a load 212 can couple to the output of power factor corrector 200A.
- Power factor corrector 200A operates in the similar manner as power factor 100 as described above earlier except for the manner in which switch 208 is controlled. (41) In the embodiment of power factor corrector 200A, switching of switch 208 is calculated and performed so that the average current of boost inductor current i ⁇ , being the line input current, varies proportionately with the rectified line input voltage V x (I) where the proportionality ratio is selected such that the capacitor link voltage/output voltage V f (t) is regulated.
- the goal of making power factor corrector 200A appear resistive to the voltage source 201 is further accomplished by coupling a sense current resistor 209A in series with switch 208 (e.g., coupled between switch 208 and the negative node of line input voltage V x (t)).
- nw in this case is the switch current ise n se A - Switch current iscnseA is being utilized to provide PFC control of switch-mode boost stage 202A, and this PFC control will be discussed later when Figure 9A is discussed in more detail.
- PFC controller 214 also has a finite state machine which is used to adjust the duty cycle of the PWM switching control signal.
- PFC controller 214 and its operations and functions can be implemented on a single integrated circuit.
- a voltage divider comprising resistors Rl and R2 is coupled to the input of the PFC controller 214 where the line input voltage V x (t) is fed in, and another voltage divider comprising resistors R3 and R4 is coupled to the input of the PFC controller where the link output voltage V c (t) is fed in.
- the values for resistors Rl, R2, R3, and R4 are selected so that the voltage dividers scale down the line input voltage V x (t) and link output voltage V c (t) to scaled line input voltage V x ⁇ c(t) and scaled link output voltage V ct c(t) that can be used for an integrated circuit.
- the inductor current i L is observed only when switch 208 is on.
- FIG. 2B depicts another preferred embodiment power factor corrector 200B.
- Power factor corrector 200B is identical to power factor corrector 200A except that instead of using a switch current resistor 209 A in which switch current is used to provide PFC control of switch-mode boost stage 202 A, a boost inductor current sense resistor 209B is utilized effectively in series with inductor 210.
- Boost inductor current isense ⁇ in this alternate embodiment is used to provide PFC control of switch- mode boost stage 202B, and this PFC control will be discussed later when Figure 9B is discussed in more detail.
- PFC controller 214 still uses a finite state machine (e.g., finite state machine 304) to adjust the duty cycle of PWM switching control signal CSo in accordance with the principles of the present invention.
- a finite state machine e.g., finite state machine 304
- PFC controller 214 in power factor corrector 200B and its operations and functions can also be implemented on a single integrated circuit.
- the voltage dividers comprising the same resistors Rl , R2, R3, and R4 for power factor corrector 200A can be utilized to scale down the line input voltage V,(t) and link output voltage V c (t) in power factor corrector 200B to scaled line input voltage V x ⁇ c(t) and scaled link output voltage V c ⁇ c(t) that can be used for an integrated circuit.
- the inductor current i L is observed all of the time (e.g., whether switch 208 is on or off).
- Typical values for sense resistor 209A or 209B are from 0.05 to 0.5 ohm.
- the manners of sensing current are certainly not limited to the use of sense resistors or the power factor correctors 200A and 200B disclosed in Figures 2A and 2B.
- Olher current sense techniques can alternatively include the use of current sense transformers or Hall effect devices.
- FIG. 3 shows details of an exemplary PFC controller 214 as used in power factor correctors 200A and 200B in respective Figures 2A and 2B.
- Exemplary PFC controller 214 includes a target current generator 300, a comparator 303, and a finite state machine 304 coupled together in the manner shown in Figure 3.
- Target current generator 300 includes an analog-to-digital converter (ADC) 320, a multiplier 301, a digital-to-analog converter (DAC) 307, a multiplier 312, a digital proportional- integral (Pl) voltage controller 302, and an ADC 322.
- Digital PI controller 302 may be a typical Pl controller having a proportional circuit path and an integral circuit path.
- C (t) of slower voltage loop 218 is fed into ADC 322, and the corresponding digital output signal 323 of ADC 322 is fed into the digital Pl voltage controller 302.
- PI controller 302 preferably is in the form of an Infinite Impulse Response (HR) digital filter.
- the output of the IIR filter e.g., Pl output signal 315 from Pl controller 302 is proportionate to the estimated power demand of load 212 to be delivered to switch-mode boost stage 202 A or 202B.
- PI output signal 315 is fed into multiplier 312.
- a scaling factor signal 317 that is equivalent to l/V ⁇ 2 is also fed into multiplier 312.
- Multiplier 312 multiplies the values from scaling factor signal 317 and Pl output signal 315 and generates scaled digital output voltage signal 309. (46)
- ADC 320 receives IC scaled line input voltage V X
- Digital output signal 319 is fed into multiplier 301.
- Multiplier 301 multiplies values of scaled digital output voltage signal 309 by values of digital output signal 319 to provide a digital output product value 350.
- Digital output product value 350 is fed into DAC 307, and DAC 307 converts the digital output product value 350 into a reference voltage V(i, arge ,) that is representative of the target current value (Wget).
- a sensed current voltage V(i,en «-) (e.g., sensed current value) is a voltage that is representative of a sensed current signal i sen se, which may be switch current i 5Cn se A in switch-mode boost stage 202A or boost inductor current i, en «B in switch-mode boost stage 202B.
- Comparator 303 compares reference voltage V(i, arge ,) with sensed current voltage V(i sense ).
- Reference voltage V(i targel ) corresponds and is proportional to a target current i ⁇ ar gci» which is the desired average inductor current for line input current ii..
- Target current iiarget being proportionate to line input voltage V x (t), ensures that the line input current ⁇ L has a high power factor and low distortion.
- Target current it atgct is a full-wave rectified sinusoidal current waveform as shown in Figures 6A and 6B.
- Comparator 303 outputs a voltage comparison result signal 314, which in this example is a two-level current comparison result signal (e.g., "two-level” implying one state ⁇ f the comparison, such as above a desired threshold, and another slate of comparison, such as below a desired threshold), and voltage comparison result signal 314 is fed into finite state machine (FSM) 304.
- FSM finite state machine
- Finite state machine 304 processes an FSM algorithm (e.g., switch control algorithm) that adjusts the duty cycle of the PWM switching control signal CSo based on the received voltage comparison result signal 314 to control switch 208 in accordance with the principles of the present invention.
- One present invention embodiment of the FSM algorithm is controlling or adjusting the switch timing of PWM switching control signal CSo such that the boost inductor current i L is above the target current threshold fifty percent (50%) of the time and below the target current threshold the other fifty percent (50%) of the time.
- This embodiment of the FSM algorithm will be discussed in more detail when Figures 9A, 9B, and 10 are described later.
- Another present invention embodiment of the FSM algorithm is controlling or adjusting the switch timing of PWM switching control signal CSo such that control switch 208 is activated until the boost inductor current i ⁇ _ reaches a target current i, arz ⁇ , that is equal to a peak current value i peak determined by iiargct + ⁇ RIPPLE /2 where i lar get is a target current and I RIPPLE is a peak-to-peak ripple current in the inductor 210.
- This other embodiment of the FSM algorithm and these current values and equations will be discussed in more detail when Figures 11 and 12 are described later.
- the embodiment shown for PFC controller 214 in Figure 3 is exemplary, and there are many possible variations.
- the multipliers may be analog instead of digital, removing the associated analog-to digital (A/D) and digital-to-analog (D/A) conversion steps.
- the analog input signals may be currents instead of voltages.
- the input sine wave may be synthesized by a table look up of function generat ⁇ r, and synchronized to the external line.
- the comparator may be digital, and the current input digitized. In all cases, a current reference signal is generated and compared to the switch-mode current. The comparison is used by a finite state machine (FSM) to control the switch control duty cycle.
- FSM finite state machine
- FSM 304 comprises a time-based controller 410.
- Exemplary time based controllers are disclosed in pending U.S. Patent Application No. 11/864,366 filed on Sept. 28, 2007 entitled “Time-Based Control of a System Having Integration Response” to John Melanson and assigned to common assignee Cirrus Logic, Inc., Austin, Texas (hereafter the "Time-Based Control patent case”).
- the Time-Based Control patent case is hereby incorporated by reference.
- time-based controller 410 implements a time-based control methodology, rather than one of the conventional magnitude -based control methodologies described above.
- Voltage comparison result signal 314 is received by time calculation logic 422 that, responsive thereto, dete ⁇ nines the time at which the state of switch 2Ub should be changed in order to maintain the average value of sensed current signal iscse at the target average value (e.g., target current itarg n ).
- Time- based controller 410 includes a pulse-width modulator (PWM) 424 that asserts or deasserts control signal 430 to change the state of switch 208 at the time indicated by time calculation logic 422.
- PWM pulse-width modulator
- an oscillator 432 feeds into FSM 304 and into time calculation logic block 422. Oscillator 432 is utilized for implementing the desired FSM algorithm.
- FIG. 5 there is illustrated a high level logical flowchart of the operation of a digital implementation of the time-based controller 410 ⁇ f Figure 4.
- the illustrated process can be implemented by an application specific integrated circuit (ASIC), general purpose digital hardware executing program code from a tangible data storage medium that directs the illustrated operations, or other digital circuitry, as is known in the art. Further, the illustrated process can be utilized to implement any of the time-based constant period, time-based constant off-time, time-based variable period, or time-based variable off-time control methodologies.
- ASIC application specific integrated circuit
- the process shown in Figure 5 begins at block 501 and then proceeds to block 502, which depicts time-based controller 410 asserting control signal CSo (e.g., placing control signal CSo in a first state) to turn on switch 208 and thus begin a time interval A (e.g., time W in Figures 7A and 9).
- control signal CSo e.g., placing control signal CSo in a first state
- a time interval A e.g., time W in Figures 7A and 9
- the process iterates at block 504 until comparator 418 indicates that time interval A has ended by signaling that the value of sensed current signal i sen se has crossed the value of target current i targc , in this case, in a positive transition.
- the change in relative magnitudes of voltage comparison result signal 314 and sensed current signal i xllM thus causes a polarity change in the output of comparator 303 indicating (in this embodiment) that sensed current signal i ⁇ se is at least as great as target current i (a rge ⁇ (or in other embodiments, that sensed current signal is equal to or less than target current i mg c t )-
- time calculation logic 422 records the duration of time interval A (block 506) based upon the value of a digital counter or timer.
- Time calculation logic 422 then calculates the duration of time interval B (e.g., time t on e in Figures 7A and 9), for example, utilizing one of the equations (e.g., Equation B for calculating the on-time ⁇ .. B ) that will be later discussed with Figure 10 (block 508).
- the duration of time interval B e.g., time t on e in Figures 7A and 9
- one of the equations e.g., Equation B for calculating the on-time ⁇ .. B
- pulse width modulator 424 then detects (e.g., utilizing a digital counter or timer) when the calculated duration of time interval B has elapsed from the time comparator 303 indicating the end of time interval B. In response to a determination that the calculated duration of time interval B has elapsed, pulse width modulator 424 deasserts control signal CSo (e.g., places control signal CSo in a second state) to turn off switch 208.
- control signal CSo e.g., places control signal CSo in a second state
- Pulse width modulator 424 thereafter waits a fixed or variable off time (time interval t O frin Figures 7A and 9) in accordance with the selected control methodology (block 514) and again asserts the control signal CSo to turn on switch 208 and begin time interval A (e.g., time t onA ) of a next cycle of operation, as shown in block 502. The process thereafter proceeds as has been described.
- a plot 600 of exemplary current waveforms (in Amps) of line input current (e.g., average boost inductor current ii) and target current iorget for the power factor correctors of Figures 2 A and 2B are shown at a time scale of 10 milliseconds.
- the exemplary waveforms are viewed from the perspective of the rectified line (mains) rate of exemplary 100 Hz. From this line (mains) rate perspective shown in Figure 6A, the target current i mrget is seen as half of a full-wave rectified sinusoidal waveform and is varying or moving.
- a plot 602 of exemplary current waveforms (in Amps) of line input current (e.g., average boost inductor current i L ) and target current (e.g., i Iarg et) for the power factor correctors of Figures 2A and 2B are shown at a time scale of 10 microseconds.
- the exemplary waveforms are viewed from the perspective of the switch rate of exemplary 100 kHz (e.g., switch rate for switch 208). From this perspective shown in Figure 6B, the target current i ⁇ a rge i is seen as pseudo-stationary.
- switch rate stationary is defined and understood to mean that a signal is varying at the scale of the line (mains) rate but is treated as stationary or constant at the scale (from the perspective) of the switch rate, particularly for the purposes of implementing the FSM algorithm (e.g., switch control algorithm) of the present invention.
- FSM algorithm e.g., switch control algorithm
- Power factor correctors 200A and 200B which vary the off-time t o n- slowly can also be described as "On-time controlled by Fast Current Feedback (e.g., current loop 216), Off-time controlled by Slow Voltage Feedforward (e.g., V x )".
- the slow voltage feedforward does not substantively interfere with the operation of the fast current feedback.
- the embodiments of power factor correctors 200A and 200B and any other suitable power factor corrector embodiment are able to vary the duty cycle of PWM control signal CSo generally in at least three different methods.
- the first method which is the preferred embodiment, is over periodic cycles of sensed current !
- the on-time to n of switch 208 e.g., w and t onB shown in Figures 7A, 7B, and 9
- the off-time toff of switch 208 e.g., ton- shown in Figures 7A, 7B, and 9 as a constant.
- the second method is over periodic cycles of sensed current i ⁇ , to maintain the on-time to n of switch 208 (e.g., tonA and ⁇ nB shown in Figures 7A, 7B, and 9) as a constant and to vary the off-time W of switch 208 (e.g., I 00 - shown in Figures 7A, 7B, and 9).
- the third method is to maintain the period of sensed current i s e n se constant and to vary the on-time to n and off-time t o rrof switch 208 accordingly.
- the third method requires more mathematical calculations but is preferred in some cases where complete control of the switching frequency rate of control signal CSo for switch 208 is needed.
- Varying the off- time ton from the perspective of the line (mains) rate provides a higher power factor and higher efficiency for switch-mode boost stages 202A and 202B.
- the off-time tofr is desirably varied across the half period of the input sine period.
- the voltage input source is very high (e.g., 240 V)
- the inductor flyback time (off-time t O ⁇ ) can be quite long.
- An increase of the off-time W is shown in accordance with Figure 7 A. The purpose of varying off-time W is to minimize distortion while maximizing efficiency.
- the off-time t off would be considered "constant" (e.g., not varying rapidly). However, the off-time t off may be varied at the line rate scale to improve performance.
- a time duration generator is used to generate a time interval (such as an off- time t off or a switching period for switch 208) that is provided to FSM 304.
- An exemplary time duration generator is shown as a period function generator 652 in Figure 6C.
- Period function generator 652 receives the IC scaled rectified line input voltage V x ⁇ c(t).
- Exemplary parameters are fed into period function generator 652 for generating the time interval that is a function of 1C scaled rectified line input voltage V ⁇ ic(t).
- the exemplary parameters are used to define the characteristics of the period function generator 652.
- Exemplary parameters fed into the period function generator 652 can include at least inductor value 654 for inductor 210, time interval parameters 656, power level 658, which is the power level relating to V c detected from capacitor 206, and RMS voltage 660, which is the RMS voltage level V x across capacitor 215 detected by a RMS voltage detector.
- Figure 7A depicts a transfer function of the representative voltage V x function generator of Figure 6C showing the off-time-to-minimum off-time ratio (to ⁇ /tofrmi ⁇ i) being mapped against values of line input voltage (V x ).
- Figure 7A generally shows how the off-time t of r is varied as a function (such as exemplary piece-wise linear function) of the instantaneous line voltage V,. This function can be chosen to maximize efficiency, and the function can alternatively be a mathematical function or a lookup table function.
- This relationship is used to determine for a given input voltage source (E g , 120 Volt or 240 Volt) how the line voltage V x varies over a given time period and how the ratio of off-time to a minimum off-time to ⁇ /WmiD varies over the same time period.
- An exemplary Mathematica code implementation of off- time being varied as a piece-wise linear function of the instantaneous line voltage Vx is shown in lines 33 to 38 of Figure 14C.
- Figures 7B depicts a line input voltage V x (t) over a ten (10) millisecond cycle when the input voltage V, n (t) is operated at a 120 Volt (RMS) input voltage source.
- Figure 7C depicts the same 10 millisecond cycle of Figure 7B showing the resulting off-time-to-minimum off-time ratios when the transfer function of Figure 7A is applied over the 10 millisecond cycle of line input voltage V x (I) shown in figure 7B.
- the value for link output voltage Vc(t) is 400 Volts (e.g., the voltage across link capacitor 206 in Figures 2A and 2B).
- graph 702 illustrates the line voltage increasing from 0 V to 170 V over the first 5 ms of the 10 ms period and then decreasing from 170 V to 0 V over the second 5 ms of the 10 ms period.
- Figure 7C shows graph 704 which depicts that the ratio Wto f i m i ⁇ stays at 1 for the first couple of milliseconds, rises to 1.3 at 5 ms, falls to 1 over the next couple of milliseconds, and stays at 1 through 10 ms.
- Figures 7B and 7C are viewed at the line input rate scale, so at that time scale, off-time to/r appears to be varying over an exemplary 10 ms sense cycle. However, at the perspective of the switch rate scale (e.g., 10 microseconds relating to 100 kHz), the off-time t o ⁇ - would be considered not to be varying rapidly
- Figure 8A depicts a line input voltage V x (t) over a ten (10) millisecond cycle when the input voltage V, n (t) is operated at a 240 Volt (RMS) input voltage source.
- Figure 8B depicts the same 10 millisecond cycle of Figure 8A showing the resulting off-time-to-minimum off-time ratios (WWmin) when the transfer function of Figure 7A is applied over the 10 millisecond cycle of rectified line input voltage V x (t) shown in Figure 8A.
- WWmin off-time-to-minimum off-time ratios
- the value for link output voltage Vc(t) is 400 Volts (e.g., the voltage across link capacitor 206 in Figures 2A and 2B).
- the maximum peak value for line voltage V x is equal to 240 Volts (RMS) multiplied ⁇ /2 (Square Root of 2) which is about 330 Volts. Furthermore, in this example, with the minimum off-time t o nTM, being still 8 microseconds, the maximum off-time W is 24 microseconds. Thus, the ratio of off-time to minimum off-time ratio toff ⁇ oftmin can vary from 1 to 3.
- Figures 8A and 8B are viewed at the line input rate scale, so at that time scale, oflT-tiine l Off appears Io be varying over an exemplary 10 ms cycle. However, ai the perspective of the switch rate scale (e.g., 10 microseconds relating to 100 kHz line rate), the off-time W would be considered not to be varying rapidly.
- exemplary waveforms of the switch current •scns cA and target current i, argc are shown at the switch rate scale for a preferred exemplary control technique of control switch 208.
- Target current i targe i is considered and viewed as switch rate stationary relative to switch current is e n seA -
- Switch current iscnscA is shown during the on-times of switch current as being fifty percent (50%) above (e.g., above-time duration) and fifty percent (50%) below (e.g., below-time duration) the target current i ta rgw-
- exemplary waveforms of the boost inductor current i scnsc o and target current ii arge i are shown at the switch rate scale.
- Target current i Iargc is considered and viewed as switch rate stationary relative to boost inductor current ijens c ⁇ - Boost inductor current iscseB is shown during the on-times of switch current as being fifty percent (50%) above and fifty percent (50%) below the target current i ⁇ during a switching period (e.g., t onA + t on e + ton)
- the waveforms in Figures 9A and 9B help illustrate an exemplary control technique that would be implemented by an FSM algorithm for FSM 304.
- switch current i sense A in switch-mode boost stage 202 A and boost inductor current i se n ⁇ B in switching power converter 202B may be generically referred to as sensed current signal i sen « -
- Time-based controller 410 is used to adjust the switch timing such that the sensed current isense (e.g., switch current is enseA or boost inductor current isense ⁇ ) is above the target current (iurg e t) threshold fifty percent (50%) of the on-time t ⁇ , n of switch 208 and below the target current (itarge ⁇ threshold the other fifty percent (50%) of the on-time to n
- the FSM algorithm e.g., switch control algorithm
- treats the target current i ta rget treats being switch rate stationary relative to sensed current i sen se-
- the boost inductor current ii_ comprise approximately linear ramps, and these linear ramps ensure that the average current of boost inductor current i L (e.g., line input current) tracks the target current i larg ci.
- the first method of varying duty cycle is implemented in which the on- time t o n of switch 208 (e.g., U IA and t on ⁇ shown in Figures 7A, 7B, and 9) is varied and the off-time t o nr is considered to be maintained as a constant over periodic cycles of sensed current i ⁇ when viewed at the switch rate scale.
- this control technique only requires the sensed current i xn ⁇ x be sensed when switch 208 is activated or "ON", making it compatible with the sense resistor 209A of Figure 2A and sense resistor 209B of Fig. 2B. Because time-based controller 410 enables control of the switch timing for switch 208 as described above, a Pl controller associated with current loop 216 is not needed or required, and thus complexity of the circuit for power factor correctors 200A and 200B can be simplified.
- FIG. 10 a state diagram 1000 is shown for the FSM 304 shown in Figures 3 and 4.
- State diagram 1000 shows how the FSM algorithms (e.g., switch control algorithms) are implemented for the embodiments of power factor correctors 202 ⁇ and 202B.
- Figures 9 ⁇ , 9B, and 10 are now discussed together.
- a timer is implemented with an oscillator 432 and a digital counter in which the clock from oscillator 432 drives the clock input of the counter.
- a digital counter with a preset and up/down count is well known in the art.
- State diagram 1000 shows that for this preferred control technique embodiment, FSM algorithm moves to a state SO in which the digital counter is reset.
- state SO switch 208 is on, and a count value T onA is started.
- Count value T OTA is used to determine and track the lapsed time for on-time tonA of switch 208.
- Sensed current i ⁇ is compared with target current i t3Iget by comparator 303 comparing sensed current voltage V(i sense ) with reference voltage V(i L ) which corresponds to a target current i tai ⁇ e i.
- new count value T 0n A 5 is used to calculate an updated count value for T 0n A by adding one (I) to the current value of T 0n A. That is,
- the count value T 0nA is then captured in a latch when comparator 303 changes state, that is, when sensed current W e becomes greater than or equal to target current i, ar&a - Count value T 0n D is used to determine and track the lapsed time for on-time of switch 208.
- New count value T 0nB ' is calculated by adding the old count value T 0nB with the captured count value T onA and dividing this sum by two (2) for providing an updated on-time t o ns, that is,
- the FSM algorithm moves to state Sl in which switch 208 is still on while the timer tracks whether the current count value T 0n B has been reached, which reflects the updated on-time tnnR having lapsed.
- FSM algorithm then moves to state S2 in which the switch 208 is off.
- Digital counter is then reset again.
- a count value T O (r is used to determine and track the lapsed time for off-time Wof switch 208, and the count value T O (r is determined as a function of the line input voltage V x (t).
- the digital counter reaches the count value T o n, FSM algorithm loops back to state SO and repeats thereafter.
- voltage loop 218 is updated at the line rate (e.g., 100 Hz or 120 Hz).
- exemplary waveforms of the switch current isenseA which ib the switch current in Figure 2A, and a peak current ip EAK is bh ⁇ wn at the switch rate scale for another preferred exemplary control technique of control switch 208.
- Target current imrset is calculated proportionate to the line input voltage V x (I) as discussed in the previous embodiment, and peak current ip EAK is considered and viewed as switch rate stationary relative to switch current i se n seA .
- Switch current isenseA is shown as ramping up by switch 208 being turned on until.switch current isenseA reaches the peak current JPEAK- When switch current i se n seA reaches peakxurrent ipEAK, switch 208 is then turned off for an off-time period X 0 ⁇ .
- Ripple current i t iipp LE is calculated as the difference between the minimum and maximum values of the inductor current i L over one period.
- the peak-to-peak inductor ripple current ⁇ RIPPLE is calculated as the off-time W multiplied by the difference of scaled link output voltage V c (t) and line input voltage V x (t) divided by the i nductance value L of inductor 210, that is:
- the inductor value L may be determined by run-time measurement. For example, if the time is measured for the switch current is e n s e A to go from target current i, ar get to then the inductance value can be determined as Vx(t) * (delta time / delta current).
- state diagram 1200 shows that for this preferred control technique embodiment, FSM algorithm moves to a state SO in which switch 208 is on. State diagram 1200 then depicts that FSM algorithm waits until the condition in which peak current JPB A K is greater than the sum of the target current and ripple current impp LE divided by two (2), that is,
- FSM algorithm shown in state diagram 1200 moves to state S l in which switch 208 is turned on. FSM algorithm then waits a "constant" off-time (as discussed earlier) and then goes back to state SO and repeats thereafter.
- Exemplary waveforms in higures 7A, 7B, 7C, 8 A, 8B, 9 A, 9B, 10, 11, and 12 define the functions and operations of the control technique algorithms for controlling switch 208.
- the characteristics of these functions and operations determine the operating behavior of and operating frequencies for the power factor correctors 200A and 200B.
- the parameters are stored in digital registers which can be loaded from an external memory.
- ROM read- only memory
- EEPROM Electrically Erasable Programmable Read-Only Memory
- flash memory or a one-time programmable (OTP) memory
- OTP one-time programmable
- Figure 13 depicts an exemplary power factor corrector 200A which incorporates a memory 1300 that is coupled to PFC controller 214.
- Memory 1300 stores operational parameters, such as the exemplary parameters (e.g., inductor value 654, time interval (such as off-time t of ror sensed current period parameters 656, power level 658, RMS level 660) for defining the transfer function of voltage V x function generator 652.
- memory 1300 is a nonvolatile storage medium.
- Memory 1300 can be, for example, a read/write memory, a one time programmable memory, a memory used for table lookup, or a loadable register. How and when the PFC operational parameters are loaded into and accessed from memory 1300 is a design choice.
- Figures 14A to 14J depict Mathematica code (i.e., Mathematica is an engineering computer program developed by Wolfram Research in Champaign, Illinois) for an exemplary implementation of the functions of the control technique algorithm as depicted by Figures 9A, 9B, and 10.
- Figures 15A to 15J depict Mathematica code for an exemplary implementation of the functions of the control technique algorithm as depicted by Figures 11 and 12.
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Abstract
A power factor correction (PFC) controller and method uses a finite state machine (304) to adjust the duty cycle of a pulse width modulation (PWM) switching control signal (CSo). The PFC controller has a target current generator (300) that receives the link output voltage ( Vcic(t)) and generates a target current (V(itarget) ) proportionate to the rectified line input voltage (Vxic (t) ). The PFC controller further includes a comparator (303) which outputs a two-level current comparison result signal. The finite state machine (304) responsive to the two-level current comparison result signal, generates a switch control signal (CSo) that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
Description
POWER FACTOR CORRECTION (PFC) CONTROLLER AND METHOD USING A FINITE STATE MACHINE TO ADJUST THE DUTY CYCLE OF A
PWM CONTROL SIGNAL
John L. Melanson
Cross-reference to Related Application
(1) This application claims the benefit under 35 U.S.C. § 119(e) and 37 C.F.R §1.78 of U.S. Provisional Application No. 60/915,547, filed May 2, 2007, and entitled "Power Factor Correction (PFC) Controller Apparatuses and Methods," and is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
Field of the Invention
(2) The present invention relates in general to the field of signal processing, and, more specifically, to a power factor correction (PFC) controller and method using a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal.
DESCRIPTION OF THE RELATED ART
(3) Power factor correctors often utilize a switch-mode boost stage to convert alternating current (AC) voltages (such as line/mains voltages) to direct current (DC) voltages or DC-to-DC wherein the input current is proportional to the input voltage. Power factor correctors provide power factor corrected (PFC) and regulated output voltages to many devices that utilize a regulated output voltage.
(4) Figure 1 represents a typical exemplary power factor corrector 100, which includes a switch-mode boost stage 102. Voltage source 101 supplies an alternating current (AC) input voltage Vm(t) to a full-wave diode bridge rectifier 103. The voltage source 101 (e.g., voltage Vjn(O) is, for example, a public utility, such as a 60 Hz/120 V line (mains) voltage in the United States of America or a 50 Hz/230 V line (mains) voltage in Europe. The input rate associated with input vυllage Vjn(I) is the
frequency of voltage source 101 (e.g., 60 Hz in the U.S. and 50 Hz. in Europe). The rectifier 103 rectifies the input voltage Vin(O and supplies a rectified, time- varying, line input voltage Vx(t) to the switch-mode boost stage 102. The actual voltage at any time t is referred to as the instantaneous input voltage. Unless otherwise stated, the term "line rate" is hereafter referred to and defined as the rectified input frequency associated with the rectified line voltage Vx(t). The line rate is also equal to twice the input frequency associated with input voltage Vm(t). The rectified line input voltage is measured and provided in tenns of Root Mean Square (RMS) voltage, e.g., Vrms.
(5) The switch-mode boost stage 102 includes a switch 108 (e.g., Field Effect Transistor (FET)) by which it is controlled and provides power factor correction (PFC) in accordance with how switch 108 is controlled. The switch-mode boost stage 102 is also controlled by switch 108 and regulates the transfer of energy from the rectified line input voltage Vx(t) through inductor 110 to capacitor 106 via a diode 1 11. The inductor current iu ramps 'up' when the switch 108 conducts, i.e. is "ON". The inductor current iL ramps down when switch 108 is nonconducttve, i.e. is "OFF", and supplies current it to recharge capacitor 106. The time period during which inductor current i|. ramps down is commonly referred to as the "inductor flyback time". A sense resistor 109 is utilized effectively in series with inductor 1 10 .
(6) Power factor correction (PFC) controller 114 of power factor corrector 100 controls switch 108 and, thus, controls power factor correction and regulates output power of the switch-mode boost stage 102. The goal of power factor correction technology is to make the switch-mode boost stage 102 appear resistive to the voltage source 101. Thus, the PFC controller 114 attempts to control the inductor current it so that the average inductor current iL is proportionate to the rectified line input voltage Vx(t). Unitrode Products Datasheet entitled "UCC2817, UCC2818, UCC3817, UCC3818 BiCMOS Power Factor Preregulator " (SLUS3951) dated February 2000 -Revised February 2006 by Texas Instruments Incorporated, Copyright 2006-2007 (referred to herein as "Unitrode datasheet") and International Rectifier Datasheet entitled "Datasheet No. PD60230 rev C IRl 150(S(PbF) and IR 11501(S)(PbF)" dated February 5, 2007 by International Rectifier, describe examples of PFC controller 114. The PFC 1 14 supplies a pulse width modulated (PWM) control signal CSo to control the conductivity of switch 108.
(7) Two modes of switching stage operation exist: Discontinuous Conduction Mode ("DCM") and Continuous Conduction Mode ("CCM"). In DCM, switch 108 of PFC controller 1 14 (or boost converter) is turned on (e.g., "ON") when the inductor current iL equals zero. In CCM, switch 108 of PFC controller 114 (or boost converter) switches "ON" when the inductor current is non-zero, and the current in the energy transfer inductor 110 never reaches zero during the switching cycle. In CCM, the current swing is less than in DCM, which results in lower I2R power losses and lower ripple current for inductor current JL which results in lower inductor core losses. The lower voltage swing also reduces Electro Magnetic Interference (EMl), and a smaller input filter can then be used. Since switch 108 is turned "OFF" when the inductor current iL is not equal to zero, diode 1 1 1 needs to be very fast in terms of reverse recovery in order to minimize losses.
(8) The switching rate for switch 108 is typically operated in the range of 20 kHz lυ 100kHz. Slower switching frequeiicieb are avoided in υrder tυ avoid the human audio frequency range as well as avoid increasing the size of inductor 110. Faster switching frequencies are typically avoided since they increase the switching losses and are more difficult to use in terms of meeting Radio Frequency Interference (RF1I) standards.
(9) Capacitor 106 supplies.stored energy to load 112. The capacitor 106 is sufficiently large so as to maintain a substantially constant link output voltage Vc(t) through the cycle of the line rate. The link output voltage Vc(t) remains substantially constant during constant load conditions. However, as load conditions change, the link output voltage Vc(t) changes. The PFC controller 1 14 responds to the changes in link output voltage Vc(t) and adjusts the control signal CS0 to resume a substantially constant output voltage as quickly as possible. The PFC controller 114 includes a small capacitor 1 15 to prevent any high frequency switching signals from coupling to the line (mains) input voltage Vin(t).
(10) PFC controller 1 14 receives two feedback signals, the rectified line input voltage Vx(t) and the link output voltage Vc(t), via a wide bandwidth current loop 1 16 and a slower voltage loop 118. The rectified hne input voltage V-(t) is sensed from node 120 between the diode rectifier 103 and inductor 1 10. The link output voltage Vc(t) is sensed from node 122 between diode 11 1 and load 112. The current loop 1 16
operates at a frequency fc that is sufficient to allow the PFC controller 1 14 to respond to changes in the rectified line input voltage Vx(Q and cause the inductor current iL to track the rectified line input voltage Vx(t) to provide power factor correction. The inductor current ΪL controlled by the current loop 1 16 has a control bandwidth of 5 kHz to 10 kHz. The voltage loop 1 18 operates at a much slower frequency control bandwidth of about 5 Hz to 20 Hz. By operating at 5 Hz to 20 Hz, the voltage loop 1 18 functions as a low pass filter to filter a harmonic ripple component of the link output voltage Vc(t).
(1 1) A number of external components which are outside of PFC controller 114 for respective power factor corrector 100 are still required. For example, a power factor corrector 100 may typically comprise of two Proportional-Integral (PI) controllers, one Pl controller associated with the current loop 1 16 and another Pl controller associated with the voltage loop 1 18. It would be desired and would simplify the circuitry for the power factor corrector 100 if the PI controller associated with the current loop 1 16 could be eliminated. Furthermore, typical power factor corrector 100 does not primarily comprise of digital circuitry. Thus, it is needed and desired to have a power factor corrector which is primarily made up of digital circuitry. It is needed and desired to also minimize the number of external components outside of a PFC controller for a power factor corrector.
SUMMARY OF THE INVENTION
( 12) The present invention provides a power factor correction (PFC) controller and method using a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal.
( 13) In one embodiment of power factor correctors and corresponding methods, a power factor currector (PFC) includes a switch-mode boost stage, a target current generator, a comparator, and a finite state machine. The switch-mode boost stage has a switch and an inductor coupled to the switch. The switch-mode boost stage receives a rectified line input voltage and provides a link output voltage. A sensed current is observed from the switch-mode boost stage. A target current generator receives the link output voltage and generates a target current proportionate to the
rectified line input voltage. A comparator receives a target current value representative of the target current and a sensed current value representative of the sensed current. The comparator outputs a two-level current comparison result signal. A finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
(14) In another embodiment of PFCs and corresponding methods, a power factor corrector (PFC) includes a switch-mode boost stage, a target current generator, a comparator, and a finite state machine. The switch-mode boost stage has a switch and an inductor coupled to the switch. The switch-mode boost stage receives a rectified line input voltage and provides a link output voltage. A sensed current is observed from the switch-mode boost stage. A target current generator receives the link output voltage and generates a target current proportionate to the rectified line input voltage. A ripple current estimator generates a ripple current that estimates a peak-to-peak inductor ripple current. A comparator, responsive to the target current, the ripple current, and the sensed current, outputs a two-level current comparison result signal. A finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
(15) In each of the embodiments, the target current generator, the comparator, and the finite state machine can be taken together to make up a power factor correction (PFC) controller. The PFC controller can be implemented on a single integrated circuit, and the rectified line input voltage and the link output voltage can be correspondingly scaled for operational use by the integrated circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
(16) The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.
(17) Figure 1 (labeled prior art) depicts a power factor corrector.
(18) Figure 2A depicts a preferred embodiment uf a power factor corrector having a switch-mode boost stage and a finite state machine that utilizes a sensed current and a target current in order to adjust the duty cycle of a PWM control signal that controls a switch of the switch-mode boost stage.
( 19) Figure 2B depicts another preferred embodiment of a power factor corrector having a switch-mode boost stage and a finite state machine that utilizes a sensed current and a target current in order to adjust the duty cycle of a PWM control signal that controls a switch of the switch-mode boost stage.
(20) Figure 3 depicts details of an exemplary PFC controller shown in Figures 2A and 2B.
(21) Figure 4 depicts an exemplary finite state machine of Figure 3 that shows details of a digital implementation of a time-based controller.
(22) Figure 5 depicts a high level logical flowchart of the operation of a digital implementation of the time-based controller shown in Figure 4.
(23) Figure 6A depicts exemplary current waveforms of rectified line input current (e.g., average boost inductor current JL) and target current (e.g., itarget) for the power factor correctors of Figures 2 A and 2B shown at a time scale of 10 milliseconds.
(24) Figure 6B depicts exemplary current waveforms ofrectified line input current (e.g., average boost inductor current JL) and target current (e.g., itarget) for the power factor correctors of Figures 2 A and 2B shown at a time scale of 10 microseconds.
(25) Figure 6C depicts exemplary parameters fed into a representative voltage Vx function generator for generating an off-time that is a function of line input voltage
(26) Figures 7Λ depicts a transfer function of the representative voltage Vx function generator of Figure 6C showing the off-time-to-minimum off-time ratio (WtoRmin) being mapped against values of line input voltage (Vx).
(27) Figures 7B depicts a 10 millisecond cycle of line input voltage Vx(t) when the input voltage V;n(t) is operated at a 120 Volt (RMS) Input Voltage Source.
(28) Figure 7C depicts the 10 millisecond cycle of Figure 7B showing the resulting off-time-to-minimum off-time ratios when the transfer function of Figure 7A is applied over the 10 millisecond cycle of line input voltage Vx(t) shown in Figure 7B.
(29) Figures 8A depicts a 10 millisecond cycle of a line input voltage Vx(t) when the input voltage V1n(I) is operated at a 240 Vυlt (RJMS) Input Voltage Source.
(30) Figure 8B depicts the 10 millisecond cycle of Figure 8A showing the resulting off-time-to-minimum off-time ratios when the transfer function of Figure 7A is applied over the 10 millisecond cycle of line input voltage Vx(t) shown in Figure 8A.
(31 ) Figure 9A depicts exemplary current waveforms for a preferred switch control algorithm for the power factor corrector shown in Figure 2A in which the switch current during its on-times is 50% above and 50% below the target current.
(32) Figure 9B depicts exemplary current waveforms for another preferred switch control algorithm for the power factor corrector shown in Figure 2B in which the boost inductor current is 50% above and 50% below the target current.
(33) Figure 10 depicts a state diagram for implementing by the finite state machine shown in Figures 3 and 4 either the preferred switch control algorithm as characterized by the exemplary current waveforms of Figure 9A or the other preferred switch control algorithm as characterized by the exemplary current waveforms of Figure 9B.
(34) Figure 1 1 depicts exemplary curient vvavefoims foi a still further preferred switch control algorithm for the power factor corrector shown in Figure 2A in which on-time of the switch current is determined when the switch current reaches a peak current that is determined by a taiget current and a ripple current.
(35) Figure 12 depicts a state diagram for implementing by the finite state machine shown in Figures 3 and 4 the preferred switch control algorithm as characterized by the exemplary current waveforms of Figure 1 1.
(36) Figure 13 depicts a power factor corrector of Figure 2A coupled to a memory.
(37) Figures HA to 1-iJ depict Mathematica code for an exemplary implementation of the functions of the switch control algorithm as depicted by Figures 9A, 9B, and 10.
(38) Figures 15A to 15J depict Mathematics code for an exemplary implementation of the functions of the switch control technique algorithm as depicted by Figures 11 and 12.
DETAILED DESCRIPTION
(39) A power factor corrector includes a switch-mode boost stage and a.power factor correction (PFC) controller that includes a finite state machine which adjusts the duty cycle of a Pulse Width Modulation (PWM) switching control signal for controlling a control switch of a switch-mode boost stage in accordance with the principles of the present invention. Jn the implementation of this invention (e.g., as shown in Figures 2A and 2B), it is necessary to observe the current (e.g., i[_) in the inductor (inductor 210). Two possible implementations for the current observation will be discussed in detail below. "isenSe" is herein used as a generic term for the observed current. The embodiment of power factor corrector 200A in Figure 2A only observes sensed current isense (e.g., switch current isenseA) when.switch 208 is on. The embodiment of power factor corrector 200B in Figure 2B observes sensed current 'sense (e.g., boost inductor current iscπseβ) all of the time (e.g., whether switch 208 is on or off).
(40) Figure 2 A depicts power factor corrector 200A, and power factor corrector 200A includes a switch-mode boost stage 202A and a PFC controller 214. PFC controller 214 uses a finite state machine to adjust the duty cycle of a PWM switching control signal CSo in accordance with the principles of the present invention. Power factor corrector 202A comprises full-wave diode bridge rectifier 203; capacitor 215; switch-mode boost stage 202A; and PFC controller 214. Switch-mode boost stage 202A further includes inductor 210, diode 21 1, switch 208, and capacitor 206. Power factor corrector 200A implements a high bandwidth current loop 216 and a slower voltage loop 218. A line (mains) voltage source 201 can couple to the input of power factor corrector 200A, and a load 212 can couple to the output of power factor corrector 200A. Power factor corrector 200A operates in the similar manner as power factor 100 as described above earlier except for the manner in which switch 208 is controlled.
(41) In the embodiment of power factor corrector 200A, switching of switch 208 is calculated and performed so that the average current of boost inductor current iι , being the line input current, varies proportionately with the rectified line input voltage Vx(I) where the proportionality ratio is selected such that the capacitor link voltage/output voltage Vf(t) is regulated. The goal of making power factor corrector 200A appear resistive to the voltage source 201 is further accomplished by coupling a sense current resistor 209A in series with switch 208 (e.g., coupled between switch 208 and the negative node of line input voltage Vx(t)). Thus, the sensed current iS).nw in this case is the switch current isenseA- Switch current iscnseA is being utilized to provide PFC control of switch-mode boost stage 202A, and this PFC control will be discussed later when Figure 9A is discussed in more detail. PFC controller 214 also has a finite state machine which is used to adjust the duty cycle of the PWM switching control signal.
(42) PFC controller 214 and its operations and functions can be implemented on a single integrated circuit. A voltage divider comprising resistors Rl and R2 is coupled to the input of the PFC controller 214 where the line input voltage Vx(t) is fed in, and another voltage divider comprising resistors R3 and R4 is coupled to the input of the PFC controller where the link output voltage Vc(t) is fed in. The values for resistors Rl, R2, R3, and R4 are selected so that the voltage dividers scale down the line input voltage Vx(t) and link output voltage Vc(t) to scaled line input voltage Vxιc(t) and scaled link output voltage Vctc(t) that can be used for an integrated circuit. In implementing power factor corrector 200A, the inductor current iL is observed only when switch 208 is on.
(43) Figure 2B depicts another preferred embodiment power factor corrector 200B. Power factor corrector 200B is identical to power factor corrector 200A except that instead of using a switch current resistor 209 A in which switch current
is used to provide PFC control of switch-mode boost stage 202 A, a boost inductor current sense resistor 209B is utilized effectively in series with inductor 210. Boost inductor current isenseβ in this alternate embodiment is used to provide PFC control of switch- mode boost stage 202B, and this PFC control will be discussed later when Figure 9B is discussed in more detail. PFC controller 214 still uses a finite state machine (e.g., finite state machine 304) to adjust the duty cycle of PWM switching control signal
CSo in accordance with the principles of the present invention. PFC controller 214 in power factor corrector 200B and its operations and functions can also be implemented on a single integrated circuit. The voltage dividers comprising the same resistors Rl , R2, R3, and R4 for power factor corrector 200A can be utilized to scale down the line input voltage V,(t) and link output voltage Vc(t) in power factor corrector 200B to scaled line input voltage Vxιc(t) and scaled link output voltage Vcιc(t) that can be used for an integrated circuit. In implementing power factor corrector 200B, the inductor current iL is observed all of the time (e.g., whether switch 208 is on or off).
(44) Typical values for sense resistor 209A or 209B are from 0.05 to 0.5 ohm. The manners of sensing current are certainly not limited to the use of sense resistors or the power factor correctors 200A and 200B disclosed in Figures 2A and 2B. Olher current sense techniques can alternatively include the use of current sense transformers or Hall effect devices.
(45) Figure 3 shows details of an exemplary PFC controller 214 as used in power factor correctors 200A and 200B in respective Figures 2A and 2B. Exemplary PFC controller 214 includes a target current generator 300, a comparator 303, and a finite state machine 304 coupled together in the manner shown in Figure 3. Target current generator 300 includes an analog-to-digital converter (ADC) 320, a multiplier 301, a digital-to-analog converter (DAC) 307, a multiplier 312, a digital proportional- integral (Pl) voltage controller 302, and an ADC 322. Digital PI controller 302 may be a typical Pl controller having a proportional circuit path and an integral circuit path. Integrated Circuit (IC) scaled link output voltage VC|C(t) of slower voltage loop 218 is fed into ADC 322, and the corresponding digital output signal 323 of ADC 322 is fed into the digital Pl voltage controller 302. PI controller 302 preferably is in the form of an Infinite Impulse Response (HR) digital filter. The output of the IIR filter (e.g., Pl output signal 315 from Pl controller 302) is proportionate to the estimated power demand of load 212 to be delivered to switch-mode boost stage 202 A or 202B. PI output signal 315 is fed into multiplier 312. A scaling factor signal 317 that is equivalent to l/V^2 is also fed into multiplier 312. Multiplier 312 multiplies the values from scaling factor signal 317 and Pl output signal 315 and generates scaled digital output voltage signal 309.
(46) ADC 320 receives IC scaled line input voltage VX|C(t) and provides a corresponding digital output signal 319 which is a digital representation of 1C scaled rectified line input voltage VxIcO). Digital output signal 319 is fed into multiplier 301. Multiplier 301 multiplies values of scaled digital output voltage signal 309 by values of digital output signal 319 to provide a digital output product value 350. Digital output product value 350 is fed into DAC 307, and DAC 307 converts the digital output product value 350 into a reference voltage V(i,arge,) that is representative of the target current value (Wget). A sensed current voltage V(i,en«-) (e.g., sensed current value) is a voltage that is representative of a sensed current signal isense, which may be switch current i5CnseA in switch-mode boost stage 202A or boost inductor current i,en«B in switch-mode boost stage 202B. Comparator 303 compares reference voltage V(i,arge,) with sensed current voltage V(isense). Reference voltage V(itargel) corresponds and is proportional to a target current iιargci» which is the desired average inductor current for line input current ii.. Target current iiarget, being proportionate to line input voltage Vx(t), ensures that the line input current ΪL has a high power factor and low distortion. Target current itatgct is a full-wave rectified sinusoidal current waveform as shown in Figures 6A and 6B.
(47) Comparator 303 outputs a voltage comparison result signal 314, which in this example is a two-level current comparison result signal (e.g., "two-level" implying one state υf the comparison, such as above a desired threshold, and another slate of comparison, such as below a desired threshold), and voltage comparison result signal 314 is fed into finite state machine (FSM) 304. Finite state machine 304 processes an FSM algorithm (e.g., switch control algorithm) that adjusts the duty cycle of the PWM switching control signal CSo based on the received voltage comparison result signal 314 to control switch 208 in accordance with the principles of the present invention. One present invention embodiment of the FSM algorithm is controlling or adjusting the switch timing of PWM switching control signal CSo such that the boost inductor current iL is above the target current threshold fifty percent (50%) of the time and below the target current threshold the other fifty percent (50%) of the time. This embodiment of the FSM algorithm will be discussed in more detail when Figures 9A, 9B, and 10 are described later. Another present invention embodiment of the FSM algorithm is controlling or adjusting the switch timing of PWM switching control
signal CSo such that control switch 208 is activated until the boost inductor current iι_ reaches a target current i,arzε, that is equal to a peak current value ipeak determined by iiargct + ΪRIPPLE/2 where ilarget is a target current and IRIPPLE is a peak-to-peak ripple current in the inductor 210. This other embodiment of the FSM algorithm and these current values and equations will be discussed in more detail when Figures 11 and 12 are described later.
(48) The embodiment shown for PFC controller 214 in Figure 3 is exemplary, and there are many possible variations. The multipliers may be analog instead of digital, removing the associated analog-to digital (A/D) and digital-to-analog (D/A) conversion steps. The analog input signals may be currents instead of voltages. The input sine wave may be synthesized by a table look up of function generatυr, and synchronized to the external line. The comparator may be digital, and the current input digitized. In all cases, a current reference signal is generated and compared to the switch-mode current. The comparison is used by a finite state machine (FSM) to control the switch control duty cycle.
(49) With reference now to Figure 4, an exemplary finite state machine (FSM) 304 is illustrated. FSM 304 comprises a time-based controller 410. Exemplary time based controllers are disclosed in pending U.S. Patent Application No. 11/864,366 filed on Sept. 28, 2007 entitled "Time-Based Control of a System Having Integration Response" to John Melanson and assigned to common assignee Cirrus Logic, Inc., Austin, Texas (hereafter the "Time-Based Control patent case"). The Time-Based Control patent case is hereby incorporated by reference.
(50) As indicated by its name, time-based controller 410 implements a time-based control methodology, rather than one of the conventional magnitude -based control methodologies described above. Voltage comparison result signal 314 is received by time calculation logic 422 that, responsive thereto, deteπnines the time at which the state of switch 2Ub should be changed in order to maintain the average value of sensed current signal iscse at the target average value (e.g., target current itargn). Time- based controller 410 includes a pulse-width modulator (PWM) 424 that asserts or deasserts control signal 430 to change the state of switch 208 at the time indicated by time calculation logic 422. Furthermore, an oscillator 432 feeds into FSM 304 and
into time calculation logic block 422. Oscillator 432 is utilized for implementing the desired FSM algorithm.
(51 ) With reference now to Figure 5, there is illustrated a high level logical flowchart of the operation of a digital implementation of the time-based controller 410 υf Figure 4. The illustrated process can be implemented by an application specific integrated circuit (ASIC), general purpose digital hardware executing program code from a tangible data storage medium that directs the illustrated operations, or other digital circuitry, as is known in the art. Further, the illustrated process can be utilized to implement any of the time-based constant period, time-based constant off-time, time-based variable period, or time-based variable off-time control methodologies.
(52) The process shown in Figure 5 begins at block 501 and then proceeds to block 502, which depicts time-based controller 410 asserting control signal CSo (e.g., placing control signal CSo in a first state) to turn on switch 208 and thus begin a time interval A (e.g., time W in Figures 7A and 9). Next, the process iterates at block 504 until comparator 418 indicates that time interval A has ended by signaling that the value of sensed current signal isense has crossed the value of target current itargc, in this case, in a positive transition. The change in relative magnitudes of voltage comparison result signal 314 and sensed current signal ixllM: thus causes a polarity change in the output of comparator 303 indicating (in this embodiment) that sensed current signal i^se is at least as great as target current i(argeι (or in other embodiments, that sensed current signal
is equal to or less than target current imgct)- In response to comparator 303 indicating that sensed current signal i^nse has crossed target current •target in a positive transition, time calculation logic 422 records the duration of time interval A (block 506) based upon the value of a digital counter or timer. Time calculation logic 422 then calculates the duration of time interval B (e.g., time tone in Figures 7A and 9), for example, utilizing one of the equations (e.g., Equation B for calculating the on-time ^..B) that will be later discussed with Figure 10 (block 508).
(53) As shown at blocks 510 and 512, pulse width modulator 424 then detects (e.g., utilizing a digital counter or timer) when the calculated duration of time interval B has elapsed from the time comparator 303 indicating the end of time interval B. In response to a determination that the calculated duration of time interval B has elapsed, pulse width modulator 424 deasserts control signal CSo (e.g., places control signal
CSo in a second state) to turn off switch 208. Pulse width modulator 424 thereafter waits a fixed or variable off time (time interval tOfrin Figures 7A and 9) in accordance with the selected control methodology (block 514) and again asserts the control signal CSo to turn on switch 208 and begin time interval A (e.g., time tonA) of a next cycle of operation, as shown in block 502. The process thereafter proceeds as has been described.
(54) With reference now to Figure 6A, a plot 600 of exemplary current waveforms (in Amps) of line input current (e.g., average boost inductor current ii) and target current iorget for the power factor correctors of Figures 2 A and 2B are shown at a time scale of 10 milliseconds. The exemplary waveforms are viewed from the perspective of the rectified line (mains) rate of exemplary 100 Hz. From this line (mains) rate perspective shown in Figure 6A, the target current imrget is seen as half of a full-wave rectified sinusoidal waveform and is varying or moving. Even though the dark thick lines which represent the current waveform for inductor current JL appear to be solid, they are actually not solid lines and represent that the inductor current iL is moving at a fast rate and thus appears to be a solid line in relative to the current waveform for target current i,argεt. With reference now to Figure 6B, a plot 602 of exemplary current waveforms (in Amps) of line input current (e.g., average boost inductor current iL) and target current (e.g., iIarget) for the power factor correctors of Figures 2A and 2B are shown at a time scale of 10 microseconds. The exemplary waveforms are viewed from the perspective of the switch rate of exemplary 100 kHz (e.g., switch rate for switch 208). From this perspective shown in Figure 6B, the target current iιargei is seen as pseudo-stationary.
(55) Thus, in this specification, the term "switch rate stationary" is defined and understood to mean that a signal is varying at the scale of the line (mains) rate but is treated as stationary or constant at the scale (from the perspective) of the switch rate, particularly for the purposes of implementing the FSM algorithm (e.g., switch control algorithm) of the present invention. This treatment of the signal as stationary is possible since the switch rate is so much greater than the line input rate (on the order of 100 to 1000 times greater). If, for example, the off-time is varied slowly, then the term "switch rate stationary" and its definition and implications still apply. Power factor correctors 200A and 200B which vary the off-time ton- slowly can also be
described as "On-time controlled by Fast Current Feedback (e.g., current loop 216), Off-time controlled by Slow Voltage Feedforward (e.g., Vx)". The slow voltage feedforward does not substantively interfere with the operation of the fast current feedback.
(56) Iu this specification, when operating modes or averages are discussed, the time scale is considered to be at the switch rate unless otherwise specified. Thus, when switch-mode boost stage 202A or 2O2B draws a current proportionate to the line (inaLiib) voltage, it is implied that the curienl is averaged acioss a few cycles of the switch rate. Furthermore, a "constant-off time" mode would imply that the off time is relatively the same within a few switching cycles at the switch rate but may vary at the line (inairib) rale. Variation at lhe line rate may be advantageous to efficiency and Radio Frequency Interference (RFI) mitigation.
(57) The embodiments of power factor correctors 200A and 200B and any other suitable power factor corrector embodiment are able to vary the duty cycle of PWM control signal CSo generally in at least three different methods. The first method, which is the preferred embodiment, is over periodic cycles of sensed current !„„„, to vary the on-time ton of switch 208 (e.g., w and tonB shown in Figures 7A, 7B, and 9) and to maintain the off-time toff of switch 208 (e.g., ton- shown in Figures 7A, 7B, and 9) as a constant. The advantages of this first method of varying the duty cycle is that the mathematical calculations required for implementing such an algorithm is relatively simple, noise is spread over a broad spectrum, and the control provided for PFC controller 214 is stable. For example, calculating an on-time tonB for switch 208 for one of the preferred embodiments simply involves the recurrent equation Tonu' = (ToπD + TonA)/2, and this equation will be discussed in more detail when Figure 10 is later described. The second method is over periodic cycles of sensed current i^^, to maintain the on-time ton of switch 208 (e.g., tonA and ^nB shown in Figures 7A, 7B, and 9) as a constant and to vary the off-time W of switch 208 (e.g., I00- shown in Figures 7A, 7B, and 9). The third method is to maintain the period of sensed current isense constant and to vary the on-time ton and off-time torrof switch 208 accordingly. The third method requires more mathematical calculations but is preferred in some cases where complete control of the switching frequency rate of control signal CSo for switch 208 is needed. In the third method where the period of sensed current isen^ is
held constant, noise in the output 350 of comparator 303 may exist and thus more filtering may be added. An example would be to have filtering that provides the following mathematical relationship for on-time W tone' = % tonβ +- % tonλ'- The W' notation is used to identify the new values from this period of sensed current i«.nse.
(58) Varying the off- time ton from the perspective of the line (mains) rate provides a higher power factor and higher efficiency for switch-mode boost stages 202A and 202B. The off-time tofr is desirably varied across the half period of the input sine period. When the voltage input source is very high (e.g., 240 V), the inductor flyback time (off-time tOβ) can be quite long. An increase of the off-time W is shown in accordance with Figure 7 A. The purpose of varying off-time W is to minimize distortion while maximizing efficiency. At the perspective of the line rate scale (e.g., 10 milliseconds relating to 100 Hz line rate), the off-time toff would be considered "constant" (e.g., not varying rapidly). However, the off-time toff may be varied at the line rate scale to improve performance.
(59) A time duration generator is used to generate a time interval (such as an off- time toff or a switching period for switch 208) that is provided to FSM 304. An exemplary time duration generator is shown as a period function generator 652 in Figure 6C. Period function generator 652 receives the IC scaled rectified line input voltage Vxιc(t). Exemplary parameters are fed into period function generator 652 for generating the time interval that is a function of 1C scaled rectified line input voltage Vχic(t). The exemplary parameters are used to define the characteristics of the period function generator 652. Exemplary parameters fed into the period function generator 652 can include at least inductor value 654 for inductor 210, time interval parameters 656, power level 658, which is the power level relating to Vc detected from capacitor 206, and RMS voltage 660, which is the RMS voltage level Vx across capacitor 215 detected by a RMS voltage detector.
(60) Figure 7A depicts a transfer function of the representative voltage Vx function generator of Figure 6C showing the off-time-to-minimum off-time ratio (toπ/tofrmiτi) being mapped against values of line input voltage (Vx). Figure 7A generally shows how the off-time tofr is varied as a function (such as exemplary piece-wise linear function) of the instantaneous line voltage V,. This function can be chosen to maximize efficiency, and the function can alternatively be a mathematical function or
a lookup table function. This relationship is used to determine for a given input voltage source (E g , 120 Volt or 240 Volt) how the line voltage Vx varies over a given time period and how the ratio of off-time to a minimum off-time toπ/WmiD varies over the same time period. An exemplary Mathematica code implementation of off- time being varied as a piece-wise linear function of the instantaneous line voltage Vx is shown in lines 33 to 38 of Figure 14C.
(61) Figures 7B depicts a line input voltage Vx(t) over a ten (10) millisecond cycle when the input voltage V,n(t) is operated at a 120 Volt (RMS) input voltage source. Figure 7C depicts the same 10 millisecond cycle of Figure 7B showing the resulting off-time-to-minimum off-time ratios when the transfer function of Figure 7A is applied over the 10 millisecond cycle of line input voltage Vx(I) shown in figure 7B. In this example illustrated in Figures 7B and 7C, the value for link output voltage Vc(t) is 400 Volts (e.g., the voltage across link capacitor 206 in Figures 2A and 2B). 1 he maximum peak value for line voltage Vx is equal to 120 Volts (HMS) multiplied V2 (Square Root of 2) which is about 170 Volts. The ratio of off-time to minimum off- time ratio toff/t0π-mm in this case varies from I to 1.3. Therefore, if the minimum off time tofimrn is set to 8 microseconds, then the off time Wat the peak of the input sine wave (e.g., 170 Volts at 5 milliseconds in Figure 7B) would be 10.4 microseconds.
(62) As shown in Figure 7B, graph 702 illustrates the line voltage increasing from 0 V to 170 V over the first 5 ms of the 10 ms period and then decreasing from 170 V to 0 V over the second 5 ms of the 10 ms period. Over this same 10 ms period, Figure 7C shows graph 704 which depicts that the ratio Wtofimiπ stays at 1 for the first couple of milliseconds, rises to 1.3 at 5 ms, falls to 1 over the next couple of milliseconds, and stays at 1 through 10 ms. Figures 7B and 7C are viewed at the line input rate scale, so at that time scale, off-time to/r appears to be varying over an exemplary 10 ms sense cycle. However, at the perspective of the switch rate scale (e.g., 10 microseconds relating to 100 kHz), the off-time toπ- would be considered not to be varying rapidly
(63) Figure 8A depicts a line input voltage Vx(t) over a ten (10) millisecond cycle when the input voltage V,n(t) is operated at a 240 Volt (RMS) input voltage source. Figure 8B depicts the same 10 millisecond cycle of Figure 8A showing the resulting
off-time-to-minimum off-time ratios (WWmin) when the transfer function of Figure 7A is applied over the 10 millisecond cycle of rectified line input voltage Vx(t) shown in Figure 8A. In this example, the value for link output voltage Vc(t) is 400 Volts (e.g., the voltage across link capacitor 206 in Figures 2A and 2B). The maximum peak value for line voltage Vx is equal to 240 Volts (RMS) multiplied Λ/2 (Square Root of 2) which is about 330 Volts. Furthermore, in this example, with the minimum off-time ton™,, being still 8 microseconds, the maximum off-time W is 24 microseconds. Thus, the ratio of off-time to minimum off-time ratio toffΛoftmin can vary from 1 to 3.
(64) Figures 8A and 8B are viewed at the line input rate scale, so at that time scale, oflT-tiine lOff appears Io be varying over an exemplary 10 ms cycle. However, ai the perspective of the switch rate scale (e.g., 10 microseconds relating to 100 kHz line rate), the off-time W would be considered not to be varying rapidly.
(65) With reference now to Figure 9A, exemplary waveforms of the switch current •scnscA and target current i,argc, are shown at the switch rate scale for a preferred exemplary control technique of control switch 208. Target current itargei is considered and viewed as switch rate stationary relative to switch current isenseA- Switch current iscnscA is shown during the on-times of switch current as being fifty percent (50%) above (e.g., above-time duration) and fifty percent (50%) below (e.g., below-time duration) the target current itargw- With reference now to Figure 9B, exemplary waveforms of the boost inductor current iscnsco and target current iiargei are shown at the switch rate scale. Target current iIargc, is considered and viewed as switch rate stationary relative to boost inductor current ijenscβ- Boost inductor current iscseB is shown during the on-times of switch current as being fifty percent (50%) above and fifty percent (50%) below the target current i^^ during a switching period (e.g., tonA + tone + ton) The waveforms in Figures 9A and 9B help illustrate an exemplary control technique that would be implemented by an FSM algorithm for FSM 304.
(66) As previously indicated, switch current isenseA in switch-mode boost stage 202 A and boost inductor current isen∞B in switching power converter 202B may be generically referred to as sensed current signal isen«- Time-based controller 410 is used to adjust the switch timing such that the sensed current isense (e.g., switch current isenseA or boost inductor current isenseβ) is above the target current (iurget) threshold fifty
percent (50%) of the on-time t<,n of switch 208 and below the target current (itargeύ threshold the other fifty percent (50%) of the on-time ton, and the FSM algorithm (e.g., switch control algorithm) treats the target current itarget as being switch rate stationary relative to sensed current isense-
(67) The boost inductor current ii_ comprise approximately linear ramps, and these linear ramps ensure that the average current of boost inductor current iL (e.g., line input current) tracks the target current ilargci. In this exemplary control technique embodiment, the first method of varying duty cycle is implemented in which the on- time ton of switch 208 (e.g., UIA and tonβ shown in Figures 7A, 7B, and 9) is varied and the off-time tonr is considered to be maintained as a constant over periodic cycles of sensed current i^^ when viewed at the switch rate scale. Thus, this control technique only requires the sensed current ixnιx be sensed when switch 208 is activated or "ON", making it compatible with the sense resistor 209A of Figure 2A and sense resistor 209B of Fig. 2B. Because time-based controller 410 enables control of the switch timing for switch 208 as described above, a Pl controller associated with current loop 216 is not needed or required, and thus complexity of the circuit for power factor correctors 200A and 200B can be simplified.
(68) With reference now to Figure 10, a state diagram 1000 is shown for the FSM 304 shown in Figures 3 and 4. State diagram 1000 shows how the FSM algorithms (e.g., switch control algorithms) are implemented for the embodiments of power factor correctors 202Λ and 202B. Figures 9Λ, 9B, and 10 are now discussed together. A timer is implemented with an oscillator 432 and a digital counter in which the clock from oscillator 432 drives the clock input of the counter. A digital counter with a preset and up/down count is well known in the art.
(69) State diagram 1000 shows that for this preferred control technique embodiment, FSM algorithm moves to a state SO in which the digital counter is reset. At state SO, switch 208 is on, and a count value TonA is started. Count value TOTA is used to determine and track the lapsed time for on-time tonA of switch 208. Sensed current i^^ is compared with target current it3Iget by comparator 303 comparing sensed current voltage V(isense) with reference voltage V(iL) which corresponds to a target current itaiκei. While sensed current ivπv continues to be less than target current
'target, then new count value T0nA5 is used to calculate an updated count value for T0nA by adding one (I) to the current value of T0nA. that is,
(70) TonA' = TonA +l Equation A
(71) The count value T0nA is then captured in a latch when comparator 303 changes state, that is, when sensed current We becomes greater than or equal to target current i,ar&a- Count value T0n D is used to determine and track the lapsed time for on-time
of switch 208. New count value T0nB' is calculated by adding the old count value T0nB with the captured count value TonA and dividing this sum by two (2) for providing an updated on-time tons, that is,
(72) TonB' = (TonB + TonAy2 Equation B
(73) The digital counter is then reset.
(74) The FSM algorithm moves to state Sl in which switch 208 is still on while the timer tracks whether the current count value T0nB has been reached, which reflects the updated on-time tnnR having lapsed. When the count value T0nR has been reached, FSM algorithm then moves to state S2 in which the switch 208 is off. Digital counter is then reset again. A count value TO(r is used to determine and track the lapsed time for off-time Wof switch 208, and the count value TO(r is determined as a function of the line input voltage Vx(t). When the digital counter reaches the count value Ton, FSM algorithm loops back to state SO and repeats thereafter. In parallel with the execution of the FSM algorithm in accordance with the state diagram 1000, voltage loop 218 is updated at the line rate (e.g., 100 Hz or 120 Hz).
(75) With reference now to Figure 1 1 , exemplary waveforms of the switch current isenseA, which ib the switch current in Figure 2A, and a peak current ipEAK is bhυwn at the switch rate scale for another preferred exemplary control technique of control switch 208. Target current imrset is calculated proportionate to the line input voltage Vx(I) as discussed in the previous embodiment, and peak current ipEAK is considered and viewed as switch rate stationary relative to switch current isenseA. Switch current isenseA is shown as ramping up by switch 208 being turned on until.switch current isenseA reaches the peak current JPEAK- When switch current isenseA reaches peakxurrent ipEAK, switch 208 is then turned off for an off-time period X0^.
(76) Ripple current itiippLE is calculated as the difference between the minimum and maximum values of the inductor current iL over one period. The peak-to-peak inductor ripple current ΪRIPPLE is calculated as the off-time W multiplied by the difference of scaled link output voltage Vc(t) and line input voltage Vx(t) divided by the i nductance value L of inductor 210, that is:
(77) JR1PPLE = toff * (Vc(I) - Vx(t))/L Equation C
(78) The desired peak current in the inductor is:
(80) Thus, if the inductor value L is known to a reasonable accuracy, then the peak current ipbAK. can be controlled. Thus, the inductor value L may be determined by run-time measurement. For example, if the time is measured for the switch current isenseA to go from target current i,arget to
then the inductance value can be determined as Vx(t) * (delta time / delta current).
(81) With reference now to Figure 12, state diagram 1200 shows that for this preferred control technique embodiment, FSM algorithm moves to a state SO in which switch 208 is on. State diagram 1200 then depicts that FSM algorithm waits until the condition in which peak current JPBAK is greater than the sum of the target current
and ripple current imppLE divided by two (2), that is,
(82) lsense > target + iRippLE/2 Equation E
(83) When the above condition is met, then FSM algorithm shown in state diagram 1200 moves to state S l in which switch 208 is turned on. FSM algorithm then waits a "constant" off-time (as discussed earlier) and then goes back to state SO and repeats thereafter.
(84) Exemplary waveforms in higures 7A, 7B, 7C, 8 A, 8B, 9 A, 9B, 10, 11, and 12 define the functions and operations of the control technique algorithms for controlling switch 208. The characteristics of these functions and operations determine the operating behavior of and operating frequencies for the power factor correctors 200A and 200B. As such, it is desirable to allow configuration of the operating parameters for different applications. In the preferred embodiment, the parameters are stored in digital registers which can be loaded from an external memory. For example, a read-
only memory (ROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a flash memory, or a one-time programmable (OTP) memory may be used to store the chosen values, and these. values are loaded into the digital registers at power up of the power factor correctors 200A or 200B. Default values for at least some of the registers may be set. The programming of the memories allow for the configuration of different applications for a programmable power factor corrector.
(85) Exemplary programmable power factor correctors are discussed and disclosed in pending U.S. Patent Application No. 11/967,275 filed on December 31 , 2007 entitled "Programmable Power Control System" to John Melanson and assigned to common assignee Cirrus Logic, Inc., Austin, Texas (hereafter the "Programmable Power Control Systems patent case"). The Programmable Power Control Systems patent case is hereby incorporated by reference.
(86) Figure 13 depicts an exemplary power factor corrector 200A which incorporates a memory 1300 that is coupled to PFC controller 214. Memory 1300 stores operational parameters, such as the exemplary parameters (e.g., inductor value 654, time interval (such as off-time tofror sensed current period parameters 656, power level 658, RMS level 660) for defining the transfer function of voltage Vx function generator 652. In at least one embodiment, memory 1300 is a nonvolatile storage medium. Memory 1300 can be, for example, a read/write memory, a one time programmable memory, a memory used for table lookup, or a loadable register. How and when the PFC operational parameters are loaded into and accessed from memory 1300 is a design choice.
(87) Figures 14A to 14J depict Mathematica code (i.e., Mathematica is an engineering computer program developed by Wolfram Research in Champaign, Illinois) for an exemplary implementation of the functions of the control technique algorithm as depicted by Figures 9A, 9B, and 10. Figures 15A to 15J depict Mathematica code for an exemplary implementation of the functions of the control technique algorithm as depicted by Figures 11 and 12.
(88) Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto
without departing from the spirit and scope of the invention as defined by the appended claims.
Claims
WHAT IS CLAIMED IS:
L A power factor corrector (PFC), comprising: a switch-mode boost stage having a switch and an inductor coupled to the switch wherein the switch-mode boost stage receives a rectified line input voltage and provides a link output voltage and wherein a sensed current is observed from the switch-mode boost stage; and a target current generator for receiving the link output voltage and for generating a target current proportionate to the rectified line input voltage; a comparator for receiving a target current value representative of the target current and a sensed current value representative of the sensed current and outputting a two-level current comparison result signal; and a finite state machine responsive to the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
2. The PFC of Claim 1 , wherein the sensed current is a switch current of the switch.
3. The PFC of Claim 2 wherein the finite state machine generates the switch control signal such that the switch current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.
4. The PFC of Claim 1 wherein the sensed current is a boost inductor current in the inductor.
5. The PFC of Claim 4 wherein the finite state machine generates the switch control signal such that the boost inductor current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.
6. The PFC of Claim 1 further comprising a timer which is utilized by the finite state machine for measuring a below-time duration in which the sensed current is less than the target current and adjusting the duty cycle of the switch control signal in conformity with the below-time duration.
7. The PFC of Claim 6 further comprising a time duration generator which receives a signal representative of the rectified line input voltage and adjusts an off-time duration of the switch in conformity with the below-time duration.
8. The PFC of Claim 7 further comprising a detector for detecting a RMS voltage of the line input voltage and wherein the time duration generator receives and uses the RMS voltage to responsively determine the off-time duration.
9. The PFC of Claim 7 wherein a power level is detected from the link output voltage and wherein the time duration generator receives and uses the power level to responsively determine the off-time duration.
10. The PFC of Claim 6 further comprising a time duration generator which receives a signal representative of the rectified line input voltage and adjusts a switching period for the switch in conformity with the below-time duration.
1 1. The PFC of Claim 10 further comprising a detector for detecting a RMS voltage of the line input voltage and wherein the time duration generator receives and uses the RMS voltage to responsively determine the switching period.
12. The PFC of Claim 10 wherein a power level is detected from the link output voltage and wherein the time duration generator receives and uses the power level to responsively determine the switching period.
13. The PFC of Claim 6 wherein the finite state machine calculates an on-time duration based on a recurrence relation responsive to a prior on-time duration and the below-time duration.
14. The PFC of Claim 6 wherein the timer further comprises: an oscillator; and a digital counter that counts responsively to the oscillator and the two-level current comparison result signal; and wherein the switch control signal controls the switch in response to the digital counter.
15. The PFC of Claim J wherein the target current generator, the comparator, and the finite state machine are incorporated into a single integrated circuit.
16. The PFC of Claim 15 wherein the integrated circuit-further comprises a timer that includes an oscillator and a counter.
17. A method for power factor correction (PFC), comprising: coupling a switch and an inductor together to form a switch-mode boost stage that receives a rectified line input voltage and provides a link output voltage; observing a sensed current from the switch-mode boost stage; receiving a link output voltage; generating a target current proportionate to the rectified line input voltage; comparing a target current value representative of the target current and a sensed current value representative of the sensed current; in response to the comparing, outputting a two-level current comparison result signal; and in response to the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
18. The method of Claim 17, wherein sensing a sensed current from the switch-mode boost stage further comprises: sensing a switch current of the switch.
19. The method of Claim 18 wherein generating a switch control signal further comprises: generating the switch control signal such that the switch current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.
20. The method of Claim 17 wherein sensing a sensed current from the switch-mode boost stage further comprises: sensing a boost inductor current in the inductor.
21. The method of Claim 20 wherein generating a switch control signal further comprises: generating the switch control signal such that the boost inductor current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.
22. The method of Claim 17 further comprising: measuring a below-time duration in which the sensed current is less than the target current; and adjusting an on-time duration of a switching time period for the switch in conformity with the below-time duration.
23. The method of Claim 22 further comprising: adjusting an off-time duration of the switch in conformity with the below-time duration.
24. The method of Claim 22 further comprising: adjusting a switching period for the switch in conformity with the below-time duration.
25. The method of Claim 22 further comprising: calculating an on-time duration of the switch based on a recurrence relation responsive to a prior on-time duration and the below-time duration.
26. An integrated circuit which incorporates a power factor correction coatroller that includes a target current generator, a comparator, and a finite state machine, the integrated circuit configured to: receive a signal representative of a rectified line input voltage; observe a sensed current from an external, switch-mode boost stage; receive another signal representative of a link output voltage; generate α target current proportionate to the input signal; compare a target current value representative of the target current and a sensed current value representative of the sensed current; in response to the compare, output a two-level current comparison result signal; and in response to the two-level current comparison result signal, generate a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
27. A power factor corrector (PFC), comprising: a switch-mode boost stage having a switch and an inductor coupled to the switch wherein the switch-mode boost stage receives a rectified line input voltage and provides a link output voltage and wherein a sensed current is observed from the switch-mode boost stage; and a target current generator for receiving the link output voltage and for generating a target current proportionate to the rectified line input voltage; a ripple current estimator for generating a ripple current that estimates a peak- to-peak inductor ripple current; a comparator, responsive to the target current, the ripple current, and the sensed current, for outputting a two- level current comparison result signal; and a finite state machine responsive to the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
28. The PFC of Claim 27, wherein the finite state machine turns on the switch for an on-time duration starting when the sensed current is less than a sum of the target current and half of the ripple current and the finite state machine turns off the switch for an off-time duration starting when the sensed current is greater than or equal to a sum of the target current and half of the ripple current.
29. The PFC of Claim 27 wherein the off-time duration is adjusted in conformity with the ripple current.
30. The PFC of Claim 27 further comprising a timer that includes an oscillator and a counter wherein the timer is utilized by the finite state machine to measure an on-time duration and an off-time duration of the switch.
31. The PFC of Claim 27 wherein the target current generator, the comparator, and the finite state machine are incorporated into a smgle integrated circuit.
32. A method for power factor correction (PFC), comprising: coupling a swilch and an inductor lugelher to form a switch-mude boosl stage that receives a rectified line input voltage; observing a sensed current from the switch-mode boost.stage; receiving a link υulpul vυllage; generating a target current proportionate to the rectified line input voltage; generating a ripple current that estimates a peak-to-peak inductor ripple current, in response to the target current, the ripple current, and the sensed current, generating a two-level current comparison result signal; and in response lυ the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.
33. The method of Claim 32, wherein generating a switch control signal further comprises: turning on the switch for an on-time duration starting when the sensed current is less than a sum of the target current and half of the ripple current; and turning off the switch for an off-time duration starting when the sensed current is greater than or equal to a sum of the target current and half of the ripple current.
34. The method of claim 33 further comprising: adjusting the off-time duration in conformity with the ripple current.
35. An integrated circuit which incorporates a power factor correction controller that includes a target current generator, a comparator, and a finite. state machine, the integrated circuit configured to: receive a signal representative of a rectified line input voltage; observe a sensed current from an external switch-mode boost stage; receive another signal representative of a link output voltage; generate a target current proportionate to the rectified line input voltage; generate a ripple current that estimates a peak-to-peak inductor ripple current; in response to the target current, the ripple current, and the sensed current, generate a two-level current comparison result signal; and in response to the two-level current comparison result signal, generate a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such tliat power factor correction is performed.
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CN2008800230275A CN101743683B (en) | 2007-05-02 | 2008-04-22 | Power factor correction (PFC) controller and method using finite state machine to adjust duty cycle of PWM control signal |
AT08746551T ATE495569T1 (en) | 2007-05-02 | 2008-04-22 | CONTROL FOR POWER FACTOR CORRECTION WITH AN AUTOMATIC MACHINE FOR ADJUSTING THE DUTY RATIO OF A PWM CONTROL SIGNAL |
DE602008004510T DE602008004510D1 (en) | 2007-05-02 | 2008-04-22 | CONTROL FOR POWER FACTORY CORRECTION WITH AN AUTOMATING DEVICE FOR SETTING THE CONTINUOUS RATIO OF A PWM CONTROL SIGNAL |
EP08746551A EP2153511B1 (en) | 2007-05-02 | 2008-04-22 | Power factor correction controller comprising a finite state machine to adjust the duty cycle of a pwm control signal |
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PCT/US2008/062387 WO2008137656A2 (en) | 2007-05-02 | 2008-05-02 | Power factor correction controller with feedback reduction |
PCT/US2008/062428 WO2008137684A1 (en) | 2007-05-02 | 2008-05-02 | Switching power converter with efficient switching control signal period generation |
PCT/US2008/062423 WO2008137679A1 (en) | 2007-05-02 | 2008-05-02 | Switching power converter with switch control pulse width variability at low power demand levels |
PCT/US2008/062378 WO2008137652A1 (en) | 2007-05-02 | 2008-05-02 | Power factor correction controller using a nonlinear delta- sigma modulator |
PCT/US2008/062384 WO2008137655A1 (en) | 2007-05-02 | 2008-05-02 | Control system using a nonlinear delta-sigma modulator with nonlinear process modeling |
PCT/US2008/062381 WO2008137654A1 (en) | 2007-05-02 | 2008-05-02 | System and method with inductor flyback detection using switch gate charge characteristic detection |
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PCT/US2008/062423 WO2008137679A1 (en) | 2007-05-02 | 2008-05-02 | Switching power converter with switch control pulse width variability at low power demand levels |
PCT/US2008/062378 WO2008137652A1 (en) | 2007-05-02 | 2008-05-02 | Power factor correction controller using a nonlinear delta- sigma modulator |
PCT/US2008/062384 WO2008137655A1 (en) | 2007-05-02 | 2008-05-02 | Control system using a nonlinear delta-sigma modulator with nonlinear process modeling |
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