DE102012108011A1 - Switching circuit for controlling switch in switching converter, has control circuit that provides control signal, on basis of generated synchronization signal, for controlling switch in switching converter - Google Patents

Abstract

The switching circuit (400) has detection circuit (406) that compares an input voltage (V in) with predetermined voltage value (404), and generates pulse signal when the input voltage drops below predetermined voltage value. A signal generating circuit (412) coupled to the detection circuit is configured to generate synchronization signal (I sync) based on generated pulse signals. A control circuit is configured to provide control signal, on basis of generated synchronization signal, for controlling switch in switching converter. An independent claim is included for a method for controlling a switch in switching converter.

Description

Various embodiments relate to a circuit for driving a switch in a switching converter.

Nowadays, switching converters / switching power supplies are equipped with a power factor correction to optimize the devices in such a way that they make the best possible use of the provided power. In general, a poor power factor, i. H. a high acceptance of the reactive power, with electrical appliances the result is that more RMS current than actually needed must be supplied.

Typically, power factor correction switching power supplies have a dual loop structure, namely, an external voltage control loop and an internal current loop. The external voltage control loop may be used to maintain the DC voltage output by the switching power supply at a predetermined value, for example 400V. The output value of the external voltage control loop may reflect the power requirements of connected loads. When this output value is multiplied by a synchronization signal, the reference signal for the inner current control circuit can be obtained. The synchronization signal usually corresponds to a rectified sine signal and is in phase with the input voltage which is supplied to the switching power supply. The task of the inner current control circuit is to form the input current into the switching power supply so that it has a sinusoidal waveform as pure as possible and is also in phase with the AC voltage, which is applied to the input of the switching power supply. The goal of this measure is the optimization of the power factor, which should be as close to one as possible.

A known power factor correction problem that can arise with boost converters, for example, is that the DC voltage output from the switch mode power supply will oscillate at a frequency of 100 Hz (first harmonic to fundamental) in the case of a 50 Hz supply voltage, or harmonics in the case of a 60 Hz supply voltage with a frequency of 120 Hz. This first harmonic should be eliminated from the voltage control loop so that it can provide a "clean" reference signal to the current loop. Since this first harmonic at twice the fundamental frequency is a very low frequency component, it can not simply be filtered out without sacrificing the control bandwidth of the voltage control loop. In a low-pass filter, which provides a correspondingly good suppression of frequencies in the range of 100 Hz, could be expected with a cutoff frequency in the range of about 10 Hz to 20 Hz, which can then also be considered as an upper bound for the control bandwidth of the overall control loop.

Another problem may arise in connection with the regulation of the input current. Most Power Factor Correction applications assume that the input voltage is a pure 50 Hz or 60 Hz monofrequency sinewave signal, without any distortion or distortion in the form of other frequency components being mixed. However, the supplied AC supply voltage may, for example, in plants and laboratories equipped with a variety of high power electronic devices, deviate from a pure sinusoidal waveform and be contaminated with spurious frequencies, such as higher harmonics, such as even harmonics, second, fourth and third or sixth order (ie third, fifth and / or seventh order odd harmonics). In such an AC environment, the operation of existing power integrated circuit (IC) ICs may be compromised, so that a sufficiently low total harmonic distortion (THD) of the input current may not be achieved at a power factor of one. As a result, corresponding switching converters / switched-mode power supplies can not meet the standards required by the market, for example the requirements of class D of the IEC standard (International Electrotechnical Commission).

According to the prior art, the first harmonic in the output voltage of a switching converter / switching power supply can be eliminated by using a first-order low-pass filter so that in the case of a 50 Hz power supply voltage the first harmonic can be filtered out at 100 Hz. However, the addition of a low-pass filter can significantly reduce the available control bandwidth of the outer voltage control loop, for example to about 10 Hz to 20 Hz. As a result, the dynamic / transient response of the overall system can be very slow. In other words, the dynamic range can be very small.

In order to improve the dynamic / transient response behavior, the low-pass filter can be replaced, for example, by a notch (second notch) filter which, in the case of a 50 Hz supply voltage, can filter out the second harmonic at 100 Hz, without the Control bandwidth is impaired. However, the notch filter requires a sophisticated design and / or design process to properly adjust the sampling frequency and feedback parameters of the notch filter, which is by no means a simple task.

For power factor correction circuits operating under non-ideal environmental conditions, such as distorted or noisy AC supply voltages, there is no commercially available power factor correction IC available which can solve the distortion problem of the input current just discussed. In general, the degree of distortion of the input current depends on the quality, that is about the signal purity, the AC input voltage of the switching converter / switching power supply.

In view of the above, it would be desirable to provide a circuit and / or method that can solve the described problems with respect to the external voltage control loop and the internal current loop.

In various embodiments, a circuit is provided for driving a switch in a switching converter, the circuit comprising: a detection circuit which may be configured to compare an applied input voltage with a predetermined voltage value and generate a pulse signal when the input voltage is below the predetermined one Voltage value drops; a signal generation circuit coupled to the detection circuit and configured to generate a synchronization signal based on the pulse signals generated by the detection circuit; and a control circuit that may be configured to provide a control signal to the switch based on the synchronization signal.

According to various embodiments, the switching converter (also referred to as switching power supply) may be a circuit which can provide a regulated DC voltage from an input voltage, which may be a (unregulated) DC or AC voltage. In this case, the underlying switching converter having at least one switch which can control a current flow in the switching converter. The switching converter can have a galvanically isolated topology and can be configured, for example, as a single-ended flow converter, a push-pull flow converter or a flyback converter or it can have a galvanically non-isolated topology and be configured, for example, as an up-converter or a down-converter. However, the switching converter may also have a different topology than those just enumerated by way of example.

According to further embodiments of the circuit, the input voltage may be a rectified AC voltage.

According to further embodiments, the circuit may further comprise a sampling circuit which is connected between an input of the circuit and the detection circuit and is adapted to sample the applied input voltage. The sampling circuit may be used to provide analog-to-digital conversion.

According to further embodiments of the circuit, the sampling circuit may comprise a sample and hold circuit, for example a zero-order sample-and-hold gate.

According to further embodiments of the circuit, the detection circuit may comprise a comparator which is adapted to compare the applied input voltage with the predetermined voltage value. The comparator can take on the role of a threshold detector, for example, where it can detect when the applied voltage falls below the threshold, which is defined by the predetermined voltage value.

According to further embodiments of the circuit, the signal generation circuit may be configured to generate a rectified sine signal as the synchronization signal.

According to further embodiments of the circuit, the signal generating circuit may be configured to generate a synchronization signal whose period corresponds to a time interval of two consecutive pulse signals.

According to further embodiments of the circuit, the period of the synchronization signal may be equal to the period of the input voltage. The input voltage may, for example, have the usual mains supply frequencies of 50 Hz or 60 Hz.

According to further embodiments, the circuit may further comprise an integrator connected between the detection circuit and the signal generation circuit and arranged to integrate the time between two consecutive pulse signals to generate a ramp signal; and wherein the control circuit may be configured based the ramp signal to provide the control signal for the switch.

According to further embodiments of the circuit, the integrator may be arranged to reset the ramp signal when receiving the pulse signal from the detection circuit.

According to further embodiments of the circuit, the signal generation circuit may have stored a value table and be configured to generate the synchronization signal from the ramp signal based on the value table.

According to further embodiments, the circuit may further comprise a driver circuit coupled to the control circuit and configured to generate a drive signal for the switch based on the control signal.

According to further embodiments of the circuit, the drive signal may be a pulse width modulated signal.

According to further embodiments, the circuit may further comprise a first sub-circuit, which may be configured at its output to provide a sum signal from a signal applied to its first input and from a signal applied to its second input, the first input being coupled to the control circuit is and the output is coupled to the driver circuit. The first sub-circuit may, for example, be configured as an adder.

According to further embodiments, the circuit may further comprise a matching circuit coupled to the second input of the first sub-circuit and configured to generate a matching signal for adjusting the control signal based on a ratio of the input voltage applied in the switching converter and an output voltage of the control circuit switching converter.

According to further embodiments, the circuit may further comprise a multiplier circuit, which is connected between the signal generating circuit and the control circuit and is arranged to multiply the synchronization signal with a control signal.

According to further embodiments, the circuit may further comprise a second sub-circuit whose first input is coupled to an output of the multiplier circuit, the output of which is coupled to the control circuit and which is adapted to receive at its second input a signal corresponding to that through the Switching converter represents flowing current and output at its output a differential signal of the two input signals. The second sub-circuit may be configured as a subtracting circuit.

According to further embodiments, the circuit may further comprise: an input to which an output voltage of the switching converter is supplied as an input signal; a delay circuit configured to delay the signal applied thereto which is dependent on the input signal to delay a time corresponding to one-half of a period of a spurious oscillation in the input signal, thereby generating a delayed input signal; a third sub-circuit configured to add the delayed input signal and the input signal to output a composite input signal; and a fourth sub-circuit coupled to the first sub-circuit and configured to subtract the composite input signal from a setpoint signal of the output voltage of the switching converter and output the control signal. The third sub-circuit may be configured as an adder, the fourth sub-circuit may be configured as a subtracting circuit.

In various embodiments, there is further provided a circuit arrangement comprising a switching converter having at least one switch configured to allow current to flow through the switching converter and a switching circuit coupled to the switching converter according to various embodiments, wherein the circuit is coupled to the switch such that this is controlled on the basis of the control signal.

In various embodiments, there is provided a method of providing a control signal to a switch in a switching converter, the method comprising: determining a voltage present in the switching converter; Comparing the voltage present in the switching converter with a predetermined voltage value; Generating a pulse signal when it is determined that the voltage applied in the switching converter voltage falls below the predetermined voltage value; Generating a synchronization signal based on the generated pulse signals; and generating a control signal for the switch based on the synchronization signal.

According to further embodiments of the method, the voltage applied to the switching converter Voltage be a rectified input voltage of the switching converter.

According to further exemplary embodiments of the method, the determination of the voltage present in the switching converter can comprise a sampling of a value of the voltage present in the switching converter and a holding of the sampled value.

According to further embodiments of the method, generating the synchronization signal may comprise generating a rectified sine signal.

According to further embodiments of the method, the rectified sine signal may have a period which corresponds to a time interval between two successive pulse signals.

According to further embodiments of the method, generating the synchronization signal may comprise generating a ramp signal.

According to further embodiments of the method, the ramp signal may be reset from the pulse signal.

According to further embodiments of the method, the synchronization signal may be generated from the ramp signal using a look-up table.

According to further embodiments of the method, the control signal can be formed by subtracting from the synchronization signal a signal which corresponds to a current flowing through the switching converter.

According to further embodiments, the method may further comprise generating a drive signal for the switch based on the control signal.

According to further embodiments of the method, the drive signal can be formed by adjusting the control signal according to a ratio of the rectified input voltage in the switching converter and its output voltage.

According to further embodiments of the method, the drive signal may comprise a pulse width modulated signal.

According to further embodiments, the method may further comprise adjusting the amplitude of the synchronization signal according to a control signal, which is formed from a difference between a desired value of the output voltage and the current value of the output voltage of the switching converter.

According to further embodiments of the method, generating the actuating signal may comprise: determining an output voltage signal based on an output voltage of the switching converter; Delaying the output voltage signal by a period corresponding to one-half of a period of a parasitic oscillation of the output voltage signal; Adding the delayed output voltage signal to the output voltage signal to provide a composite output voltage signal; Subtracting the combined output voltage signal from a setpoint signal of the output voltage of the switching converter, so that the actuating signal is provided.

In various other embodiments, a circuit for driving a switch is provided in a switching converter, wherein the circuit may comprise: an input to which an output voltage of the switching converter is supplied as an input signal; a delay circuit, which may be configured to delay the signal supplied thereto, which is dependent on the input signal, to delay a time corresponding to one-half of a period of a spurious oscillation in the input signal, so that a delayed input signal is generated; a first sub-circuit which may be configured to add the delayed input signal and the input signal to output a composite input signal; a second sub-circuit coupled to the first sub-circuit and configured to subtract the composite input signal from a reference signal of the output voltage of the switching converter and output an actuating signal; and a control circuit configured to provide a control signal to the switch based on the control signal. The first sub-circuit may be configured as an adder, the second sub-circuit may be configured as a subtracting circuit.

According to further embodiments, the circuit may further comprise a scaling circuit configured to scale the amplitude of the input signal so that a scaled input signal is generated and supplied to the delay circuit, wherein the delay circuit may be configured to delay the scaled input signal by the time and thereby form a delayed scaled input signal, wherein the first sub-circuit may be configured to add the delayed scaled input signal and the input signal.

According to further embodiments of the circuit, the scaling circuit may be configured to halve the amplitude of the input signal.

According to further embodiments, the circuit may further comprise a sense circuit connected between the input and the scaling circuit and configured to sample the input signal and provide the sampled input signal to the first sub-circuit and the delay circuit. The sampling circuit may be used to provide analog-to-digital conversion.

According to further embodiments of the circuit, the sampling circuit may comprise a sample and hold circuit, for example a zero-order sample-and-hold gate.

According to further embodiments of the circuit, the spurious vibration in the input signal may be a first harmonic.

According to further embodiments, the circuit may further comprise a regulator, which is connected between the second sub-circuit and the control circuit and is adapted to generate from the control signal, a regulated control signal.

According to further embodiments of the circuit, the controller may be configured as a proportional-integral controller.

According to further embodiments, the circuit may further comprise a driver circuit coupled to the control circuit and configured to generate a drive signal for the switch based on the control signal.

According to further embodiments of the circuit, the drive signal may be a pulse width modulated signal.

According to further embodiments, the circuit may comprise a third sub-circuit which may be configured at its output to form a sum signal from a signal applied to its first input and from a signal applied to its second input, the first input being coupled to the control circuit is and the output is coupled to the driver circuit. The third sub-circuit may be configured as an adder.

According to further embodiments, the circuit may further comprise a matching circuit coupled to the second input of the third sub-circuit and configured to generate a matching signal for adjusting the control signal based on a ratio of the voltage applied in the switching converter and an output voltage of the switching converter ,

According to further embodiments, the circuit may further comprise a multiplier circuit which is connected between the second sub-circuit and the control circuit and is arranged to multiply the control signal with a synchronization signal.

According to further embodiments, the circuit may further comprise a fourth sub-circuit whose first input is coupled to the output of the multiplier circuit, whose output is coupled to the control circuit and which is arranged to receive at its second input a signal corresponding to that through the Switching converter represents current flowing, and output at its output a differential signal of the two input signals. The fourth sub-circuit may be configured as a subtracting circuit.

According to further embodiments, the circuit may further comprise a detection circuit which may be configured to compare an applied input voltage with a predetermined voltage value and generate a pulse signal when the input voltage falls below the predetermined voltage value and a signal generation circuit coupled to the detection circuit and configured to generate the synchronization signal based on the pulse signals generated by the detection circuit.

In various embodiments, a circuit arrangement is provided that includes a switching converter having at least one switch configured to allow current flow through the switching converter and a switching circuit coupled to the switching converter according to various embodiments, wherein the circuit is coupled to the switch such that this is controlled on the basis of the control signal.

In various embodiments, there is provided a method of providing a control signal to a switch in a switching converter, the method comprising: determining an output voltage signal based on an output voltage of the switching converter; Delaying the output voltage signal by a period of time equal to one-half of a period of a parasitic oscillation of the output voltage signal corresponds; Adding the delayed output voltage signal to the output voltage signal to provide a composite output voltage signal; Subtracting the combined output voltage signal from a setpoint signal of the output voltage of the switching converter to provide an actuating signal, and generating a control signal for the switch based on the actuating signal.

According to further embodiments of the method, the amplitude of the output voltage signal may be scaled by halving the amplitude.

According to further embodiments, the method may further comprise generating a controlled actuating signal from the actuating signal by means of a regulator.

According to further embodiments of the method, the controlled control signal can be generated by means of a proportional-integral controller.

According to further embodiments of the method, a signal which corresponds to a current flowing through the switching converter can be subtracted from the actuating signal when generating the control signal.

According to further embodiments, the method may further comprise generating a drive signal for the switch based on the control signal.

According to further embodiments of the method, the drive signal may be formed by adjusting the control signal according to a ratio of a rectified input voltage of the switching converter and its output voltage.

According to further embodiments of the method, the drive signal may comprise a pulse width modulated signal.

According to further embodiments, the method may further comprise multiplying the actuating signal with a synchronization signal derived from a rectified input voltage of the switching converter to form the control signal.

According to further embodiments of the method, generating the synchronization signal may include: determining a voltage present in the switching converter; Comparing the voltage present in the switching converter with a predetermined voltage value; Generating a pulse signal when it is determined that the voltage applied to the switching converter falls below the predetermined voltage value; and generating the synchronization signal based on the generated pulse signals.

According to further embodiments of the method, the spurious oscillation in the output voltage signal may be a first harmonic.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

Show it:

1 a conventional switching power supply;

2 a signal conditioning circuit according to various embodiments;

3A to 3C Waveforms at various nodes within the signal conditioning circuit according to various embodiments;

4 a circuit for generating a synchronization signal according to various embodiments;

5A to 5D Waveforms at various nodes within the circuit for generating a synchronization signal according to various embodiments;

6 a switching converter according to various embodiments;

7A to 7C various voltage waveforms based on a simulation of the operation of a conventional switching converter;

8A to 8C various voltage waveforms based on a simulation of the operation of the switching converter according to various embodiments;

9A to 9C various voltage waveforms based on a simulation of the operation of the switching converter according to various embodiments, in which a load jump occurs;

10 a circuit for generating a synchronization signal according to various embodiments;

11 a signal conditioning circuit according to various embodiments;

12 a method for generating a synchronization signal according to various embodiments; and

13 a signal conditioning method according to various embodiments.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "front", "rear", etc. is used with reference to the orientation of the described figure (s). Because components of embodiments can be positioned in a number of different orientations, the directional terminology is illustrative and is in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be understood that the features of the various exemplary embodiments described herein may be combined with each other unless specifically stated otherwise. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

As used herein, the terms "connected," "connected," and "coupled" are used to describe both direct and indirect connection, direct or indirect connection, and direct or indirect coupling. In the figures, identical or similar elements are provided with identical reference numerals, as appropriate.

In 1 is a common circuit 100 for power factor correction, which is part of a switching power supply (also referred to as a switching converter), which is set up as a boost converter. The circuit 100 for power factor correction in this case has a separate control circuit 154 for power factor correction.

The circuit 100 for power factor correction has an input terminal 102 on which with a voltage source 101 which can provide a supply AC voltage V_supply. The input connection 102 For example, it may be configured as an electrical interface to the utility network that provides an AC voltage having a predetermined amplitude and frequency. An input terminal of the input terminal is via a first current detection device 104 For example, an ammeter, to an electrical path between a first the diode 108 and a second diode 110 connected. The other input terminal of the input terminal 102 is at an electrical path between a third diode 112 and a fourth diode 114 connected. The first diode 108 and the third diode 112 are connected to a terminal of an inductance 118 and to a terminal of a voltage detecting device 116 connected, for example, a voltmeter. The other connection of the voltmeter 116 is with the second diode 110 and the fourth diode 114 coupled. The other end of the inductance 118 is to a terminal of a fifth diode 126 coupled. Between the other end of the inductor 118 and the fifth diode 126 is serially a second current sensing device 122 , For example, an ammeter, interconnected. The other end of the fifth diode 126 is to a connection of a capacity 128 connected, the other end of the capacity 128 is with the merger of the corresponding terminals of the second diode 110 , the fourth diode 114 and the first voltmeter 116 connected. A first controllable connection of a switch 124 is at the electrical path between the second ammeter 122 and the fifth diode 126 coupled. The other controllable connection of the switch 124 is at the junction of the corresponding terminals of the second diode 110 , the fourth diode 114 and the first voltmeter 116 coupled. The desk 124 For example, it may be any transistor, such as a metal oxide semiconductor field effect transistor (MOSFET) or a bipolar junction transistor (BJT). A series arrangement comprising a first resistor 132 and a second resistor 134 is parallel to the capacity 128 coupled. Further, a second switch 136 provided, which optionally the second resistor 134 can bridge. The second switch 136 is with a control signal source 137 coupled. Parallel to the series arrangement comprising the first resistor 132 and the second resistor 134 is a second voltage detection device 138 coupled, for example, a voltmeter.

The structure of the circuit 100 for power factor correction was constructed for simulation purposes as in 1 shown so that it may differ in detail from an actual embodiment. In actual circuit design, voltage dividers and shunt resistors (or current transformers) would normally be used instead of the illustrated voltmeters and ammeters. The current detection by means of the second current detection device 122 For example, usually in the connection path between the diodes 110 . 114 on the one hand and the switch 124 and the capacitor 128 on the other hand.

The components described so far can be associated with the up-converter, the circuit 100 for power factor correction. The other components which will be described below may be the power factor correction control circuit 154 (hereinafter also referred to as LFK control circuit) are assigned.

An output of the first voltmeter 116 is to an input of a scaling circuit 148 coupled. An output of the scaling circuit 148 is at a first input of a multiplication circuit 146 coupled. An output of the second voltmeter 138 is to a subtrahend terminal of a first subtracting circuit 152 coupled. The minuend port of the first subtraction circuit 152 an output voltage reference signal V_dc_ref is supplied. An output of the first subtraction circuit 152 is to an input of a regulator 150 coupled. An output of the regulator 150 is to a second input of the multiplication circuit 146 coupled. An output of the multiplication circuit 146 is to a minuend terminal of a second subtractor circuit 144 coupled. A subtrahend terminal of the second subtracting circuit 144 is to a signal output of the second ammeter 122 coupled. An output of the second subtractor circuit 144 is to an input of a control circuit 142 coupled. An output of the control circuit 142 is to an input of a driver circuit 140 coupled. An output of the driver circuit 140 is to a control terminal of the first switch 124 coupled.

With the first ammeter 104 The input alternating current I_supply can be monitored and / or determined. The ammeter 104 is used for signal analysis and is to be regarded as an optional component. The input AC voltage V_supply of the voltage source 102 is done by means of the four diodes 108 . 110 . 112 . 114 rectified, which form a bridge rectifier. Is the switch 124 closed (ie, conducting), the rectified input alternating current I in flows through the inductance 118 , where a magnetic field of inductance 118 is built. Will the switch 124 opened (ie not made conductive), so tries the inductance 118 to maintain the current flow and induces a voltage which is the voltage across the capacitor 128 exceeds. This will turn the diode 126 operated in the forward direction, so that the current through the fifth diode 126 , which acts as a freewheeling diode, in the capacitor 128 can flow and continue to charge. The capacitor 128 is operated here as a charging or storage capacitor, since it adds up the output voltage V_dc. In this phase, ie during the period in which the switch 124 is open, the magnetic field of the inductance 118 degraded, causing an energy transfer in the form of a through the inductance 118 driven current flow through the diode 126 in the capacity 128 he follows. Thus, the voltage of the capacitor 128 be supplied to a load, which in this case by the first resistor 132 and optionally the second resistor 134 is modeled.

By means of the first voltmeter 116 For example, the rectified input AC voltage V_in, which is generated by means of the rectifier from the input AC voltage V_supply, and the associated measured value can be detected by the scaling circuit 148 to be provided. The scaling circuit 148 is set up to scale its input signal by a factor k. That is, the output of the scaling circuit 148 may have an amplitude which is by the factor k with respect to the amplitude of the input signal of the scaling circuit 148 is reduced. The scaling circuit may have, for example, a voltage divider. The output signal of the scaling circuit is a synchronization signal I_sync which corresponds to a scaled rectified input AC voltage V_in. The synchronization signal I_sync may be the first input of the multiplication circuit 146 be supplied. The synchronization signal I_sync can be used to switch 124 such that the of the exemplary switching power supply 100 received input alternating current I_supply has a pure, ie monofrequency, sinusoidal waveform and is in phase with the input AC voltage V_supply.

By means of the second voltmeter 138 can the output voltage V_dc of the circuit 100 be determined for power factor correction, ie the on the serial arrangement of the capacitor 128 and the second resistor 130 applied voltage, which can be applied to the load. The determined output voltage V_dc of the circuit 100 for power factor correction, the subtrahend input of the first subtraction circuit 152 be supplied. The setpoint of the output voltage V_dc_ ref the circuit 100 for power factor correction, which can be output, for example, from a reference signal source, the Minuend input of the first subtraction circuit 152 be supplied. Consequently, the first subtracting circuit is 152 set to output an output signal, for example, a control signal (C), which is the difference between the setpoint of the output voltage V_dc_ref of the circuit 100 for power factor correction and the actual value of the output voltage V_dc of the circuit 100 corresponds to power factor correction. Seen in this way, the output signal of the first subtracting circuit 152 are considered as the instantaneous error signal representing the deviation of the (instantaneous) output voltage V_dc of the circuit 100 for power factor correction from its setpoint V_dc_ref. This control signal (C) can be a controller 150 which can output a controlled control signal I_amplitude (which can also be understood as a regulated error signal). The regulator 150 For example, it may be configured as a P controller, a PI controller, a PID controller, or may be any other controller, such as a repetitive controller. The regulated control signal I_amplitude can be the second input of the multiplication circuit 146 be supplied. The controlled control signal I_amplitude can be used to the duty cycle of the driver circuit 140 the switch 124 adjusted drive signal, so that the value of the output voltage V_dc of the circuit 100 for power factor correction can be increased or decreased depending on whether the instantaneous value of the output voltage V_dc is below or above the setpoint value of the output voltage V_dc_ref.

The multiplication circuit 146 is set up to multiply the synchronization signal I_sync with the regulated control signal I_amplitude and to provide a reference signal I_ref. The reference signal I_ref combines the above-described information content of the synchronization signal I_sync and the regulated control signal I_amplitude. By means of the second subtraction circuit 144 the reference signal I_ref is adjusted by means of the value of the coil current I_in, ie by means of the value of the bridge diode having the four diodes 108 . 110 . 112 . 114 rectified input alternating current I_in, which by the inductance 118 flows. This adaptation can be done by subtracting the value of the coil current I_in from the reference signal I_ref. The output signal of the second subtraction circuit 144 can the control circuit 142 be supplied. The control circuit 142 which may comprise, for example, a regulator, such as a PI regulator, may be arranged on the basis of the output signal of the second subtraction circuit fed to it 144 to output a control signal. The control signal may be to the driver circuit 140 are fed, which from a drive signal for the switch 124 generated. The drive signal is for controlling the state of the switch 124 such that the of the circuit 100 power factor correction input AC current I_supply has a sinusoidal as possible waveform and is in phase with the input AC voltage V_supply and that the output voltage V_dc equal to the setpoint of the output voltage V_dc_ref. The driver circuit 140 or the control circuit 142 may comprise a pulse width modulator, which may be used to generate the control signal / drive signal.

In 2 is a circuit for signal conditioning 200 illustrated according to various embodiments. The circuit 200 According to various embodiments may additionally in the LFK control circuit 154 in 1 be arranged in the signal path between the output of the second voltmeter 138 and the subtrahend input of the first subtracting circuit 152 What to do later with reference to 6 will be described in more detail.

The signal conditioning circuit 200 According to various embodiments, the output voltage V_dc of the circuit 100 be supplied to the power factor correction. First, the output voltage from a sampling circuit 202 are sampled, so that at certain intervals discrete values of the output voltage V_dc can be detected and until the beginning of the next sampling by the sampling circuit 202 can be kept as its output signal value. The sampling circuit 202 can be configured as an analog-to-digital converter. The output of the sampling circuit 202 can be connected to an input of a scaling circuit 204 be coupled. The scaling circuit 204 may be arranged to halve its input signal, ie to multiply by a factor of 0.5, so that the amplitude of its output signal is smaller by half than the amplitude of its input signal. The output of the scaling circuit 204 is on the one hand to an input of a delay circuit 208 and to a first input of an adder circuit 206 coupled. An output of the delay circuit 208 is to a second input of the adder circuit 206 coupled. The delay circuit 208 can be implemented analog or digital. Accordingly, the sampling switch circuit 202 be implemented digitally or analogously. The output of the adder circuit 206 is at the subtrahend input of the first subtractor circuit 152 coupled (see also 1 ). Seen in this way, the output signal of the adder circuit 206 a processed output voltage signal Z, which of the output voltage V_dc of in 1 shown usual circuit 100 derived for power factor correction and which the first subtraction circuit 152 can be supplied. The further signal path, ie the subtraction of the adder circuit 206 issued composite Input signal Z from the setpoint of the output voltage V_dc_ref of the circuit 100 for power factor correction and supplying this result to the regulator 150 to obtain the controlled control signal I_amplitude corresponds to that in 1 illustrated and already described signal path. Exemplary signal curves of the output signal of the scaling circuit 204 , the output signal of the delay circuit 208 and the output Z of the adder circuit 206 are in 3 and will be explained in more detail later to the operation of the signal conditioning circuit 200 to explain in more detail according to various embodiments.

The output voltage V_dc of the circuit 100 for power factor correction may be contaminated with harmonics, for example, with a frequency which is twice the frequency of the fundamental and usually carries the largest power, so that higher-order vibrations compared to the first harmonic can be neglected in first approximation. Generally, as mentioned in the beginning, harmonics are problematic and should be eliminated. The first harmonic has an oscillation frequency of 100 Hz at a frequency of the input AC voltage V_supply of 50 Hz, at a frequency of the input AC voltage V_supply of 60 Hz, it has an oscillation frequency of 120 Hz. The examples here are limited in practice only to input AC voltages V_supply with frequencies of 50 Hz or 60 Hz, since these frequencies correspond to the common mains frequencies encountered on the earth. For the functionality of the signal conditioning circuit 200 however, according to various embodiments, this is not a limitation since its operation can be adjusted to any frequency of the input AC voltage.

An output voltage V_dc, which is contaminated with interfering harmonics and thus is not a pure DC voltage but contains alternating voltage components, can have a negative effect on the outer voltage control loop, since the disturbances on the of the first subtracting circuit 152 can output transmitted control signal and so the control can become unstable. Furthermore, if the spurious harmonics are not filtered out of the output voltage V_dc, this can result in the rectified input AC voltage V_in being multiplied by a signal that varies within a sine half-wave and, as a result, receives a signal that is not pure Sine amount function corresponds. Thus, the input current I_supply of the associated switching converter is no longer regulated to a sine-amount function and the input current before the bridge rectifier is thus no longer sinusoidal. Consequently, it may be of interest to obtain the first harmonic from the output voltage signal V_dc of the circuit 100 to remove power factor correction. It should be noted that the signal conditioning circuit 200 according to various embodiments may be arranged such that any harmonic from the output voltage V_dc is removed. Usually, however, the first harmonic (ie, the second harmonic) provides the largest contribution, hence it is believed that the first harmonic should be removed from the AC voltage component contaminated output voltage V_dc. In principle, with the signal conditioning circuit 200 several harmonics are removed at the same time. In contrast, with a notch filter only the harmonic to which the notch filter is tuned can be filtered out.

The delay circuit 208 is arranged to delay the sampled and scaled output voltage V_dc supplied thereto for a predetermined period of time. The predetermined period of time may correspond to half a period of oscillation from which the output voltage signal V_dc is to be adjusted. Depending on whether the input AC voltage is 50 Hz or 60 Hz, the delay circuit may be configured to delay the sampled and scaled output voltage signal V_dc by half a period of the corresponding first harmonic, which is then 100 Hz or 120 Hz. Consequently, the delay circuit can 208 be set to delay its input signal by 5 milliseconds (equivalent to half the period of the first harmonic at a frequency of 100 Hz) or by about 4.2 milliseconds (equivalent to half the period of the first harmonic with a frequency of 120 Hz). The delayed output voltage signal V_dc is provided by the adder circuit 206 added to the non-delayed output voltage signal V_dc. The composite input signal Z, ie the output signal of the adder circuit 206 , is free of the first harmonic, as its components in the delayed and in the instantaneous output voltage signal V_dc in the addition in the adder circuit 206 cancel / cancel each other. In the case of a 50 Hz input AC voltage V_supply, the composite input signal Z would also be freed from the fifth harmonic (300 Hz), the ninth harmonic (500 Hz) and so on. This aspect will be described below with reference to FIGS 3A to 3C explained in more detail. The output voltage V_dc adjusted from the first harmonic, which with respect to the first harmonic now provides a trouble-free (or "clean") DC voltage can then by means of the first subtraction circuit 152 from the set value of the output voltage V_dc_ref of the circuit 100 to be subtracted from the power factor correction, so that the first subtractor circuit 152 the controller 150 a fault-free actuating signal can be provided with regard to the first harmonic.

It should be noted that at the in 2 illustrated embodiment of the circuit for signal processing 200 According to various embodiments, the scaling circuit 204 alternatively also between the output of the adder circuit 206 and the subtrahend input of the first subtracting circuit 152 can be connected, so that the scaling of the control signal to the correct, the setpoint of the output voltage V_dc_ref corresponding average can be done only after the elimination of the interfering harmonic.

It is worth mentioning at this point that the signal processing circuit 200 may be configured such that the signal propagation time of the instantaneous scaled output voltage signal V_dc between the output of the scaling circuit 204 and the first input of the adder circuit 206 and the sum of the signal delays from the signal propagation time of the first undelayed scaled output voltage signal V_dc between the output of the scaling circuit 204 and the input of the delay circuit 208 and the signal delay of the then delayed scaled output voltage signal V_dc between the output of the delay element 208 and the second input of the adder circuit 206 and the first input of the adder circuit 206 can be the same. Alternatively, the signal propagation times may be offset so that the actual delay time of the delay circuit 208 can be adjusted. In other words, it is important that the signals at the time of addition by the first adder circuit 206 have the correct phase shift of half a period of the noise component to be removed.

In 3A is a diagram 302 shown in which the output signal 312 of in 2 shown scaling circuit 204 is shown. This signal corresponds to the instantaneous scaled output voltage signal of the switching converter. In 3B is a diagram 304 shown in which the output signal 314 of in 2 shown delay circuit 208 is shown. This signal corresponds to the delayed scaled output voltage signal V_dc. In 3C is a diagram 306 shown in which the output signal 316 of in 2 shown adding circuit 206 is shown. The diagrams in the 3A to 3C each have an x-axis 308 on, on which the time is applied. The explicit scaling is only on the x-axis 308 in the diagram 306 the 3C and is the same for the other two diagrams. Furthermore, the diagrams in the 3A to 3C one y-axis each 310 on which a voltage in volts is plotted.

In the illustrated exemplary scenario, the setpoint of the output voltage is V_dc_ref of the circuit 100 for power factor correction 400 V. Consequently, in each case the mean value of the voltage of the output signal 312 from the scaling circuit 204 and the output signal 314 of the delay circuit 208 200 V, wherein in both signals a disturbance around this mean value in the form of a harmonic with an amplitude of about 6 V can be seen. The output signal of the scaling circuit 312 but is out of phase with the output of the delay element 208 , More specifically, the delay element 208 set up the propagation of the signal supplied to it by a time delay of half the period of the disturbing oscillation, so as to bring about the desired phase shift. This is the second input of the adder circuit 206 supplied signal shifted by half a period of the disturbing oscillation with respect to the signal which is the first input of the adder circuit 206 is supplied. As mentioned above, in this exemplary scenario, the disturbance to be eliminated is the first harmonic of the utility grid voltage. The output signal 316 which is from the adder circuit 206 is equal to the sum of the graph 302 in 3A shown signal 312 and in the diagram 304 in 3B shown signal 314 , Due to the temporal shift by half a period of the disturbing oscillation, the components of the disturbing oscillation cancel each other out in the addition of the two signals. As in the diagram 306 in 3C can be seen, is the output signal 316 of the adder circuit 206 free of the disturbing harmonic. By scaling the output voltage signal V_dc by a factor of 0.5 prior to dividing the output voltage signal V_dc, the sum of the delayed output voltage signal 312 and the instantaneous scaled output voltage signal 314 representing signal 316 in this exemplary scenario 400V, which is the setpoint V_dc_ref of the output voltage V_dc of the circuit 100 corresponds to power factor correction.

It should also be noted that the presented concept also applies to any frequency other than the frequency of the first harmonic considered here by way of example at a mains frequency of the input AC voltage of 50 Hz or of 60 Hz Hz is applicable. The functioning of the in 2 illustrated circuit 200 According to various embodiments, based on the addition of two equally reported AC / AC signals superimposed on an interfering frequency, the one rectified AC voltage is phase shifted by a predetermined period of time of the other rectified AC voltage. The predetermined period of time may correspond to half the period of the disturbing oscillation. When adding the two rectified AC voltages, the wave peaks of the interfering frequency component then coincide with their wave troughs, so that the interfering frequency component is eliminated in the sum signal of the two rectified AC voltage signals. By a configuration parameter, which can be supplied to the delay element, its delay time and thus the induced phase shift can be adjusted and thus adjusted to any vibration which is to be eliminated. Furthermore, the configuration parameter can be used to fine tune the delay time to account for potential signal propagation delays since the reference point for the desired phase shift resulting in cancellation of the spurious frequency component is the first adder circuit 206 is.

With the signal conditioning circuit 200 According to various embodiments, a "clean" (freed from a noise component), the output voltage V_dc of the circuit 100 power factor correction signal may be provided to the first subtracting circuit 152 for comparison with the setpoint V_dc_ref of the output voltage. The resulting from this comparison control signal C, which can be regarded as a current error signal, the controller 150 be supplied so as to provide a regulated control signal (regulated error signal) I_amplitude, which is used as a reference for adjusting the amplitude of the circuit 100 can be used for power factor correction recorded input alternating current I_supply. As in the signal conditioning circuit 200 According to various embodiments, no low pass filter is used, the dynamic / transient response may be very fast. In addition, the implementation of the delay circuit 208 based on a ripple cancellation method simpler than the implementation of a notch filter.

As mentioned above, to generate a reference signal for the recorded input current in a switching power supply / switching converter further a synchronization signal may be required. In conventional switching power supplies, such as the in 1 illustrated circuit 100 For power factor correction, the synchronization signal is proportional to the input AC voltage, ie the input AC voltage V_supply is scaled by a factor k only to obtain the synchronization signal I_sync. This approach works well as long as the input AC voltage V_supply has no interference, ie a pure sine wave with, for example, one of the predetermined line frequencies of typically 50 Hz or 60 Hz. However, if the input AC voltage V_supply is contaminated with higher harmonics or other types of distortion and thus presents a non-ideal AC input voltage V_supply, this control method will produce a dirty synchronization signal, which may result in poor regulation of the input current.

In 4 is a circuit 400 for generating a trouble-free synchronization signal according to various embodiments. In this context, a trouble-free synchronization signal is to be understood as a signal which is derived from the input signal of the circuit 400 is derived according to various embodiments and a monofrequency rectified sine wave signal having a frequency which is the fundamental frequency of the input signal of the circuit 400 according to various embodiments. At the frequency of the circuit 400 output synchronizing signal I_sync may be useful to double the mains frequency of the input AC voltage V_supply. The doubling is in this case the consequence of the previous rectification of the mains voltage V_supply, which is supplied to the switching converter as a sine signal.

In the course of this description, the rectification of a sine signal is understood as leaving the signal components greater than zero and inverting the signal components smaller than zero, whereby after rectification of a sine signal, a signal is formed which has twice the frequency and illustratively has only peaks, each second wave crest one "Folded" wave trough corresponds.

In conjunction with a switching converter / switching power supply, the circuit 400 for generating a no-interference synchronization signal according to various embodiments, be able to generate a no-interference synchronization signal regardless of the quality of the input AC voltage V_supply, ie independent of the degree of interference of the input AC voltage V_supply. Generally speaking, the uses circuit 400 for generating a synchronization signal according to various embodiments, the principle of a zero-crossing detection.

As input, the circuit can 400 for generating a synchronization signal according to various embodiments, the rectified by means of the bridge rectifier input AC voltage V_in are supplied. The circuit 400 According to various embodiments, a sample and hold circuit 402 have, to which these rectified input AC voltage V_in can be supplied. The output of the sample and hold circuit 402 may be a first input of a detection circuit 406 be supplied. A comparative value 404 can be supplied to a second input of the detection circuit. The circuit 400 According to various embodiments may further comprise an integrator 410 exhibit. An output of the detection circuit 406 can be connected to a first input of the integrator 410 be coupled. A second input of the integrator may be connected to a register or memory 408 be coupled. The circuit 400 According to various embodiments may further include a signal generating circuit 412 exhibit. An output of the integrator 410 may be applied to an input of the signal generation circuit 412 be coupled. At the output of the signal generation circuit 412 the synchronization signal I_sync can be provided. Exemplary signal curves of the rectified input AC voltage 416 , the output signal 418 of the detection circuit 406 , the output signal 420 of the integrator 410 and the output signal 422 the signal generating circuit 412 be in the 5A to 5D explained in more detail below.

The rectified input AC voltage V_in can by means of the sample and hold circuit 402 the detection circuit 406 be provided, which this with a predetermined constant voltage value 404 which may be, for example, 3 V or, for example, 1 V or, for example, 0.75 V or, for example, 0.5 V or even less. The constant voltage value 404 can assume any value and can be adapted to the desired detection accuracy of the zero crossing and / or to the amplitude of the rectified input AC voltage V_in. The detection circuit 406 is configured to generate a pulse signal when it detects that the rectified input AC voltage V_in is less than the predetermined voltage value 404 , A falling of the rectified input AC voltage V_in below the predetermined voltage value 404 , which represents a positive threshold to be dropped and is suitably close to zero, can be interpreted as a zero crossing of the input AC voltage V_supply. The time interval T between two successive pulse signals is therefore half the period of the input AC voltage V_supply. The integrator 410 may be arranged to integrate the time between two pulse signals so as to generate a ramp signal. With every pulse signal generated, the integration process in the integrator becomes 410 reset. The output signal of the integrator is sawtooth-shaped, which can increase from zero to pi. The time interval T determines the value of a constant C = Pi / T stored in the register or memory 408 is stored and the second input of the integrator 410 is supplied. Based on the instantaneous value of the ramp signal and the constant C, the instantaneous angle of the rectified input AC voltage V_in can be determined. From this, by means of the signal generator 412 a synchronization signal I_sync are generated, which corresponds to a trouble-free, rectified input AC voltage V_in. To generate the interference-free synchronization signal I_sync for controlling the recorded input alternating current I_supply can from the integrator 410 generated ramp signal by means of a trigonometric function, such as the sine function, are evaluated or it can be used a corresponding look-up table, which contains for each argument of the sine, so each angle, the corresponding value of the function. The corresponding circuit unit, which calculates an instantaneous angle of the sinusoidal signal to be generated from the ramp signal, either in the integrator 410 or in the signal generation circuit 412 be provided. As a result, the signal generating circuit generates 412 on the basis of the angle values, a rectified sine signal as a synchronization signal I_sync whose frequency corresponds to twice the frequency of the input AC voltage. For example, the most dominant component may be the pure AC voltage with the line frequency of 50 Hz or 60 Hz.

At this point it should be mentioned that the circuit 400 for generating a synchronization signal according to various embodiments, although its functionality has been described embedded in a LFK circuit for a switching converter, can generally be used to generate a signal which is the rectified from any sinusoidal signal which may be superimposed with disturbing frequencies corresponds to any sinusoidal signal, but adjusted to the interference frequencies, so represents a "clean", rectified sine wave signal.

In the 5A to 5D are the corresponding ones in the circuit 400 illustrated signals for generating a synchronization signal according to various embodiments, which the signal detection device 414 be supplied. In 5A is a diagram 502 in which the input AC voltage V_in is shown. In 5B is a diagram 504 shown in which the output signal 516 of the detection circuit 406 is shown. In 5C is a diagram 506 shown in which of the integrator 410 generated ramp signal 520 is shown. In 5D is a diagram 508 in which the interference-free synchronization signal I_sync is shown. The diagrams in the 5A to 5D each have an x-axis 510 on, on which the time is applied. The explicit scaling is only on the x-axis 510 in the diagram 508 in the 5D and is for the other three diagrams 502 . 504 . 506 equal. Furthermore, the diagrams in the 5A to 5D one y-axis each 512 on which in each case the amplitude of the signal shown in the associated diagram is plotted.

In the following to explain the operation of the circuit 400 For generating a synchronization signal according to various embodiments used scenario, the rectified input AC voltage V_in (and thus also the input AC voltage V_supply, from which the rectified input AC voltage V_in is derived by rectification) deviates significantly from a rectified, monofrequenten sinusoidal signal, as in diagram 502 in 5A you can see. Whenever the rectified input AC voltage V_in reaches approximately zero or below the predetermined voltage value 404 falls, which is positive and can be close to zero, speaks the detection circuit 406 and it will be a pulse signal 514 in the output signal 516 of the detection circuit 406 generated. Between the pulse signals 514 can the output signal 516 of the detection circuit 406 have a low level, for example the value zero. As in the diagram 506 in 5C is shown at every pulse signal 514 the ramp signal 520 reset. The initial value of the ramp signal 520 can be set to zero, the end point of the ramp signal 520 the value Pi can be assigned. Thus, an instantaneous value of the ramp signal (calibrated with the constant C) corresponds to the angular value of the instantaneous rectified input AC voltage V_in in radians, which is a sinusoidal signal (contaminated with spurious frequencies). It can be seen that, in this case, the noises or disturbance oscillations superimposed on the rectified input AC voltage V_in have substantially no influence on the determination of the angle of the rectified input AC voltage V_in, since only the zero crossings of the rectified input AC voltage V_in are used to determine the frequency of the interference-free synchronization signal I_sync, which in the diagram 508 in 5D is shown. In other words, the synchronization signal I_sync may be dependent on the course of the ramp signal 520 dependent by the synchronization signal I_sync the sine value (or cosine value) of the current ramp signal 520 divided by the constant C corresponds. The frequency of the (clean) synchronization signal I_sync can be determined solely by the zero crossings of the input AC voltage V_supply, which can be essentially independent of interference frequencies on the input AC voltage signal V_supply. Because the ramp signal 520 has a smooth course and its start point and its end point of zero crossings of the input AC voltage V_dc are determined, it can be ensured that the synchronization signal I_sync thus generated is synchronous with the input AC voltage V_supply, but is adjusted to their interference frequencies, as can be determined by comparison the rectified input AC voltage V_in in the diagram 502 in 5A with the interference-free synchronization signal I_sync in the diagram 508 in 5D clearly sees.

In 6 is a circuit 600 for power factor correction according to various embodiments. The circuit 600 for power factor correction has a boost converter (analogous to that in FIG 1 illustrated conventional circuit 100 for power factor correction) and a separate power factor correction circuit 610 (hereinafter referred to as LFK circuit) according to various embodiments. Due to the similarity of both switching power supplies the same elements are provided with the same reference numerals. Additional or modified elements bear in the in 6 illustrated circuit 600 for power factor correction according to various embodiments reference numerals, which begin with the numeral 6. On the functions of component / assemblies in the circuit 600 for power factor correction according to various embodiments, already in connection with the in 1 illustrated circuit 100 for power factor correction, will not be discussed again. So z. B. the boost converter is not described again, since this is the up-converter of in 1 similar to the usual switching power supply.

The LFK circuit 610 According to various embodiments, based on the LFK control circuit 154 out 1 , In the signal path between the second voltmeter 138 and the first Subtracting circuit 152 can the signal conditioning circuit 606 be connected according to various embodiments, so that the output voltage V_dc free of harmonics can be supplied to the outer voltage control loop. The implementation of the signal conditioning circuit 606 According to various embodiments, for example, in 2 correspond to the implementation shown, wherein the first subtraction circuit 152 and the regulator 150 "Double" are shown (ie both in 2 as well as in 6 ).

Furthermore, in the signal path between the first voltmeter 116 and the multiplication circuit 146 the scaling circuit 148 (please refer 1 ) by the circuit for generating a synchronization signal 604 be replaced according to various embodiments. The implementation of the circuit for generating a synchronization signal 604 According to various embodiments, for example, in 4 correspond to the implementation shown.

Depending on requirements, only the circuit for signal processing 606 According to various embodiments or the circuit for generating a smooth synchronization signal 604 according to various embodiments in the LFK circuit 610 be provided according to various embodiments. The provision of both of these circuits is not mandatory, but may prove advantageous in terms of precise, fast and efficient regulation of the output voltage V_dc and minimization of the disturbances imposed on the input AC input I_supply.

The LFK circuit 610 According to various embodiments, a matching circuit may further be provided 602 which is arranged to adjust the control signal based on a ratio of the rectified input AC voltage V_in and the output voltage V_dc of the circuit 600 for power factor correction according to various embodiments. This can be done with the matching circuit 602 to a second adder circuit 608 be coupled, so that one of the matching circuit 602 output signal D to that of the control circuit 142 output control signal S is added before this the driver circuit 140 is supplied. That of the control circuit 142 outputted control signal S can be used to the duty cycle of the switch 142 in accordance with changes made to the circuit 600 to continuously adjust the load connected to power factor correction according to various embodiments. The matching circuit 602 together with the second adder circuit 608 can provide a pilot control, in this case a control loop, which is independent of the circuit 600 to power factor correction connected load in the entire control circuit of the circuit 600 for power factor correction according to various embodiments engages. That of the matching circuit 602 generated signal D may have a value which is determined according to the formula D = 1 - V_in / V_dc, ie only from the rectified input AC voltage V_in and from the output voltage V_dc of the circuit 600 for power factor correction according to various embodiments. From the sum of the signal D and the control signal S, the driver circuit 142 form a drive signal which is the control terminal of the switch 142 can be supplied and so directly the duty cycle of the switch 142 can determine, ie the relationship between the time in which the switch 142 is conductive, and the time in which the switch 142 is non-conductive.

By providing the customization network 602 can by means of the LFK circuit 610 According to various embodiments, the equilibrium equation of an up-converter in non-leaking operation is taken into account in its operation. With the LFK circuit 610 In accordance with various embodiments, a switching converter, such as a boost converter, may generally be operated so that the overall system can respond quickly to load transients.

To the effectiveness and usefulness of the LFK circuit 610 According to various embodiments to investigate in conjunction with an up-converter, in particular in comparison to a conventional LFK circuit, as he, for example, in 1 are shown in the 7A to 7C and in the 8A to 8C Simulation results presented based on a common circuit 100 for power factor correction or the circuit 600 for power factor correction according to various embodiments. The 7A to 7C show simulation results, which are based on a conventional switching power supply, the switch is thus controlled by a conventional LFK circuit. The implementation of the ordinary switched-mode power supply used for the simulation corresponds to that of the circuit 100 for power factor correction 1 , The 8A to 8C show simulation results, which on the switching power supply 600 according to various embodiments, whose switch from a LFK circuit 610 is driven according to various embodiments. The one used for this simulation Implementation of the switched-mode power supply according to various embodiments can be found in FIG 6 correspond to the implementation shown.

In the diagram 702 in 7A a curve of the input AC voltage V_supply is shown. In the diagram 704 in 7B a plot of the input alternating current I_supply is shown. In the diagram 706 in 7C a curve of the output voltage V_dc is shown. The diagrams in the 7A to 7C each have an x-axis 708 on, on which the time is applied. The explicit scaling is only on the x-axis 708 in the diagram 706 of the 7C and is the same for the other two diagrams. Furthermore, the diagrams in the 7A to 7C one y-axis each 710 on which a voltage in volts (diagram 702 in 7A and diagram 706 in 7C ) or a current in amperes (Diagram 704 in 7B ) is applied. As already mentioned, the simulation results refer to the 7A to 7C on an ordinary circuit 100 for power factor correction, as in 1 is shown.

For comparison, corresponding waveforms in the diagrams in the 8A to 8C shown, which represent simulation results with a circuit 600 power factor correction according to various embodiments, as shown in FIG 6 has been obtained. That is, in the diagram 802 in 8A a curve of the input AC voltage V_supply is shown. In the diagram 804 in 8B a plot of the input alternating current I_supply is shown. In the diagram 806 in 8C a curve of the output voltage V_dc is shown. The diagrams in the 8A to 8C each have an x-axis 808 on, on which the time is applied. The explicit scaling is only on the x-axis 808 in the diagram 806 of the 8C and is the same for the other two diagrams. Furthermore, the diagrams in the 8A to 8C one y-axis each 810 on which a voltage in volts (diagram 802 in 8A and diagram 806 in 8C ) or a current in amperes (Diagram 804 in 8B ) is applied. The scaling of the x-axis and the y-axis in the respective corresponding diagrams in the 7A to 7C and 8A to 8C are equal.

The input AC voltage V_supply in the diagram 702 in 7A and the diagram 802 in 8A has a frequency of 50 Hz. For investigation purposes, it is contaminated / superimposed with the fifth harmonic and the seventh harmonic to simulate a non-ideal input AC voltage V_supply. The first harmonic, ie the fundamental, superimposed higher harmonics cause a significant deformation of the first harmonic.

In the simulation results of the ordinary switching power supply, it can be observed that the input AC current I_supply has a similar shape to the input AC voltage V_supply. In other words, the noise contained in the input AC voltage V_supply is caused by the ordinary LFK control circuit 154 in 1 transmitted to the input alternating current I_supply. That's because as in 1 can be seen, the synchronization signal I_sync downscaling only one and rectified input AC voltage V_supply corresponds. By rectification, the higher harmonics are not filtered out, and thus the switch becomes 124 such that the input alternating current I_supply is brought into phase with the course of the input alternating voltage V_supply. Although the ordinary LFK control circuit 154 being able to maintain the power factor at approximately 1, the disturbances in the input alternating current I_supply are unavoidable and the total harmonic distortion (THD) of the input alternating current I_supply is relatively large.

In comparison, it can be seen that the input alternating current I_supply in the circuit 600 for power factor correction, according to various embodiments, having a smooth sinusoidal waveform without the fifth harmonic and seventh harmonic interference superimposed on the input AC voltage V_supply. Also in this case, the power factor is about 1. The LFK circuit 610 According to various embodiments, it is capable of bringing the input AC current I_supply in phase with the input AC voltage V_supply and, overall, simulating the current draw I_supply on the waveform of the input voltage V_supply, the input AC current I_supply having a smooth, sinusoidal shape despite significant noise frequencies on the input AC voltage V_supply.

The diagrams 902 . 904 . 906 in the 9A to 9C represent waveforms in a simulation scenario in which a load jump on the circuit 600 for power factor correction according to various embodiments. The diagrams 902 . 904 . 906 each represent the same signals in the same order as the diagrams in the 8A to 8C , That is, in the first diagram 902 in 9A a curve of the input AC voltage V_supply is shown. In the second diagram 904 in 9B a plot of the input alternating current I_supply is shown. In the third diagram 906 in 9C a curve of the output voltage V_dc is shown. The diagrams in the 9A to 9C each have an x-axis 908 on, on which the time is applied. The explicit scaling is only on the x-axis 908 in the diagram 906 of the 9C and is the same for the other two diagrams. Furthermore, the diagrams in the 9A to 9C one y-axis each 910 on which a voltage (diagram 902 in 9A and diagram 906 in 9C ) or a current in amperes (Diagram 904 in 9B ) is applied.

The in diagram 902 in 9A shown input AC voltage V_supply has a frequency of 50 Hz and is also contaminated / superimposed with the fifth harmonic and the seventh harmonic to simulate a non-ideal input AC voltage V_supply. As with the previous diagrams 802 to 806 in the 8A to 8C already explained, is the LFK circuit 610 According to various embodiments, capable of bringing the input alternating current I_supply in phase with the input alternating voltage V_supply and, in general, simulating the variation of the input alternating current to the profile of the input alternating voltage V_supply, without, however, compensating for the input alternating current I_supply in the Impose on the AC input voltage V_supply.

At the dashed vertical line 918 , which at 0.5 s on the x-axis 908 If there is a load jump. At the arbitrarily selected time of 0.5 sec, the load connected to the switching power supply according to various embodiments is increased abruptly. This can be simulated by the time in the circuit of 0.5 s 600 power factor correction switch according to various embodiments 136 is closed, so that the load instead of through the series connection of the first and second resistor 132 and 134 now from the first resistance 132 is modeled alone. After the load step, the switched mode power supply according to various embodiments has an increased power requirement, which is reflected in the larger amplitude of the input alternating current I_supply from the time of the load jump. Furthermore, it can be observed that the output voltage V_dc at the time of the jump in load drops from its average value of approximately 400 V, which at the same time corresponds to the setpoint value V_dc_ref of the output voltage V_dc, by approximately 4%. Thus falls below the setpoint output voltage is very low. In addition, the output voltage V_dc returns to its original equilibrium state after only about two cycles of the input AC voltage V_supply, that is, to a mean output voltage V_dc of about 400 V. The absence of a low-pass filter in the LFK circuit 610 According to various embodiments allows a very fast dynamic / transient response, so that dips in the output voltage V_dc, for example, at load jumps, can be compensated very quickly.

For comparison, it should be noted that when using a low-pass filter with a cutoff frequency of about 10 Hz to eliminate the first harmonic at 100 Hz in the output voltage V_dc this with a corresponding conventional switching power supply only at the time of about 0.6 s to their original regulated Voltage setpoint would return. Thus, the process of Ausregelns the load jump-induced change of the output voltage V_dc to the setpoint V_dc_ref by a corresponding conventional LFK circuit with a low-pass filter about nine clock cycles of the input AC voltage V_supply take and thus take in about more than four times as long as Ausregelvorgang in the switching power supply according to various embodiments.

It should be noted that although the LFK circuit presented herein has been described in connection with a boost converter according to various embodiments, it may also be used with other converter topology, for example, bridgeless converters, quasi bridgeless converters. and interleaved converters, as long as they are operated in a non-clutter mode of operation. The performance of the LFK circuit according to various embodiments should be about equally good for all of these converter topologies with respect to overall system control. In addition, the LFK circuit according to various embodiments can be implemented very simply in digital form.

In 10 is the circuit 1000 for generating a synchronization signal according to various embodiments, wherein the circuit may comprise: an input 1002 to which an input voltage can be supplied; a detection circuit 1004 which may be configured to compare the applied input voltage with a predetermined voltage value and to generate a pulse signal when the input voltage falls below the predetermined voltage value; a signal generation circuit 1006 which is connected to the detection circuit 1004 is coupled and may be configured based on the detection circuit 1004 generated pulse signals to generate a synchronization signal; and a control circuit 1008 , which may be configured based on the synchronization signal to provide a control signal for the switch of the switching converter. Furthermore, the circuit 1000 an exit 1010 at which the control signal for the switch can be provided.

In 11 is the circuit 1100 for signal conditioning according to various embodiments, wherein the circuit may comprise: an input 1102 to which an output voltage of the switching converter can be fed as input signal; a delay circuit 1104 configured to delay the signal applied to it which is dependent on the input signal to delay a time equal to one-half of a period of a harmonic in the input signal to produce a delayed input signal; a first sub-circuit 1106 which is arranged to add the delayed input signal and the input signal, so that a combined input signal is output; a second sub-circuit 1108 which is connected to the first sub-circuit 1106 is coupled and is arranged to subtract the combined input signal from a setpoint signal of the output voltage of the switching converter, so that a control signal is output; and a control circuit 1110 which is arranged to provide a control signal for the switch based on the actuating signal. Furthermore, the circuit 1100 an exit 1112 at which the control signal for the switch can be provided.

In 12 is a sequence of a procedure 1200 for generating a synchronization signal. With the in 12 illustrated method 1200 For example, a drive signal may be provided to a switch in a switching converter. In detail, the procedure 1200 have: determining a voltage applied in the switching converter voltage 1202 ; Compare the voltage applied in the switching converter voltage with a predetermined voltage value 1204 ; Generating a pulse signal 1206 when it is determined that the voltage applied to the switching converter falls below the predetermined voltage value; Generating a synchronization signal 1208 based on the generated pulse signals; and generating a control signal 1210 for the switch based on the synchronization signal.

In 13 is a sequence of a procedure 1300 shown for signal processing according to various embodiments. With the in 13 illustrated method 1300 For example, a drive signal may be provided to a switch in a switching converter. In detail, the procedure 1300 comprising: determining an output voltage signal based on an output voltage of the switching converter 1302 ; Delaying the output voltage signal by a period corresponding to one-half of a period of a harmonic of the output voltage signal 1304 ; Adding the delayed output voltage signal to the output voltage signal to provide a composite output voltage signal 1306 ; Subtracting the combined output voltage signal from a setpoint signal of the output voltage voltage of the switching converter to provide an actuating signal 1308 ; and generating a control signal for the switch based on the actuating signal 1310 ,

Claims (24)

Circuit ( 400 . 1000 ) for driving a switch ( 124 ) in a switching converter, wherein the circuit ( 400 . 1000 ): a detection circuit ( 406 . 1004 ), which is set up, an applied input voltage (V_in) having a predetermined voltage value ( 404 ) and a pulse signal ( 514 ) when the input voltage (V_in) falls below the predetermined voltage value ( 404 ) falls; A signal generation circuit ( 412 . 1006 ) which is connected to the detection circuit ( 406 . 1004 ) and is arranged on the basis of that of the detection circuit ( 406 . 1004 ) generated pulse signals ( 514 ) to generate a synchronization signal (I_sync); and a control circuit ( 142 . 1008 ), which is arranged on the basis of the synchronization signal, a control signal (S) for the switch ( 124 ). Circuit ( 400 . 1000 ) according to claim 1, further comprising: a sampling circuit ( 402 ), which between an input of the circuit ( 400 . 1000 ) and the detection circuit ( 406 . 1004 ) and is set up to sample the applied input voltage (V_in). Circuit ( 400 . 1000 ) according to claim 1 or 2, wherein the detection circuit ( 406 . 1004 ) has a comparator which is set up the applied input voltage (V_in) with the predetermined voltage value ( 404 ) to compare. Circuit ( 400 . 1000 ) according to one of claims 1 to 3, wherein the signal generating circuit ( 412 . 1006 ) is arranged to generate a rectified sine signal as the synchronization signal (I_sync). Circuit ( 400 . 1000 ) according to one of claims 1 to 4, wherein the signal generating circuit ( 412 . 1006 ) is arranged to generate a synchronization signal (I_sync) whose Period duration at a time interval of two consecutive pulse signals ( 514 ) corresponds. Circuit ( 400 . 1000 ) according to one of claims 1 to 5, further comprising: • an integrator ( 410 ), which between the detection circuit ( 406 . 1004 ) and the signal generation circuit ( 412 . 1006 ) and is set up, the time between two consecutive pulse signals ( 514 ) to provide a ramp signal ( 520 ) to create; and wherein the control circuit ( 142 . 1008 ), based on the ramp signal ( 520 ) the control signal (S) for the switch ( 124 ). Circuit ( 400 . 1000 ) according to claim 6, wherein the integrator ( 410 ) is set up such that the ramp signal ( 520 ) is reset when it is detected by the detection circuit ( 406 . 1004 ) the pulse signal ( 514 ) receives. Circuit ( 400 . 1000 ) according to one of claims 1 to 7, further comprising: a driver circuit ( 140 ) which is connected to the control circuit ( 142 ) and is set up, based on the control signal (S) a drive signal for the switch ( 124 ) to create. Circuit arrangement ( 600 ), comprising: • a switching converter with at least one switch ( 124 ) configured to allow a current flow through the switching converter; and • a switching circuit coupled to the switching converter ( 610 ) according to one of claims 1 to 8, wherein the circuit ( 610 ) to the switch ( 124 ) is coupled so that it is driven on the basis of the control signal (S). Procedure ( 1200 ) for providing a control signal for a switch ( 124 ) in a switching converter, the method comprising: • determining ( 1202 ) a voltage applied in the switching converter (V_in); • To compare ( 1204 ) of the voltage applied in the switching converter (V_in) with a predetermined voltage value ( 404 ); • Produce ( 1206 ) of a pulse signal ( 514 ), when it is determined that the voltage applied in the switching converter (V_in) below the predetermined voltage value ( 404 ) falls; • Produce ( 1208 ) of a synchronization signal (I_sync) on the basis of the generated pulse signals ( 514 ); and • generating ( 1210 ) of a control signal (S) for the switch ( 124 ) based on the synchronization signal (I_sync). Procedure ( 1200 ) according to claim 10, further comprising: adjusting the amplitude of the synchronization signal (I_sync) in accordance with a control signal (I_amplitude), which formed from a difference between a desired value (V_dc_ref) of the output voltage (V_dc) and the current value of the output voltage (V_dc) of the switching converter becomes. Procedure ( 1200 ) according to claim 11, wherein generating the control signal (I_amplitude) comprises: • determining ( 1302 ) an output voltage signal based on an output voltage (V_dc) of the switching converter; • Delay ( 1304 ) the output voltage signal by a time corresponding to one-half of a period of a parasitic oscillation of the output voltage signal; • Add ( 1306 ) the delayed output voltage signal to the output voltage signal to provide a composite output voltage signal (Z); • Subtract ( 1308 ) of the combined output voltage signal (Z) from a reference signal (V_dc_ref) of the output voltage of the switching converter, so that the actuating signal (C) is provided. Circuit ( 200 . 1100 ) for driving a switch in a switching converter, the circuit comprising: 1102 ), which as an input signal, an output voltage (V_dc) of the switching converter can be fed; A delay circuit ( 208 ) configured to delay the signal supplied thereto, which is dependent on the input signal, to delay a time corresponding to one-half of a period of a spurious oscillation in the input signal, so that a delayed input signal is generated; A first sub-circuit ( 206 ) configured to add the delayed input signal and the input signal to output a composite input signal (Z); A second sub-circuit ( 152 . 1108 ) connected to the first sub-circuit ( 206 ) is coupled and is arranged to subtract the combined input signal (Z) from a setpoint signal (V_dc_ref) of the output voltage of the switching converter and output a control signal (C); and a control circuit ( 142 . 1110 ), which is set up, based on the actuating signal (C) a control signal (S) for the switch ( 124 ). Circuit ( 200 . 1100 ) according to claim 13, further comprising: • a scaling circuit ( 204 ) which is arranged to scale the amplitude of the input signal to produce a scaled input signal and the delay circuit ( 208 ) is supplied; Where the delay circuit ( 208 ) is arranged to delay the scaled input signal by time, thereby forming a delayed scaled input signal; Where the first sub-circuit ( 206 ) is adapted to add the delayed scaled input signal and the input signal. Circuit ( 200 . 1100 ) according to claim 14, wherein the scaling circuit ( 204 ) is arranged to halve the amplitude of the input signal. Circuit ( 200 . 1100 ) according to claim 14 or 15, further comprising: a sampling circuit ( 202 ), which between the entrance ( 1102 ) and the scaling circuit ( 204 ) and is adapted to sample the input signal and the sampled input signal to the first sub-circuit ( 206 ) and the delay circuit ( 208 ) provide. Circuit ( 200 . 1100 ) according to claim 16, wherein the sampling circuit ( 202 ) is set up as a zero-order sample-and-hold gate. Circuit ( 200 . 1100 ) according to one of claims 13 to 17, further comprising: a regulator ( 150 ), which between the second sub-circuit ( 152 ) and the control circuit ( 142 ) is connected and is arranged to generate from the control signal (C) a regulated control signal (I_amplitude). Circuit ( 200 . 1100 ) according to claim 18, wherein the controller ( 150 ) is set up as a proportional-integral controller. Circuit ( 200 . 1100 ) according to one of claims 13 to 19, further comprising: a driver circuit ( 140 ) which is connected to the control circuit ( 142 ) and is set up, based on the control signal (S) a drive signal for the switch ( 124 ) to create. Circuit arrangement ( 600 ), comprising: • a switching converter with at least one switch ( 124 ) configured to allow a current flow through the switching converter; and • a switching circuit coupled to the switching converter ( 610 ) according to one of claims 13 to 20, wherein the circuit ( 610 ) to the switch ( 124 ) is coupled so that it is driven on the basis of the control signal (S). Procedure ( 1300 ) for providing a control signal (S) for a switch ( 124 ) in a switching converter, the method comprising: • determining ( 1302 ) an output voltage signal based on an output voltage (V_dc) of the switching converter; • Delay ( 1304 ) the output voltage signal by a time corresponding to one-half of a period of a parasitic oscillation of the output voltage signal; • Add ( 1306 ) the delayed output voltage signal to the output voltage signal to provide a composite output voltage signal (Z); • Subtract ( 1308 ) of the combined output voltage signal (Z) from a setpoint signal (V_dc_ref) of the output voltage of the switching converter, so that an actuating signal (C) is provided, 1310 ) of a control signal (S) for the switch ( 124 ) based on the control signal (C). Procedure ( 1300 ) according to claim 22, wherein the amplitude of the output voltage signal is scaled by halving the amplitude. Procedure ( 1300 ) according to any one of claims 22 to 23, wherein in generating ( 1310 ) of the control signal (S) from the actuating signal (C), a signal is subtracted, which corresponds to a current flowing through the switching converter current (I_in).

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