WO2008105372A1 - 磁気記憶装置の製造方法および磁気記憶装置 - Google Patents

磁気記憶装置の製造方法および磁気記憶装置 Download PDF

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Publication number
WO2008105372A1
WO2008105372A1 PCT/JP2008/053197 JP2008053197W WO2008105372A1 WO 2008105372 A1 WO2008105372 A1 WO 2008105372A1 JP 2008053197 W JP2008053197 W JP 2008053197W WO 2008105372 A1 WO2008105372 A1 WO 2008105372A1
Authority
WO
WIPO (PCT)
Prior art keywords
opening
storage device
magnetic storage
insulating film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/053197
Other languages
English (en)
French (fr)
Inventor
Haruo Furuta
Shuichi Ueno
Ryoji Matsuda
Tatsuya Fukumura
Takeharu Kuroiwa
Lien-Chang Wang
Eugene Chen
Yiming Huai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Grandis Inc
Original Assignee
Renesas Technology Corp
Grandis Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Grandis Inc filed Critical Renesas Technology Corp
Priority to US12/528,854 priority Critical patent/US8546151B2/en
Publication of WO2008105372A1 publication Critical patent/WO2008105372A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

　ＴＭＲ素子を含む磁気記憶装置の製造方法は、配線層が設けられた層間絶縁膜の上に、絶縁膜を形成する工程と、絶縁膜に、配線層が露出するように開口部を形成する開口工程と、開口部を埋めるように、絶縁層上に金属層を形成する金属層形成工程と、ＣＭＰ法を用いて絶縁層上の金属層を研磨除去し、開口部内に残った金属層を下部電極とするＣＭＰ工程と、下部電極上にＴＭＲ素子を形成する工程とを含む。また、磁気記憶装置は、配線層を備えた層間絶縁膜と、層間絶縁膜の上に設けられた絶縁膜と、絶縁膜に、配線層が露出するように設けられた開口部と、開口部の内面を覆うように設けられたバリアメタル層と、開口部を埋めるように、バリアメタル層上に設けられた下部電極と、下部電極に設けられたＴＭＲ素子とを含む。
PCT/JP2008/053197 2007-02-27 2008-02-25 磁気記憶装置の製造方法および磁気記憶装置 Ceased WO2008105372A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/528,854 US8546151B2 (en) 2007-02-27 2008-02-25 Method for manufacturing magnetic storage device and magnetic storage device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007046776A JP5080102B2 (ja) 2007-02-27 2007-02-27 磁気記憶装置の製造方法および磁気記憶装置
JP2007-046776 2007-02-27

Publications (1)

Publication Number Publication Date
WO2008105372A1 true WO2008105372A1 (ja) 2008-09-04

Family

ID=39721204

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053197 Ceased WO2008105372A1 (ja) 2007-02-27 2008-02-25 磁気記憶装置の製造方法および磁気記憶装置

Country Status (4)

Country Link
US (1) US8546151B2 (ja)
JP (1) JP5080102B2 (ja)
TW (1) TWI462233B (ja)
WO (1) WO2008105372A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011088359A1 (en) * 2010-01-15 2011-07-21 Qualcomm Incorporated Magnetic tunnel junction on planarized electrode
CN113272983A (zh) * 2018-11-20 2021-08-17 应用材料公司 自旋轨道矩磁阻式随机存取存储器及其制造方法
JP2022543359A (ja) * 2019-08-07 2022-10-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ガルバニック効果を克服するためのｔ字形底部電極を有するｍｒａｍ構造体

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5527649B2 (ja) * 2009-08-28 2014-06-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
EP2652791B1 (en) 2010-12-17 2017-03-01 Everspin Technologies, Inc. Magnetic random access memory integration having improved scaling
TWI420127B (zh) * 2011-07-05 2013-12-21 Voltafield Technology Corp 穿隧式磁阻感測器
TWI445225B (zh) * 2011-11-07 2014-07-11 Voltafield Technology Corp 磁阻元件結構形成方法
CN104752605A (zh) * 2013-12-31 2015-07-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9865798B2 (en) 2015-02-24 2018-01-09 Qualcomm Incorporated Electrode structure for resistive memory device
KR102399342B1 (ko) * 2015-08-21 2022-05-19 삼성전자주식회사 메모리 장치 및 그 제조 방법
KR102409755B1 (ko) * 2015-09-30 2022-06-16 삼성전자주식회사 자기 저항 메모리 소자 및 그 제조 방법
US10164169B2 (en) * 2016-09-30 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device having a single bottom electrode layer
JP2023128981A (ja) * 2022-03-04 2023-09-14 キオクシア株式会社 メモリデバイス及びメモリデバイスの製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004514286A (ja) * 2000-11-15 2004-05-13 モトローラ・インコーポレイテッド 自己配列磁気クラッド書き込み線およびその方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3677455B2 (ja) * 2001-02-13 2005-08-03 Ｎｅｃエレクトロニクス株式会社 不揮発性磁気記憶装置およびその製造方法
US6531371B2 (en) * 2001-06-28 2003-03-11 Sharp Laboratories Of America, Inc. Electrically programmable resistance cross point memory
JP2004119478A (ja) 2002-09-24 2004-04-15 Renesas Technology Corp 半導体記憶装置、不揮発性記憶装置および磁気記憶装置
JP4829502B2 (ja) * 2005-01-11 2011-12-07 シャープ株式会社 半導体記憶装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004514286A (ja) * 2000-11-15 2004-05-13 モトローラ・インコーポレイテッド 自己配列磁気クラッド書き込み線およびその方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011088359A1 (en) * 2010-01-15 2011-07-21 Qualcomm Incorporated Magnetic tunnel junction on planarized electrode
US8681536B2 (en) 2010-01-15 2014-03-25 Qualcomm Incorporated Magnetic tunnel junction (MTJ) on planarized electrode
KR101386182B1 (ko) 2010-01-15 2014-04-17 퀄컴 인코포레이티드 평탄화된 전극 상의 자기 터널 접합
US9082962B2 (en) 2010-01-15 2015-07-14 Qualcomm Incorporated Magnetic Tunnel Junction (MTJ) on planarized electrode
CN113272983A (zh) * 2018-11-20 2021-08-17 应用材料公司 自旋轨道矩磁阻式随机存取存储器及其制造方法
JP2022543359A (ja) * 2019-08-07 2022-10-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ガルバニック効果を克服するためのｔ字形底部電極を有するｍｒａｍ構造体

Also Published As

Publication number Publication date
TW200901390A (en) 2009-01-01
JP2008211011A (ja) 2008-09-11
TWI462233B (zh) 2014-11-21
JP5080102B2 (ja) 2012-11-21
US20100264501A1 (en) 2010-10-21
US8546151B2 (en) 2013-10-01

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