WO2008102285A1 - Circuit de protection et dispositif protégé contre les décharges électrostatiques, et procédé de protection - Google Patents

Circuit de protection et dispositif protégé contre les décharges électrostatiques, et procédé de protection Download PDF

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Publication number
WO2008102285A1
WO2008102285A1 PCT/IB2008/050523 IB2008050523W WO2008102285A1 WO 2008102285 A1 WO2008102285 A1 WO 2008102285A1 IB 2008050523 W IB2008050523 W IB 2008050523W WO 2008102285 A1 WO2008102285 A1 WO 2008102285A1
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WO
WIPO (PCT)
Prior art keywords
circuit
scr
transistor
voltage
voltage supply
Prior art date
Application number
PCT/IB2008/050523
Other languages
English (en)
Inventor
Olivier Quittard
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2008102285A1 publication Critical patent/WO2008102285A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Definitions

  • the invention relates to an electrostatic protection circuit, to a device protected against electrostatic discharge and a method of protecting the device.
  • Protection against electrostatic discharge (ESD) may be integrated onto a chip, especially an integrated circuit, by providing a defined low impedance channel to prevent thermal damage in silicon. Alternatively, an ESD voltage pulse may be clamped to a safe level.
  • ESD protection is a particular difficulty for mixed-voltage technologies, which are being extensively used for consumer electronic products.
  • One example is display drivers ICs where a low-voltage digital part controls high-voltage analogue outputs.
  • SCR semiconductor controlled rectifier
  • SCRs are used. Latch-up is a condition in which the SCR has stabilized in the on-state, and thereby provides an undesired low impedance path between the voltage supply rails, possibly draining a connected battery, or causing damage to the circuit.
  • the SCR device is particularly susceptible to latch-up, because of its very low holding voltage, which is typically below the supply voltage. Avoiding latch-up when using SCRs requires a major engineering effort to tune all of the layout parameters, which has to be repeated for each new technology. Moreover, SCRs still present some risk for ESD-induced latch-up (during system-level ESD testing or voltage spikes during normal operation mode, for example) because of their low holding voltage.
  • This invention relates specifically to SCR ESD protection solutions, and aims to provide a low area solution, with improved latch-up immunity, because it can be switched off during normal operation of the IC, and with rapid active triggering during an ESD pulse (or during other voltage spikes on supply buses).
  • an ESD protection circuit comprising: a semiconductor controlled rectifier (hereinafter "SCR") provided between first and second voltage supply terminals; a transistor circuit for controlling the triggering of the SCR, and which is adapted to turn the SCR on in response to a voltage surge on the first voltage supply terminal; an RC control circuit which is adapted to control the transistor circuit to turn the SCR off after a delay following the voltage surge.
  • SCR semiconductor controlled rectifier
  • the invention uses a transistor controlled SCR to provide ESD protection (for example a MOSFET controlled SCR).
  • the SCR is controlled actively both for switch on and switch off. This provides an arrangement that is immune to latch-up.
  • the design can be robust to process variations, and can quickly and easily be adapted for different high voltage supply requirements.
  • the SCR is used as a power device to give a high current capability.
  • the RC control circuit preferably comprises a resistor and capacitor in series between the first and second voltage supply lines, and wherein the junction between the resistor and capacitor provides a switch off control signal.
  • This switch off signal then decays in a predictable way after a voltage surge so that the predetermined delay is defined.
  • a drive circuit and/or an inverter may be provided, for processing the switch off control signal provided by the RC control circuit. This provides a more accurately defined (sharp) control signal for the transistor circuit.
  • the SCR preferably comprises has an equivalent circuit of: a first bipolar transistor between the first voltage supply terminal and the base of a second bipolar transistor, with the second bipolar transistor between the base of the first bipolar transistor and the second voltage supply terminal.
  • the transistor circuit can then comprise a first transistor for actively turning the SCR off by shorting the base and emitter of one of the bipolar transistors.
  • the transistor circuit can comprise a second transistor for actively turning the SCR on by shorting the collector and emitter of one of the bipolar transistors.
  • the transistor circuit preferably comprises a MOSFET circuit.
  • the invention also provides an ESD protected device comprising: an input pad; at least one device to be protected having a first terminal connected to the input pad; and an ESD protection circuit of the invention.
  • the invention also provides a method of providing ESD protection, comprising: controlling the triggering of a semiconductor controlled rectifier (hereinafter "SCR") provided between first and second voltage supply terminals, such that: the SCR is turned on in response to a voltage surge on a first voltage supply terminal; and the SCR is turned off by an RC control circuit after a delay following the voltage surge.
  • SCR semiconductor controlled rectifier
  • Figure 1 shows a known MOSFET controlled SCR
  • Figure 2 shows an ESD protection circuit of the invention
  • Figure 3 shows an ESD protected device of the invention.
  • the drawings are purely schematic and not to scale. Like components are given the same reference numerals in different figures.
  • the invention provides an ESD protection circuit which uses an actively controlled semiconductor controlled rectifier ("SCR").
  • SCR semiconductor controlled rectifier
  • a transistor circuit preferably a MOSFET circuit
  • RC control circuit labeled “RC trigger circuit” in Figure 2
  • RC trigger circuit is adapted to control the transistor circuit to turn the SCR off after a predetermined delay following a detected voltage surge.
  • Figure 1 shows a known MOSFET controlled SCR circuit, and which forms the main building block of the ESD protection circuit of the invention.
  • the circuit is represented by a first PNP bipolar transistor 10 between a first voltage supply terminal 12 (the anode) and the base of a second, NPN, bipolar transistor 14.
  • the second bipolar transistor 14 is between the base of the first bipolar transistor 10 and a second voltage supply terminal 16 (the cathode).
  • the two bipolar devices are integrated together, with the base of the PNP device functioning as the collector of the NPN device, and vice versa.
  • the SCR is controlled by a MOSFET transistor circuit, which comprises a first n-type transistor 18 for actively turning the SCR off by shorting the base and emitter of the bipolar transistor 10.
  • a second, p-type, transistor 20 is for actively turning the SCR on, by shorting the collector and emitter of the bipolar transistor 10.
  • the SCR may alternatively be turned on by shorting the collector and base of the bipolar transistor 14.
  • the MOSFET-controlled SCR shown in Figure 1 is conventionally used as a power switching device.
  • the emitters of the PNP and NPN bipolar transistors form the anode and cathode contacts, respectively, and the two control transistors have a common gate contact which forms the gate node 22 of the controllable SCR circuit.
  • the circuit When the gate node is tied to ground (VSS), the circuit operates with the SCR turned on, and thereby providing an ESD discharge path.
  • the circuit remains turned on until a current flow between the anode and cathode drops below a threshold level.
  • transistor 18 is off and transistor 20 is turned on.
  • This means the drain voltage of the transistor 20 is pulled high, giving a high base voltage for the bipolar transistor 14.
  • This turns the bipolar transistor 14 on, which in turn pulls the base voltage of the PNP bipolar transistor low, which turns transistor 10 on.
  • the two bipolar transistors are thus turned on, and the SCR is in an on state.
  • the SCR is kept on until the current flow drops below the so-called holding current.
  • the circuit When the gate node is tied to a high voltage (VDD), the circuit is actively switched off. In particular, the transistor 18 is turned on and the transistor 20 is turned off.
  • the base-to-emitter voltage of the PNP bipolar transistor is thus set at VSS (e.g. OV), and this turns off the PNP transistor 18, which in turn switches off the NPN transistor 10, so that the SCR is turned off.
  • the MOSFET-controlled SCR can be both turned on and turned off using the gate node. Fast turn-on and turn-off behaviour can be obtained due to the MOSFET switching devices, and high current capability is possible due to the bipolar SCR device.
  • the invention is based on the recognition that this type of circuit can be controlled to provide actively triggered ESD protection using an RC control circuit, to provide latch-up immunity, and high current capability.
  • Figure 2 shows an ESD protection circuit of the invention, and comprises a MOSFET controlled SCR 30 which functions as described with reference to Figure 1 , an RC control circuit 32, a pre-dhver circuit 34 and an inverter circuit 36.
  • the resistors R2 and R3 represent the inherent well resistance of both p-well and n-well devices.
  • the RC control circuit 32 is adapted to control circuit 30 to turn the SCR off after a predetermined delay following a voltage surge.
  • the RC control circuit comprises a resistor RO and capacitor CO in series between the anode 12 and cathode 16.
  • the junction 38 between the resistor and capacitor provides a switch off control signal. This switch off signal then ramps up in a predictable way after a voltage surge so that a predetermined delay is defined.
  • the RC decay signal is provided to a pre-dhver circuit 34 which provides a signal with a sharp transition.
  • the pre-dhver circuit comprises a PMOS transistor 40 which drives a resistive load R1.
  • the steady state condition is thus a low signal on line 42.
  • This is converted to a high signal by the inverter 36, which has transistor MP1 on.
  • This high output signal on the gate line 44 turns off the SCR as explained above.
  • the ESD pulse raises the voltage on VDD, which pulls up the source voltage of the p-type transistor 40.
  • the gate voltage of transistor 40 is initially held low by the capacitor CO which cannot change voltage instantaneously. As a result, the transistor 40 is initially turned on.
  • the voltage on the drain of the transistor 40 rises and turns on the inverter n-type transistor MN1 , so that the voltage on the gate line 44 is pulled down to the voltage VSS.
  • this turns on the SCR to provide an ESD protection discharge path.
  • the gate voltage of the transistor 40 will vary as the capacitor CO charges in response to the change in the voltage VDD.
  • the gate voltage will reach a voltage which turns the transistor 40 back off after a time delay which depends on the RC time constant. However, the transistor 40 should remain turned on for the duration of the ESD event. After the ESD event, the voltage VDD will return to its previous levels, and the steady state condition will again be reached.
  • the control circuit RC time constant must therefore be large enough to keep the SCR on throughout the duration of the ESD pulse. On the other hand, it has to be small enough to switch off the SCR after the supply voltage has stabilized to the normal circuit operating state. With a resistor value of 250k ⁇ and a capacitance value of 4.OpF, an RC time constant of 1 ⁇ s is obtained.
  • the invention uses a controlled SCR to provide ESD protection.
  • the SCR is controlled actively both for switch-on and switch-off. This provides an arrangement that is immune to latch-up.
  • the design can be robust to process variations, and can quickly and easily be adapted for different high voltage supply requirements.
  • the SCR is used as a power device to give a high current capability.
  • the SCR device is turned on during an ESD pulse or a voltage spike on VDD.
  • the structure of the MOSFET-controlled SCR enables the circuit to be automatically turned off once the overstress is finished (for example after a defined RC delay).
  • the RC control circuit turns on the SCR on the rising edge of the ESD pulse (and not only on the peak voltage reached). This widens the design window compared to the more conventional clamp arrangement, in which the clamp is allowed to turn on only after the ESD pulse voltage has exceeded the supply voltage.
  • the invention can enable a significant decrease in area consumption, directly dependent on the currently capability.
  • the active control of the switch on and off of the SCR circuit gives latch- up immunity, both for DC latch-up and ESD induced latch-up.
  • the invention is of particular interest for all CMOS technologies, including Advanced CMOS. Ranges of application of the invention include small and large display drivers, SMART power technologies, and automotive technologies.
  • Figure 3 shows an ESD protected device comprising input pads 54,56, in which a device to be protected 50 has a first terminal connected to the first input pad 54 and a second terminal connected the second input pad 56.
  • ESD protection circuit 52 of the invention provides a discharge path between the input pads.
  • the SCR will be triggered.
  • the timing of the end of the ESD protection period is determined by the RC time. After a time longer than the RC time, the control circuit will return to its original (off) state, thus switching the SCR off.
  • the SCR can only be active during pulses shorter than the RC time, which provides perfect immunity against DC latch-up.
  • the holding voltage does not need to be higher than the nominal voltage swings, in order to prevent accidental latch-up issues, as would be required for conventional SCRs, used as ESD protection devices.
  • the triggering voltage has to be lower than the minimum failure voltage of the circuit being protected, to ensure that these circuits do not suffer any damage.
  • the inverter may not be required.
  • the PMOS and NMOS transistors may be swapped and the inverter removed.
  • the pre-dhve circuit functions as an inverter, and its resistor could be replaced by an NMOS transistor, so that the pre-drive circuit can combine pre- dhve and inverter functions, further reducing the area and power consumption.
  • the pre-drive circuit is also optional, and the inverter circuit can implement the waveform shaping function of the pre-driver circuit. Indeed, both the inverter and pre-drive circuits are not essential to the invention, and the RC circuit may directly supply a control signal to a suitable MOSFET controlled SCR.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Circuit de protection contre les décharges électrostatiques, comportant un thyristor prévu entre des première et seconde bornes d'alimentation en tension. Un circuit à transistors commande le déclenchement du thyristor et est apte à allumer le thyristor par suite d'une surtension sur la première borne d'alimentation en tension. Un circuit de commande RC est apte à commander le circuit à transistors pour éteindre le thyristor au bout d'un laps de temps faisant suite à la surtension.
PCT/IB2008/050523 2007-02-20 2008-02-13 Circuit de protection et dispositif protégé contre les décharges électrostatiques, et procédé de protection WO2008102285A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07102742.9 2007-02-20
EP07102742 2007-02-20

Publications (1)

Publication Number Publication Date
WO2008102285A1 true WO2008102285A1 (fr) 2008-08-28

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PCT/IB2008/050523 WO2008102285A1 (fr) 2007-02-20 2008-02-13 Circuit de protection et dispositif protégé contre les décharges électrostatiques, et procédé de protection

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9509137B2 (en) 2014-01-06 2016-11-29 Macronix International Co., Ltd. Electrostatic discharge protection device
CN111599806A (zh) * 2020-05-18 2020-08-28 深圳市晶扬电子有限公司 用于esd保护的低功耗双向scr器件和静电防护电路
US10978444B2 (en) * 2018-09-19 2021-04-13 Nxp B.V. RC-triggered bracing circuit
US20230402448A1 (en) * 2022-06-14 2023-12-14 Analog Devices, Inc. Electrostatic discharge protection for high speed transceiver interface

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012431A1 (en) * 2002-07-17 2004-01-22 Scott Hareland Semiconductor controlled rectifier / semiconductor controlled switch based esd power supply clamp with active bias timer circuitry
US20050275984A1 (en) * 2004-06-14 2005-12-15 King Billions Electronics Co., Ltd. Latch-up-free ESD protection circuit using SCR
WO2005124863A1 (fr) * 2004-06-16 2005-12-29 Austriamicrosystems Ag Systeme de protection pour circuit a semi-conducteurs comprenant une structure de thyristor et procede pour faire fonctionner ce systeme

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012431A1 (en) * 2002-07-17 2004-01-22 Scott Hareland Semiconductor controlled rectifier / semiconductor controlled switch based esd power supply clamp with active bias timer circuitry
US20050275984A1 (en) * 2004-06-14 2005-12-15 King Billions Electronics Co., Ltd. Latch-up-free ESD protection circuit using SCR
WO2005124863A1 (fr) * 2004-06-16 2005-12-29 Austriamicrosystems Ag Systeme de protection pour circuit a semi-conducteurs comprenant une structure de thyristor et procede pour faire fonctionner ce systeme

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9509137B2 (en) 2014-01-06 2016-11-29 Macronix International Co., Ltd. Electrostatic discharge protection device
US10978444B2 (en) * 2018-09-19 2021-04-13 Nxp B.V. RC-triggered bracing circuit
CN111599806A (zh) * 2020-05-18 2020-08-28 深圳市晶扬电子有限公司 用于esd保护的低功耗双向scr器件和静电防护电路
CN111599806B (zh) * 2020-05-18 2022-06-21 深圳市晶扬电子有限公司 用于esd保护的低功耗双向scr器件和静电防护电路
US20230402448A1 (en) * 2022-06-14 2023-12-14 Analog Devices, Inc. Electrostatic discharge protection for high speed transceiver interface
US11942473B2 (en) * 2022-06-14 2024-03-26 Analog Devices, Inc. Electrostatic discharge protection for high speed transceiver interface

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