WO2008069271A1 - Dispositif d'affichage au plasma, et son procédé de commande - Google Patents

Dispositif d'affichage au plasma, et son procédé de commande Download PDF

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Publication number
WO2008069271A1
WO2008069271A1 PCT/JP2007/073590 JP2007073590W WO2008069271A1 WO 2008069271 A1 WO2008069271 A1 WO 2008069271A1 JP 2007073590 W JP2007073590 W JP 2007073590W WO 2008069271 A1 WO2008069271 A1 WO 2008069271A1
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Prior art keywords
electrode
discharge
period
voltage
data
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PCT/JP2007/073590
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English (en)
Japanese (ja)
Inventor
Toshiyuki Maeda
Hidehiko Shoji
Original Assignee
Panasonic Corporation
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Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to EP07850199A priority Critical patent/EP2063409A4/fr
Priority to US12/513,692 priority patent/US8294636B2/en
Priority to JP2008548329A priority patent/JP4890563B2/ja
Priority to CN2007800453777A priority patent/CN101563718B/zh
Publication of WO2008069271A1 publication Critical patent/WO2008069271A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/298—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using surface discharge panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/2803—Display of gradations

Definitions

  • the present invention relates to a plasma display device and a driving method thereof.
  • a typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged opposite to each other. Yes.
  • a plurality of pairs of display electrodes each consisting of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes.
  • the back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of partition walls formed in parallel with the data electrodes on each of them.
  • a phosphor layer is formed on the side surface of the partition wall.
  • the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed, and the discharge gas is sealed in the internal discharge space.
  • a discharge cell is formed at a portion where the display electrode and the data electrode face each other.
  • ultraviolet light is generated by gas discharge in each discharge cell, and the RGB color phosphors are excited and emitted with this ultraviolet light to perform color display.
  • Patent Document 1 discloses a novel driving method in which light emission not related to gradation display is reduced as much as possible to suppress an increase in black luminance and an contrast ratio is improved. The driving method is briefly described below!
  • Each subfield has an initialization period, an address period, and a sustain period.
  • initializing discharge is simultaneously performed in all the discharge cells, the history of wall charges for individual individual discharge cells is erased, and it is necessary for the subsequent address operation.
  • Form wall charges In the subsequent address period, the scan panel is sequentially applied to the scan electrodes, and the address panel corresponding to the image signal to be displayed is applied to the data electrodes, and the address discharge is selectively performed between the scan electrodes and the data electrodes.
  • the sustain period a predetermined number of sustain pulses corresponding to the luminance weight are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light.
  • Patent Document 2 describes a driving method that solves the problem that a bright spot is visually recognized in a discharge cell in which excessive positive wall charges are accumulated on a scan electrode.
  • An abnormal wall charge erasing section is provided that applies a positive rectangular waveform voltage to the scan electrode during the all-cell initialization period or the selection initialization period, and then applies a negative rectangular waveform voltage to the scan electrode.
  • a strong rectangular discharge is generated at the abnormal wall charge erasing portion with a positive rectangular waveform voltage applied to the scan electrode.
  • This strong! / Discharge causes the wall charges to be inverted, and then an erasing discharge is generated by the negative rectangular waveform voltage applied to the scanning electrodes, thereby erasing the wall charges.
  • Patent Document 1 Japanese Patent Laid-Open No. 2000-242224
  • Patent Document 2 JP-A-2005-326612
  • a discharge cell whose discharge start voltage has greatly decreased due to secular change or the like causes discharge due to a positive rectangular waveform voltage applied to the scan electrode in the abnormal wall charge erasing portion, and is applied to the subsequent scan electrode.
  • An erasing discharge is caused by the negative rectangular waveform voltage, and the wall charges are erased.
  • the wall charge is erased in the abnormal wall charge erasing portion even though excessive positive wall charge is not accumulated on the scan electrode. Cannot perform proper write operations.
  • An object of the present invention is to provide a plasma display device capable of performing normal write operation and displaying an image with good quality even in a discharge cell having a greatly reduced discharge start voltage, and a driving method thereof. Is to provide.
  • a plasma display device includes a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes.
  • a plasma display device driven by a subfield method including a subfield comprising: a scan electrode drive circuit that drives a scan electrode; a sustain electrode drive circuit that drives a sustain electrode; and a data electrode drive circuit that drives a data electrode
  • at least one subfield of the plurality of subfields includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge can be performed, and the scan electrode driving circuit includes a first period within the initialization period.
  • an upward ramp waveform voltage is applied to the scan electrode, the scan electrode is used as an anode, and the sustain electrode and data electrode are used as a cathode
  • a first initializing discharge is generated, and a downward ramp waveform voltage is applied to the scanning electrode in the second period after the first period within the initializing period so that the scanning electrode serves as a cathode and the sustaining electrode and the data electrode serve as an anode.
  • the second initializing discharge is generated, the positive rectangular waveform voltage and the negative rectangular waveform voltage are applied to the scan electrode in the third period after the second period in the initializing period, and the data
  • the electrode driving circuit applies a positive rectangular waveform voltage to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the third period. To be applied.
  • At least one subfield of the plurality of subfields includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible.
  • a first initialization is performed in which an up-slope waveform voltage is applied to the scan electrode by the scan electrode driving circuit, and the scan electrode serves as an anode and the sustain electrode and the data electrode serve as a cathode. A discharge is generated. As a result, negative wall charges are stored on the scan electrodes, and positive wall charges are stored on the sustain electrodes and the data electrodes.
  • a downward ramp waveform voltage is applied to the scanning electrode by the scan electrode driving circuit, and the scan electrode serves as a cathode, and the sustain electrode and the data electrode serve as an anode.
  • a second initializing discharge is generated. Thereby, the wall charge on the scan electrode and the wall charge on the sustain electrode are reduced, and the wall charge on the data electrode is adjusted to a value suitable for the write operation.
  • a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scanning electrode by the scan electrode driving circuit. Further, in the third period, a positive rectangular waveform voltage is applied to the data electrode by the data electrode driving circuit between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.
  • a discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scanning electrode! /.
  • the discharge cell that accumulates excessive wall charges is discharged with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scanning electrode.
  • the discharge becomes a state where the erasing discharge is forcibly terminated in the middle. The condition is cleared.
  • the wall charge inside the discharge cell is erased.
  • the wall charge is not erased in the third period of the initialization period, and thus a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.
  • the data electrode drive circuit may continuously apply two or more positive rectangular waveform voltages to the data electrode in the third period! /.
  • the data electrode driving circuit continuously applies two or more positive rectangular waveform voltages to the data electrode in the third period, and the voltage of the rectangular waveform voltage applied first to the data electrode
  • the application time may be the shortest of the voltage application periods of a plurality of rectangular waveform voltages applied to the data electrodes.
  • a plasma display device includes a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes.
  • a plasma display device that is driven by a subfield method including a subfield of a scan electrode, a scan electrode drive circuit that drives a scan electrode, a sustain electrode drive circuit that drives a sustain electrode, and a data electrode drive circuit that drives a data electrode, And at least one subfield of the plurality of subfields includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible, and the scan electrode driving circuit includes a first period of the initialization period.
  • a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scan electrodes, and the data electrode driver circuit In this period, a positive rectangular waveform voltage is applied to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.
  • At least one subfield of the plurality of subfields includes an initialization period in which the wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible.
  • a downward ramp waveform voltage is applied to the scan electrode by the scan electrode driving circuit, and an initialization discharge is generated with the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. Is done.
  • the sustain discharge is performed in the sustain period of the previous subfield, and in the discharge cell, the wall charge on the scan electrode and the wall charge on the sustain electrode are reduced, and the wall charge on the data electrode is also suitable for the write operation. Adjusted to the value.
  • the scan electrode driving circuit applies a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scan electrodes.
  • the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode are During this period, a positive rectangular waveform voltage is applied to the data electrode by the data electrode driving circuit.
  • a discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scanning electrode! /.
  • the discharge cell that accumulates excessive wall charges is discharged with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scanning electrode.
  • the discharge becomes a state where the erasing discharge is forcibly terminated in the middle. The condition is cleared.
  • the wall charge inside the discharge cell is erased.
  • a driving method of a plasma display device includes: a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes; A driving method of a plasma display device that is driven by a subfield method in which a field period includes a plurality of subfields, the step of driving a scan electrode, the step of driving a sustain electrode, and the step of driving a data electrode And at least one subfield of the plurality of subfields includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible, and the step of driving the scan electrode is performed within the initialization period.
  • At least one subfield of the plurality of subfields includes an initialization period in which the wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible.
  • an upward ramp waveform voltage is applied to the scan electrode, and a first initialization discharge is generated with the scan electrode as an anode and the sustain electrode and the data electrode as a cathode.
  • a first initialization discharge is generated with the scan electrode as an anode and the sustain electrode and the data electrode as a cathode.
  • negative wall charges are stored on the scan electrodes
  • positive wall charges are stored on the sustain electrodes and the data electrodes.
  • a downward ramp waveform voltage is applied to the scan electrode, and a second initial period in which the scan electrode is a cathode and the sustain electrode and the data electrode are an anode. A discharge is generated. Thereby, the wall charge on the scan electrode and the wall charge on the sustain electrode are reduced, and the wall charge on the data electrode is also adjusted to a value suitable for the write operation.
  • a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scan electrodes.
  • a positive rectangular waveform voltage is applied to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.
  • a discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scanning electrode! /.
  • the discharge cell that accumulates excessive wall charges is discharged with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scanning electrode.
  • the discharge becomes a state where the erasing discharge is forcibly terminated in the middle. The condition is cleared.
  • the wall charge inside the discharge cell is erased.
  • the wall charges are not erased during the third period of the initialization period, so that a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.
  • the step of driving the data electrode may include a step of continuously applying two or more positive-polarity rectangular waveform voltages to the data electrode in the third period.
  • the step of driving the data electrode includes a step of continuously applying two or more positive rectangular waveform voltages to the data electrode in the third period, and is applied to the data electrode first.
  • the voltage application time of the rectangular waveform voltage is the number of rectangles applied to the data electrode. It may be the shortest during the voltage application period of the waveform voltage.
  • a discharge cell with a small discharge delay among the discharge cells having a reduced discharge start voltage can be discharged with a rectangular waveform voltage applied first. This prevents the wall charges from being erased during the third period of the initialization period even when the discharge delays of the discharge cells in which the discharge start voltage has decreased are different. Therefore, a normal write operation is performed.
  • a driving method of a plasma display device includes a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes.
  • a driving method of a plasma display device that is driven by a subfield method in which a field period includes a plurality of subfields, the step of driving a scan electrode, the step of driving a sustain electrode, and the step of driving a data electrode
  • at least one subfield of the plurality of subfields includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge can be performed.
  • a downward ramp waveform voltage is applied to the scan electrode, the scan electrode becomes the cathode, and the sustain electrode and data electrode
  • An initializing discharge to be polar and a step of applying a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scanning electrode in a second period after the first period of the initializing period.
  • the step of driving the data electrode includes applying a positive rectangular waveform voltage to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the second period. Includes steps.
  • At least one subfield of the plurality of subfields includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible.
  • a downward ramp waveform voltage is applied to the scan electrode, and an initialization discharge is generated with the scan electrode as a cathode and the sustain electrode and the data electrode as an anode.
  • the sustain discharge is performed in the sustain period of the previous subfield, and in the discharge cell, the wall charge on the scan electrode and the wall charge on the sustain electrode are reduced, and the wall charge on the data electrode is also a value suitable for the write operation.
  • the discharge delay is large, the discharge cell voltage greatly exceeds the discharge start voltage at the time of occurrence of discharge in the first period of the initialization period. /, Discharge occurs. Or, strong discharge using the data electrode as a cathode! As a result, excessive positive wall charges are accumulated on the scan electrodes.
  • the positive rectangular waveform voltage and the negative rectangular waveform voltage are applied to the scan electrodes.
  • the positive rectangular waveform voltage is applied to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.
  • a discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scanning electrode! /.
  • the discharge cell that accumulates excessive wall charges is discharged with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scanning electrode.
  • the discharge becomes a state where the erasing discharge is forcibly terminated in the middle. The condition is cleared.
  • the wall charge inside the discharge cell is erased.
  • the wall charges are not erased in the second period of the initialization period, so that a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.
  • a discharge cell having a reduced discharge start voltage is! / Since the wall charges are not erased in the final period, normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.
  • FIG. 1 is a perspective view showing a main part of a panel used in the first embodiment of the present invention.
  • Fig. 2 is an electrode array diagram of the panel according to the first embodiment of the present invention.
  • FIG. 3 is a block diagram of a plasma display device using the panel driving method.
  • Figure 4 shows the drive waveform applied to each electrode of the panel.
  • FIG. 5 is a circuit diagram of the data electrode driving circuit according to the first embodiment of the present invention.
  • FIG. 6 is a circuit diagram of the scanning electrode driving circuit according to the first embodiment of the present invention.
  • FIG. 7 is a circuit diagram of a sustain electrode driving circuit according to the first embodiment of the present invention.
  • FIG. 8 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the first embodiment of the present invention.
  • FIG. 9 is a waveform diagram of driving applied to each electrode of the panel according to the second embodiment of the present invention.
  • FIG. 10 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the second embodiment of the present invention.
  • FIG. 11 is a waveform diagram of driving applied to each electrode of the panel according to the third embodiment of the present invention.
  • FIG. 12 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the third embodiment of the present invention.
  • FIG. 13 is a waveform diagram of driving applied to each electrode of the panel in the fourth embodiment of the present invention.
  • FIG. 14 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the fourth embodiment of the present invention.
  • FIG. 1 is an exploded perspective view showing the structure of panel 10 in the first exemplary embodiment of the present invention.
  • a plurality of display electrode pairs 28 composed of scanning electrodes 22 and sustaining electrodes 23 are formed.
  • a dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24.
  • a plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon.
  • a phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided.
  • the front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 28 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is sealed with glass frit or the like. Sealed with material.
  • a mixed gas of neon and xenon is sealed as a discharge gas.
  • the discharge space is divided into a plurality of sections by the barrier ribs 34, and discharge cells are formed at the intersections of the display electrode pairs 28 and the data electrodes 32! /. These discharge cells discharge and emit light to display an image.
  • the structure of the panel is not limited to the above-described one, and for example, it may be provided with a stripe-shaped partition wall.
  • FIG. 2 is an electrode array diagram of the panel in accordance with the exemplary embodiment of the present invention.
  • N scan electrodes SCN;! To SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS;! To SUSn (sustain electrode 5 in FIG. 1) are alternately arranged along the row direction.
  • M data electrodes D;! To Dm (data electrode 9 in FIG. 1) are arranged.
  • MX n are formed in the discharge space.
  • FIG. 3 is a circuit block diagram of plasma display device 1 in the first exemplary embodiment of the present invention.
  • the plasma display apparatus 1 supplies necessary power to the panel 10, the image signal processing circuit 51, the data electrode drive circuit 52, the scan electrode drive circuit 53, the sustain electrode drive circuit 54, the timing generation circuit 55, and each circuit block. Power supply circuit (not shown).
  • the image signal processing circuit 51 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield.
  • Data electrode drive circuit 52 is a subfield Each image data is converted into a signal corresponding to each data electrode Dl to Dm, and each data electrode D;! To Dm is driven.
  • the timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks.
  • the scan electrode drive circuit 53 has a sustain pulse generation circuit 100 for generating sustain pulses to be applied to the scan electrodes SCN ;! to SCNn during the sustain period, and each scan electrode SCN ;! ⁇ Drive each SCNn.
  • the sustain electrode drive circuit 54 has a circuit for applying the voltage Vel to the sustain electrode SUS ;! to SUSn during the initialization period, and a sustain electrode for generating the sustain pulse to be applied to the sustain electrode SUS ;! to SUSn during the sustain period.
  • a sustain generation circuit 200 for driving the sustain electrodes SUS1 to SUSn based on the timing signal.
  • one field is divided into 10 subfields (first SF, second SF,..., And 10th SF), and each subfino red is (1, 2, 3, 6). , 11, 18, 30, 44, 60 and 80).
  • the field is configured so that the luminance weight increases toward the rear subfield.
  • FIG. 4 is a drive waveform diagram applied to each electrode of the panel in the first exemplary embodiment of the present invention, and shows a subfield having an initialization period for performing the all-cell initialization operation (hereinafter referred to as “all-cell initials”).
  • the driving waveforms of a subfield having an initialization period for performing a selective initialization operation (hereinafter abbreviated as “selective initialization subfield”) are shown.
  • Figure 4 shows the drive waveform diagram with the first SF as the all-cell initialization subfield and the second SF as the selective initialization subfield.
  • the entire cell initialization period is divided into the following three periods: the first half (first period), the second half (second period), and the abnormal charge erasure section (third period). .
  • the sustain electrodes SUS;! To SUSn are held at 0 (V)
  • the data electrodes D;! To Dm are held at the positive voltage Vd (V)
  • the scan electrodes SCN ⁇ Slowly from the voltage Vp (V) below the discharge start voltage to the voltage Vr (V) exceeding the discharge start voltage with respect to SCNn Ascending ramp waveform voltage is applied. Then, a weak initializing discharge is generated with the scan electrodes SCN ;! to SCNn as the anode and the sustain electrodes SUS;! To SUSn and the data electrodes Dl to Dm as the cathode.
  • the first weak initializing discharge is generated in all the discharge cells, negative wall voltage is stored on the scan electrodes SCN;! To SCNn and the sustain electrodes SUS;! To SUSn and the data electrode D;! ⁇ Positive wall voltage is stored on Dm.
  • the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.
  • the sustain electrode SUS;! To SUSn is kept at the positive voltage Vel (V)
  • the data electrode D;! To Dm is kept at O (V)
  • the scan electrode SCN Apply a falling ramp waveform voltage that slowly decreases from voltage Vg (V) to voltage (Va + Vset2) (V).
  • Vg voltage
  • Va + Vset2 voltage
  • a second weak initializing discharge is generated with the scan electrodes SCN ;! to SCNn as the cathode and the sustain electrodes SUS ;! to SUSn and the data electrodes D;! To Dm as the anode.
  • the initializing operation of the all-cell initializing subfield is an all-cell initializing operation for generating an initializing discharge in all the discharge cells.
  • the discharge cell is caused to discharge by the slowly rising waveform voltage applied to the scan electrodes SCN ;! to SCN n. Since the voltage greatly exceeds the discharge start voltage, a strong discharge is generated instead of a weak discharge. Alternatively, a strong discharge using the data electrodes Dl to Dm as a cathode is generated in advance. Then, excessive negative wall charges are accumulated on the scan electrodes SCN ;! to SCNn. Then, in the latter half of the initialization period, the discharge cell again generates a strong discharge while applying a falling ramp waveform voltage to the scan electrodes SCN ;! to SCNn, and an excessive positive voltage is applied to the scan electrodes SCN ;! to SCNn. Wall charges are accumulated.
  • the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period.
  • the discharge cells discharged with the positive voltage Vd (V) applied to the data electrodes D ;! to Dm are not discharged with the negative voltage Va (V) applied to the scan electrodes SCN ;! to SCNn.
  • the discharge cell in which abnormal wall charges are accumulated is the positive voltage Vd (V) applied to the data electrodes D1 to Dm or the negative voltage Va (V) applied to the scan electrodes SCN ;! to SCNn. Discharge.
  • the discharge cell is discharged with the positive voltage Vd (V) applied to the data electrode D;!
  • the discharge is in a state where the erasing discharge is forcibly terminated halfway, but abnormally.
  • the state where wall charges are accumulated is eliminated.
  • a discharge cell in which an erasure discharge is generated with a negative pulse voltage Va (V) applied to scan electrodes SCN1 to SCNn the wall voltage inside the discharge cell is erased.
  • scan electrode SCN ;! SCNn is applied with negative voltage Va (V) and scan electrode SCN ;! SCNn is held at voltage Vc (V) because voltage Vc (V) is voltage Va (V
  • Vc (V) is voltage Va (V
  • Vd positive write pulse voltage
  • Va scan pulse voltage
  • the voltage at the intersection of the data electrode Dk and the scan electrode SCN1 is the magnitude of the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SCN1 to the externally applied voltage (Vd – Va) (V). Is added to the value and exceeds the discharge start voltage.
  • sustain electrodes SUS ;! to SUSn are returned to 0 (V), and positive sustain pulse voltage Vs (V) is applied to scan electrodes SC N ;! to SCNn.
  • V sustain pulse voltage
  • the voltage between scan electrode SCNi and sustain electrode SUSi is equal to the sustain pulse voltage Vs (V) of the wall voltage on scan electrode SCNi and sustain electrode SUSi.
  • the magnitude is added up and exceeds the discharge start voltage.
  • Sustain discharge occurs between scan electrode SCNi and sustain electrode SU Si, negative wall charges are accumulated on scan electrode SCNi, and positive wall charges are accumulated on sustain electrode SUSi. At this time, positive wall charges are also accumulated on the data electrode Dk.
  • sustain pulse voltage alternately to scan electrodes SCN1 to SCNn and sustain electrodes SUS;! To SUSn sustain discharge is continuously performed in the discharge cells in which the address discharge is generated in the address period.
  • a so-called narrow pulse was applied between the scan electrode SCN;! To SCNn and the sustain electrode SUS;! To SUS n to leave a positive wall charge on the data electrode Dk.
  • the wall charges on the scan electrodes SCN;! To SCNn and the sustain electrodes SUS;! To SUSn are erased.
  • sustain electrodes SUS;! To SUSn are held at Vel (V)
  • data electrodes D1 to Dm are held at 0 (V)
  • scan electrodes SCN;! To SCNn are set to Vq (V).
  • the initializing operation of the selective initializing subfield is a selective initializing operation in which the initializing discharge is performed in the discharge cells in which the sustain discharge has been performed in the previous subfield.
  • the writing period and the sustaining period are the same as the writing period and the sustaining period of the all-cell initialization subfield, description thereof is omitted.
  • the power showing an example in which the subfield for performing the all-cell initialization operation is one subfield, but the present invention is not limited to this.
  • an all-cell initializing operation may be performed in a plurality of subfields, and one or more all-cell initializing periods may be provided in one or more all-cell initializing periods. Yes.
  • FIG. 5 is a circuit diagram of the data electrode driving circuit 52 according to the first embodiment of the present invention.
  • the data electrode driving circuit 52 includes a power supply VD that generates a voltage Vd, switching elements Q ID;! To QlDm, and switching elements Q2Dl to Q2Dm. Then, the data electrodes 32 (D;! To Dm) are independently connected to the power supply VD via the switching elements Q1D;! To QlDm and clamped to the voltage Vd. Further, the data electrodes 32 (D;! To Dm) are independently grounded via the switching elements Q2D1 to Q2 Dm, and are clamped to 0 (V). In this way, the data electrode driving circuit 52 drives the data electrodes 32 independently, and applies a positive write pulse voltage Vd to the data electrodes 32.
  • control signals SD;! To SDm of the data electrode driving circuit 52 are given as timing signals to the data electrode driving circuit 52 by the timing generation circuit 55 and the image signal processing circuit 51.
  • FIG. 6 is a circuit diagram of scan electrode drive circuit 53 in the first exemplary embodiment of the present invention.
  • Scan electrode drive circuit 53 includes sustain pulse generation circuit 100 that generates a sustain pulse, initialization waveform generation circuit 300 that generates an initialization waveform, scan pulse generation circuit 400 that generates a scan pulse, and scan electrode 22 with voltage Va.
  • a switching element Q 15 for clamping to is provided.
  • the sustaining noise generation circuit 100 includes a power recovery unit 110 and a clamp unit 120.
  • the power recovery unit 110 includes a power recovery capacitor C10, switching elements Ql l and Q12, backflow prevention diodes Dl l and D12, and resonance inductors Ll l and L12.
  • the clamp unit 120 includes switching elements Q13 and Q14. The power recovery unit 110 and the clamp unit 120 are connected to the scan electrode 22 via the scan pulse generation circuit 400.
  • the power recovery unit 110 performs LC resonance between the panel capacitance (not shown) of the plasma display panel and the inductor L11 or the inductor L12 to raise the sustaining voltage and Form a falling edge.
  • the sustain pulse voltage rises, the charge stored in the power recovery capacitor C10 is moved to the interelectrode capacitance Cp via the switching element Ql1, the diode D11, and the inductor L11.
  • the sustain node falls, the charge stored in the panel capacitance is returned to the power recovery capacitor C10 via the inductor L12, the diode D12, and the switching element Q12. In this way, the sustaining noise is applied to the scanning electrode 22.
  • the power recovery capacitor C10 has a sufficiently large capacity compared to the interelectrode capacitance Cp, and is charged to about Vs / 2, which is half of the voltage Vs of the power supply VS so as to function as a power supply for the power recovery unit 110. ing.
  • scan electrode 22 is connected to power supply VS via switching element Q13, and scan electrode 22 is clamped to voltage Vs. Further, the scanning electrode 22 is grounded via the switching element Q14 and clamped to 0 (V). In this way, the voltage clamp unit 120 drives the scan electrode 22. Therefore, the impedance at the time of voltage application by the voltage clamp unit 120 is small, and a large discharge current due to a strong sustain discharge can be stably passed.
  • sustain pulse generating circuit 100 controls switching element Ql 1, switching element Q 12, switching element Q 13, and switching element Q 14 to control scan electrode 22 using power recovery unit 110 and voltage clamp unit 120. Apply maintenance noise.
  • switching elements can be configured using generally known elements such as MOSFET (metal oxide semiconductor field effect transistor) or IGBT (insulated gate bipolar transistor).
  • the initialization waveform generation circuit 300 includes Miller integration circuits 310 and 320, generates the above-described initialization waveform, and controls the initialization voltage in the all-cell initialization operation.
  • the Mira integrating circuit 310 has a field effect transistor FET1, a capacitor C1, and a resistor R1, and generates an upward ramp waveform voltage that gradually rises in a ramp shape to a voltage Vr obtained by superimposing the voltage Vz on the voltage Vs. .
  • Miller integrating circuit 320 has field effect transistor FET2, capacitor C2, and resistor R2, and gradually decreases in a ramp shape to a predetermined initialization voltage Va. Generating a down-ramp waveform voltage.
  • the input terminals of Miller integrating circuit 310 and Miller integrating circuit 320 are shown as terminal IN1 and terminal IN2, respectively.
  • the force S adopting a Miller integrating circuit using a FET that is practical as the initialization waveform generating circuit 300 and has a relatively simple configuration is not limited to this configuration. As long as the circuit can generate the rising ramp waveform voltage and the falling ramp waveform voltage, any circuit may be used.
  • Scan pulse generation circuit 400 includes switching element S31, switching element S32, and scan IC (integrated circuit) 401, and includes a main energization line (sustain pulse generation circuit 100, initialization waveform generation circuit 300, and scan pulse generation circuit).
  • the scanning electrode is selected by selecting either the voltage applied to the energized line (indicated by a broken line in the drawing in which 400 is connected in common) or the voltage obtained by superimposing the voltage Vscn on the voltage of the main energized line. Apply to. For example, during the writing period, the voltage of the main conduction line is maintained at the negative voltage Va, and the negative voltage Va input to the scan IC 401 and the voltage Vc obtained by superimposing the voltage Vscn on the negative voltage Va are switched and output. By doing so, the above-described negative scanning noise voltage is generated.
  • the scan electrode driving circuit 53 includes an AND gate AG that performs a logical product operation, and a comparator CP that compares the magnitudes of the input signals input to the two input terminals.
  • the comparator CP compares the voltage (Va + Vset2) in which the voltage Vset2 is superimposed on the voltage Va and the voltage of the main conduction line, and outputs “0” if the voltage of the main conduction line is higher. Otherwise, “1” is output.
  • Two input signals, that is, an output signal SL1 (CEL1) of the comparator CP and a switching signal SL2 are input to the AND gate AG.
  • the switching signal CEL2 for example, a timing signal output from the timing generation circuit 55 can be used.
  • the AND gate AG outputs “1” if any of the input signals is “1”, and outputs “0” otherwise.
  • the output of the AND gate AG is input to the scanning noise generation circuit 400.
  • Scan pulse generation circuit 400 outputs the voltage of the main energizing line if the output of AND gate AG is “0”, and outputs the voltage Vscn to the voltage of the main energizing line if the output force S of AND gate AG is “l”. Output the superimposed voltage.
  • FIG. 7 is a circuit diagram of sustain electrode drive circuit 54 in the first exemplary embodiment of the present invention.
  • Sustain electrode driving circuit 54 includes sustain pulse generating circuit 200 for generating sustain pulses, And switching elements Q26 and Q27 for clamping the sustain electrode 23 to the voltage Ve.
  • the maintenance noise generation circuit 200 includes a power recovery unit 210 and a clamp unit 220.
  • the power recovery unit 210 includes a power recovery capacitor C20, switching elements Q21 and Q22, backflow prevention diodes D21 and D22, and resonance inductors L21 and L22.
  • the clamp unit 120 includes switching elements Q23 and Q24.
  • the power collection unit 210 and the clamp unit 220 are connected to the sustain electrode 23. These switching elements can be configured using generally known elements such as MOSFETs or IGBTs.
  • FIG. 8 is a timing chart for explaining an example of the operations of data electrode drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit 54 in the all-cell initialization period in the present embodiment. .
  • the entire cell initialization period is divided into three periods, the first half (first period), the second half (second period), and the abnormal charge erasing part (third period).
  • switching element Q11 of scan electrode drive circuit 53 When switching element Q11 of scan electrode drive circuit 53 is turned on at time tl, a current starts to flow from scan capacitor Q10 for power recovery through switching element Ql l, diode D11 and inductor L11 to scan electrode 22, and the voltage of scan electrode 22 Begins to rise. At time t2, switching element Q13 of scan electrode driving circuit 53 is turned on. Then, since the scan electrode 22 is connected to the power source VS through the switching element Q13, the scan electrode 22 is clamped to the voltage Vs.
  • the control signals SD;! To SDm of the switching elements Q1D;! To QlDm and the switching elements Q2Dl to Q2Dm of the data electrode drive circuit 52 are set to Lo (low level).
  • Switching element Q1D;! To QlDm are turned on, switching elements Q2Dl to Q2Dm are turned off, and the voltage of data electrode 32 is clamped to voltage Vd.
  • Switching element Q1D;! To Q lDm is composed of elements that turn on when the control signal is Lo.
  • the potential of input terminal IN1 of Miller integrating circuit 310 is set to “no, i level”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal IN1. As a result, a constant current flows from the resistor R1 to the capacitor C1, and the source voltage of the transistor FET1 is ramped. Rises and is superimposed on voltage Vs via capacitor 31. The output voltage of the scan electrode drive circuit 53 also starts to rise in a ramp shape. This voltage rise continues until the output voltage rises to Vr. When the output voltage rises to Vr, the output voltage is fixed at Vr while the potential of the input terminal IN1 is “no, i level”. In this way, an up-ramp waveform voltage that gradually rises from voltage Vs to voltage Vr exceeding the discharge start voltage is applied to scan electrode 22.
  • control signals SD;! To SDm of switching element Q1D;! To QlDm and switching elements Q2Dl to Q2Dm of data electrode drive circuit 52 are set to Hi (high level).
  • the switching elements Q1D;! To QlDm are turned off, the switching elements Q2 Dl to Q2Dm are turned on, and the voltage of the data electrode 32 is clamped to the voltage 0 (V).
  • the potential of input terminal IN2 of Miller integrating circuit 320 is set to “no, i level”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal IN2. As a result, a constant current flows from the resistor R2 to the capacitor C2, so that the drain voltage of the transistor FET2 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 53 starts to decrease in a ramp shape. Switching Ql l and Q13 are turned off just before time t8.
  • the comparator CP compares the down-ramp waveform voltage (the voltage of the main energizing line) with the voltage (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va.
  • the output signal SL1 from the CP switches from “0” to “1” at time t9 when the down-ramp waveform voltage becomes equal to or lower than the voltage (Va + Vset2).
  • the switching signal SL2 is “1”
  • both inputs of the AND gate AG are “1”
  • “1” is output from the AND gate AG.
  • the scanning noise generating circuit 400 outputs a voltage Vc in which the voltage Vscn is superimposed on the down-ramp waveform voltage.
  • the minimum voltage in the down-ramp waveform voltage can be (Va + Vset2).
  • switching element Q24 is turned on. Then, since the sustain electrode 23 is grounded through the switching element Q24, the voltage of the sustain electrode 23 is clamped to 0 (V). Further, switching element Q11 of scan electrode driving circuit 53 is turned on at the same timing as switching element Q24 is turned on at time tl2. Then, current starts to flow from the power recovery capacitor C10 to the scan electrode 22 through the switching element Ql1, the diode D11, and the inductor L11, and the voltage of the scan electrode 22 starts to rise.
  • switching element Q 13 of scan electrode drive circuit 53 is turned on. Then, since the scanning electrode 22 is connected to the power source VS through the switching element Q 13, the scanning electrode 22 is clamped to the voltage Vs.
  • switching element Q12 of scan electrode drive circuit 53 is turned on. Then, the current of the scan electrode 22 begins to flow to the capacitor C10 through the inductor L12, the diode D12, and the switching element Q12, and the voltage of the scan electrode 22 begins to decrease.
  • control signal SD;! SDm of switching element Q1D;! QlDm and switching element Q2Dl Q2Dm of data electrode drive circuit 52 is set to Lo.
  • Switching element Q1D;! QlDm is turned on, switching element Q2Dl Q2Dm is turned off, and the voltage of data electrode 32 is clamped to voltage Vd.
  • control signal SD;! SDm of switching element Q1D;! QlDm and switching element Q2Dl Q2Dm of data electrode drive circuit 52 is set to Hi.
  • Switching element Q1D;! QlDm is turned off, switching element Q2Dl Q2Dm is turned on, and data The voltage at the data electrode 32 is clamped at a voltage of 0 (V).
  • the switching signal SL2 of the AND gate AG of the scan electrode driving circuit 53 is set to "1".
  • the voltage S of the main conduction line is compared with the voltage S (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va, and the voltage of the main conduction line is the voltage Va. a + Vset2) or less, the output signal SL1 from the comparator CP is “1”.
  • the scan noise generation circuit 400 outputs the voltage Vc in which the voltage Vscn is superimposed on the voltage of the main energization line, and the voltage of the scan electrode driver 22 becomes Vc.
  • switching element Q14 of scan electrode drive circuit 53 is turned on. Then, the scanning electrode 22 is clamped to a voltage of 0 (V). Just before time t20, switching element Q15 is turned off, switching signal SL2 of AND gate AG is set to “0”, and the potential of input terminal IN2 of Miller integrating circuit 320 is set to “low level”.
  • the data electrode drive circuit has the circuit configuration shown in FIG. 5
  • the scan electrode drive circuit 53 has the circuit configuration shown in FIG. 6,
  • the sustain electrode drive circuit 7 has the circuit configuration shown in FIG. 7, and drives the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 at the timing shown in the timing chart of FIG.
  • the drive waveforms applied to the data Dl to Dm electrode, scan electrode 22 and sustain electrode 23 in the all-cell initialization period of the present embodiment.
  • a positive polarity voltage is applied to the data electrode between the positive polarity pulse voltage applied to the scan electrode and the negative polarity voltage. To do. Accordingly, normal write discharge can be performed in the subsequent write period, and a high-quality image can be displayed.
  • FIG. 9 is a drive waveform diagram applied to each electrode of the panel in the present embodiment, and shows drive waveforms in the all-cell initialization subfield and the selective initialization subfield. Further, FIG. 9 shows a drive waveform including the first SF as an all-cell initializing subfield and the second SF as a selective initializing subfield.
  • the entire cell initialization period is divided into the first half (first period), the second half (second period), and the abnormal charge erasure part (third period) as follows. Since the first half and the second half of the all-cell initialization period are the same as those in the first embodiment, detailed description thereof is omitted. If the discharge delay increases due to insufficient priming or the like, excessive positive wall charges are accumulated on the scan electrodes SCN ;! to SCNn in the first half and second half of the all-cell initialization period.
  • the sustain electrodes SUS;! To SUSn are returned to O (V) again.
  • a positive voltage Vs (V) less than the discharge start voltage is applied to the scan electrode SCN ;! to SCNn for 5 to 203, and then the data electrode D;! To Dm has a time of 1001 3 to 13
  • the first positive voltage Vd (V) of 1001 ⁇ ⁇ 1 3 is applied to the data electrode 131 ⁇ ] 3111 with the second positive voltage ⁇ (1
  • the application time of the first positive voltage Vd (V) applied to the data electrodes D1 to Dm is set to the second positive voltage Vd ( V) should be shorter than the application time.
  • a negative voltage Va (V) is applied to scan electrodes SCN ;! to SCNn for a short time of 5 s or less.
  • Va negative voltage
  • the discharge start voltage of the discharge cells that have performed a stable initialization discharge has dropped! /, N! /
  • the discharge cell has no discharge, and the wall voltage is also in the second half of the initialization period. Keep the state of the part.
  • voltage Vs (V) is applied to scan electrode SCN ;! to SC Nn. Then, since the discharge start voltage is exceeded, a strong discharge is generated, and the wall voltage on the scan electrode SCNi is inverted.
  • the first positive voltage Vd (V) is applied to the data electrodes Dl to Dm in the discharge cell in which the discharge start voltage is greatly reduced.
  • the discharge delay of discharge cells of red, green and blue is greatly different Otherwise, the first positive voltage Vd (V) applied to the data electrodes Dl to Dm causes discharge in the red, green, and blue discharge cells, and the wall charge is adjusted so that the write operation can be performed normally during the write period. can do.
  • the discharge delays of the red, green, and blue discharge cells are significantly different, the discharge cell having a large discharge delay is the first positive voltage Vd (V) applied to the data electrode D;! May not discharge.
  • the application time of the first positive voltage Vd (V) applied to the data electrode D Determined according to the characteristics of the green discharge cell with a small discharge delay.
  • the application time of the first positive voltage Vd (V) is set to a very short value of about 150ns.
  • the necessity of adjusting the first positive voltage Vd (V) applied to the data electrodes Dl to Dm to the characteristics of the green discharge cell having a small discharge delay will be described. If the application time of the first positive voltage Vd (V) is too long, for example, about 400 ns, in the green discharge cell with a small discharge delay, the erasing discharge cannot be terminated halfway, and the wall charge is reduced. It will be erased. Therefore, for the first positive voltage Vd (V) applied to the data electrodes Dl to Dm, the application time is set very short in accordance with the characteristics of the green discharge cell having a small discharge delay.
  • Blue and red discharge cells having a large discharge delay may not discharge at the first positive voltage Vd (V) having a short application time. Therefore, the second positive voltage V d (V) is then applied to the data electrodes Dl to Dm.
  • the application time of the second positive voltage Vd (V) is determined according to the characteristics of the red and blue discharge cells having a large discharge delay. Due to the large discharge delay, the blue and red discharge cells that were not discharged with the first positive voltage Vd (V) with a short application time applied to the data electrodes Dl to Dm are connected to the data electrodes D;! To Dm. Discharge occurs at the applied second positive voltage Vd (V).
  • the application time of the second positive voltage Vd (V) applied to the data electrodes D ;! to Dm is about 400 ns.
  • the green discharge cell with a small discharge delay is discharged at the first positive voltage Vd (V) applied to the data electrodes Dl to Dm, the second discharge voltage applied to the data electrodes D;! No discharge at positive voltage Vd (V).
  • the green cells having a small discharge delay are discharged by the first positive voltage Vd (V) applied to the data electrodes D1 to Dm, and red and blue having a large discharge delay.
  • Discharge cells that did not discharge with the first positive voltage Vd (V) applied to the data electrodes Dl to Dm are the second positive cells applied to the data electrodes D ;! to Dm. Discharge with voltage Vd (V).
  • the discharge cells whose discharge start voltage has dropped are the first positive voltage Vd (V) applied to the data electrode D;! To Dm and the second positive voltage Vd applied to the data electrode D;! To Dm. It discharges at either voltage (V), and does not discharge at the negative voltage Va (V) applied to scan electrodes SCN;! To SCNn. Since the discharge cell whose discharge start voltage has decreased does not discharge with the negative voltage Va (V) applied to the scan electrodes SCN ;! to SCNn, the wall charge is prevented from being erased.
  • the discharge cell in which abnormal wall charges are accumulated is the first applied to the data electrodes Dl to Dm.
  • the discharge sensor that did not discharge with the first positive voltage Vd (V) applied to the data electrode D;! To Dm is the second positive voltage applied to the data electrode D;! To Dm.
  • Discharge occurs at voltage Vd (V) or negative voltage Va (V) applied to scan electrodes SC Nl to SCNn.
  • the discharge cell in which abnormal wall charges are accumulated is the first positive voltage Vd (V) applied to the data electrodes Dl to Dm, the second voltage applied to the data electrodes D;! To Dm.
  • Discharge occurs at any of positive voltage Vd (V) and negative voltage Va (V) applied to scan electrodes SCN1 to SCNn, and the abnormal accumulation of wall charges can be eliminated. .
  • the time during which the positive voltage Vs (V) is applied to the scan electrodes SCN ;! to SC Nn and the negative voltage Va (V) are applied.
  • the first positive voltage Vd (V) and the second positive voltage Vd (V) are applied to the data electrodes Dl to Dm during the period between the first and second data.
  • the power of an example in which the subfield for performing the all-cell initialization operation is one subfield is not limited to this.
  • an all-cell initializing operation may be performed in a plurality of subfields, and one or more all-cell initializing periods out of a plurality of all-cell initializing periods may be provided with an abnormal charge erasing unit. .
  • FIG. 10 shows the entire cell initialization period in the first embodiment.
  • 7 is a timing chart for explaining an example of operations of data electrode drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit 54. Also, the time from tl to t17 is the same as that in the first embodiment, and thus the description thereof is omitted.
  • control signals SD At time tlOO following time t7, control signals SD;! To SDm of switching elements Q1D;! To QlDm and switching elements Q2Dl to Q2Dm of data electrode drive circuit 52 are set to Lo. Switching element Q1D;! To QlDm is turned on, switching elements Q2Dl to Q2Dm are turned off, and the voltage of data electrode 32 is clamped to voltage Vd.
  • control signals SD;! To SDm of switching element Q1D;! To QlDm and switching elements Q2Dl to Q2Dm of data electrode drive circuit 52 are set to Hi.
  • the time from tl8 to time t20 is the same as that of the first embodiment of the present invention, and the description thereof will be omitted.
  • the data electrode drive circuit has the circuit configuration shown in FIG. 5
  • the scan electrode drive circuit 53 has the circuit configuration shown in FIG. 6
  • the sustain electrode drive circuit 7 has the circuit configuration shown in FIG. 7, and drives the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 at the timing shown in the timing chart of FIG.
  • the positive pulse voltage is applied twice to the data electrode between the positive pulse voltage and the negative pulse voltage applied to the scan electrode. .
  • the positive pulse voltage is applied twice to the data electrode between the positive pulse voltage and the negative pulse voltage applied to the scan electrode.
  • FIG. 11 is a driving waveform diagram applied to each electrode of the panel in the present embodiment, and shows driving waveform diagrams of the all-cell initializing subfield and the selective initializing subfield.
  • FIG. 11 shows a drive waveform including the first SF as an all-cell initialization subfield and the second SF as a selective initialization subfield.
  • the drive waveform and the operation of the all-cell initialization subfield will be described. Since the first half and the second half of the all-cell initialization period are the same as those in the first embodiment, detailed description thereof is omitted. If the discharge delay becomes large, such as when priming is insufficient, excessive positive wall charges are accumulated on the scan electrodes SCN ;! to SCNn in the first half and second half of the all-cell initialization period. Further, the writing period and the sustaining period are the same as those in the first embodiment, and thus description thereof is omitted here.
  • the initialization period is divided into two periods, the first half (first period) and the abnormal charge erasing section (second period) as follows.
  • the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.
  • the discharge cell having the decreased discharge start voltage is the data electrode Dl.
  • Discharge occurs when positive voltage Vd (V) is applied to ⁇ Dm.
  • the positive voltage Vd (V) applied to the data electrodes Dl to Dm is applied for a very short time, the erasing discharge is forcibly terminated halfway.
  • the wall charge in the discharge cell is adjusted so that the writing operation can be normally performed in the writing period.
  • the discharge cell discharged with the positive voltage Vd (V) applied to the data electrode D ;! to Dm does not discharge with the negative voltage Va (V) applied to the scan electrode SCN ;! to SCNn! /, .
  • the discharge cell in which abnormal wall charges are accumulated is a positive voltage Vd (V) applied to the data electrodes Dl to Dm or a negative voltage Va (V (V) applied to the scan electrodes SCN;! To SCNn. ).
  • Vd positive voltage
  • V (V) negative voltage
  • the discharge becomes a force that causes the erase discharge to be terminated in the middle.
  • the state where is accumulated is canceled.
  • the wall charges inside the discharge cell are erased.
  • the probability of discharge with positive voltage Vd (V) applied to data electrodes Dl to Dm increases as the amount of accumulated wall charges increases and the discharge delay decreases. Get higher.
  • the write period and the sustain period are the same as the write period and the sustain period of the all-cell initialization subfield, and thus description thereof is omitted.
  • the power indicating the example in which the subfield for performing the selective initialization operation is two subfields is not limited to this.
  • the selective initialization operation may be performed in a plurality of subfields, and the abnormal charge erasing unit may be provided in one or more selective initialization periods among the plurality of selective initialization periods.
  • FIG. 12 is a timing for explaining an example of the operations of the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 in the selective initialization period according to the third embodiment of the invention. It is a chart. Since time t8 to t20 is the same as that of the first embodiment of the present invention, detailed description is omitted.
  • the data electrode drive circuit 52 and the scan electrode drive circuit 53 from time t8 to time t20 in the drive timing chart of the all-cell initialization period shown in FIG. 8 in the first embodiment of the present invention.
  • the operation in sustain electrode drive circuit 54 is the same as that in data electrode drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit 54 in the selection initialization period in the present embodiment.
  • the data electrode driving circuit has the circuit configuration shown in FIG. 5
  • the scan electrode driving circuit 53 has the circuit configuration shown in FIG. 6,
  • the sustain electrode driving circuit 7 has the circuit configuration shown in FIG. 7, and drives the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 at the timing shown in the timing chart of FIG.
  • the drive waveforms applied to the data Dl to Dm electrode, the scanning electrode 22 and the sustain electrode 23 in the selective initialization period of the present embodiment.
  • a positive pulse voltage is applied to the data electrode between the positive pulse voltage and the negative pulse voltage applied to the scan electrode. Accordingly, normal write discharge can be performed in the subsequent write period, and a high-quality image can be displayed.
  • FIG. 6 shows the marks on the electrodes of the panel according to the third embodiment of the present invention.
  • FIG. 5 is a drive waveform diagram to be applied, and shows drive waveforms of an all-cell initialization subfield and a selective initialization subfield.
  • FIG. 6 shows an example of a drive waveform diagram in which the first SF is used as an all-cell initializing subfield and the second SF is used as a selective initializing subfield.
  • the first half and the second half of the all-cell initialization period are the same as those in the first embodiment, and thus detailed description thereof is omitted. If the discharge delay becomes large due to insufficient priming, etc., excessive positive wall charges are accumulated on the scan electrodes SCN ;! to SCNn in the first half and second half of the all-cell initialization period. Further, the writing period and the sustain period are the same as those in the first embodiment, and thus description thereof is omitted.
  • the selection initialization period is divided into two periods, the first half (first period) and the abnormal charge erasing part (second period) as follows.
  • sustain electrodes SUS;! To SUSn are held at Vel (V)
  • data electrodes D;! To Dm are held at O (V)
  • scan electrodes SCN;! To SCNn Apply a downward ramp waveform voltage that gradually falls from Vq (V) to Va (V). Then, in a discharge cell that has undergone a sustain discharge in the sustain period of the previous subfield, a weak initializing discharge occurs, the wall voltage on scan electrode SCNi and sustain electrode SUSi is weakened, and the wall voltage on data electrode Dk Is also adjusted to a value suitable for the write operation.
  • the initializing operation in the selective initializing subfield is a selective initializing operation in which the initializing discharge is performed in the discharge cells in which the sustain discharge is performed in the previous subfield.
  • the time is shorter than the application time of the second positive voltage Vd (V) to be applied. Thereafter, a negative voltage Va (V) is applied to scan electrodes SCN1 to SCNn for a short time of 5 seconds or less.
  • Va negative voltage
  • the discharge start voltage of the discharge cells that have performed a stable initializing discharge has dropped! /, NA! /, No discharge has occurred in the discharge cells, and the wall voltage has also been in the initializing period. Hold the state of the second half.
  • the voltage Vs (V) is applied to the scan electrode SCN ;! to SCNn.
  • the first positive voltage Vd (V) is applied to the data electrodes Dl to Dm in the discharge cells in which the discharge start voltage is greatly reduced. If the discharge delays of the red, green, and blue discharge cells are not significantly different, the red, green, and blue discharge cells are applied with the first positive voltage Vd (V) applied to the data electrode D; It is possible to adjust the wall charge so that a discharge occurs and the writing operation can be performed normally during the writing period. However, when the discharge delays of the red, green, and blue colors of the discharge cells are significantly different, the discharge cell having a large discharge delay is the first positive voltage Vd (V) applied to the data electrode D;! May not discharge.
  • the application time of the first positive voltage Vd (V) applied to the data electrode D;! Decide according to the characteristics of the V and green discharge cells with small discharge delay.
  • the application time of the first positive voltage Vd (V) is set to a very short value of about 150ns. Blue and red discharge cells with large discharge delays may not discharge at the first positive voltage Vd (V) with a short application time. Then, the second positive voltage Vd (V) is applied to the data electrodes D ;! to Dm. The application time of the second positive voltage Vd (V) is determined in accordance with the characteristics of the red and blue discharge cells having a large discharge delay.
  • the blue and red discharge cells that did not discharge with the first positive voltage Vd (V) applied to the data electrodes Dl to Dm with a short application time are connected to the data electrodes D;! To Dm. Discharge occurs at the applied second positive voltage Vd (V).
  • the application time of the second positive voltage Vd (V) applied to the data electrodes D1 to Dm is about 400 ns.
  • the green discharge cell with a small discharge delay is the first positive electrode applied to the data electrodes Dl to Dm. Since it is discharged at the voltage Vd (V), it is not discharged at the second positive voltage Vd (V) applied to the data electrode D;! ⁇ Dm. In this way, the green discharge cell with a small discharge delay is discharged with the first positive voltage Vd (V) applied to the data electrodes D;! To Dm, and the red and blue discharges with a large discharge delay.
  • the discharge cells that did not discharge with the first positive voltage Vd (V) applied to the data electrodes D;! To Dm are the second positive voltage Vd (V ) To discharge. By these discharges, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period.
  • the discharge cells whose discharge start voltage has dropped are the first positive voltage Vd (V) applied to the data electrodes Dl to Dm and the second positive voltage Vd (V ) Discharge at either voltage, but not at negative voltage Va (V) applied to scan electrodes SCN ;! to SCNn.
  • the discharge cell having a reduced discharge start voltage is not discharged with the negative voltage Va (V) applied to the scan electrodes SCN ;! to SCNn! /, Thus preventing wall charges from being erased! /.
  • the discharge cell in which abnormal wall charges are accumulated is the first applied to the data electrodes Dl to Dm.
  • the discharge sensor that did not discharge at the first positive voltage Vd (V) applied to the data electrode D;! To Dm is the second positive voltage applied to the data electrode D;! To Dm.
  • Discharge occurs at voltage Vd (V) or negative voltage Va (V) applied to scan electrodes SC Nl to SCNn.
  • the discharge cell in which abnormal wall charges are accumulated is the first positive voltage Vd (V) applied to the data electrode D;! To Dm, and the first voltage applied to the data electrode D;! To Dm.
  • 2 positive voltage Vd (V) and scan electrode SCN1 Discharge occurs at any of negative voltages Va (V) applied to ⁇ SCNn, and the abnormal accumulation of wall charges can be resolved.
  • the write period and the sustain period are the same as the write period and the sustain period of the all-cell initialization subfield, and thus description thereof is omitted.
  • the power indicating an example in which the subfield for performing the selective initialization operation is two subfields.
  • the present invention is not limited to this.
  • the selective initialization operation may be performed in a plurality of subfields, and the abnormal charge erasing unit may be provided in one or more selective initialization periods among the plurality of selective initialization periods.
  • the abnormal charge erasing unit in the initialization period is improved by adjusting the wall charge of the discharge cell in which the discharge start voltage is greatly reduced. It is possible to display an image with quality.
  • FIG. 14 is a timing chart for explaining an example of operations of the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 in the selective initialization period according to the fourth embodiment of the present invention. It is. Further, since time t8 to t20 is the same as that of the second embodiment, detailed description is omitted. That is, in the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 from time t8 to time t20 in the drive timing chart of the all-cell initialization period shown in FIG. 10 in the second embodiment. Operation The operation is the same as in the data electrode drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit 54 in the selective initialization period in the present embodiment.
  • the data electrode drive circuit has the circuit configuration shown in FIG. 5
  • the scan electrode drive circuit 53 has the circuit configuration shown in FIG. 6
  • the sustain electrode drive circuit 7 has the circuit configuration shown in FIG. 7, and drives the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 at the timing shown in the timing chart of FIG.
  • the present invention makes it possible to display an image with good quality by preventing the wall charge from being erased by the abnormal wall charge erasing unit in the initialization period for the discharge cell having a greatly reduced discharge start voltage. It is useful as an image display device using a plasma display panel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

Un circuit de commande d'électrodes à balayage applique une tension à forme d'ondes ascendante sur des électrodes à balayage (SCN1 à SCNn) au cours d'un premier segment d'une période d'initialisation, pour générer de ce fait une première décharge d'initialisation ; il applique une tension à forme d'ondes descendante sur les électrodes à balayage (SCN1 à SCNn) au cours d'un deuxième segment consécutif au premier segment de la période d'initialisation, pour générer de ce fait une deuxième décharge d'initialisation ; et il applique une tension à forme d'ondes rectangulaire (Vs) d'une polarité positive, et une tension à forme d'ondes rectangulaire (Va) d'une polarité négative sur les électrodes à balayage (SCN1 à SCNn) au cours d'un troisième segment consécutif au deuxième segment de la période d'initialisation. Un circuit de commande d'électrode de données applique une tension à forme d'ondes rectangulaire (Vd) d'une polarité positive sur des électrodes de données (D1 à Dm), au cours de la période de temps qui suit le moment où la tension à forme d'ondes rectangulaire (Vs) de la polarité positive a été appliquée sur les électrodes à balayage (SCN1 à SCNn) au cours du troisième segment, et qui précède le moment où la tension à forme d'ondes rectangulaire (Va) de la polarité négative est appliquée sur les électrodes à balayage (SCN1 à SCNn).
PCT/JP2007/073590 2006-12-08 2007-12-06 Dispositif d'affichage au plasma, et son procédé de commande WO2008069271A1 (fr)

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EP07850199A EP2063409A4 (fr) 2006-12-08 2007-12-06 Dispositif d'affichage au plasma, et son procédé de commande
US12/513,692 US8294636B2 (en) 2006-12-08 2007-12-06 Plasma display device and method of driving the same
JP2008548329A JP4890563B2 (ja) 2006-12-08 2007-12-06 プラズマディスプレイ装置およびその駆動方法
CN2007800453777A CN101563718B (zh) 2006-12-08 2007-12-06 等离子体显示装置及其驱动方法

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JP2010254778A (ja) * 2009-04-23 2010-11-11 National Institute For Materials Science 導電性ポリロタキサン

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KR20090081425A (ko) 2009-07-28
US8294636B2 (en) 2012-10-23
EP2063409A1 (fr) 2009-05-27
TW200834514A (en) 2008-08-16
CN101563718B (zh) 2011-05-25
US20100066727A1 (en) 2010-03-18
KR101002458B1 (ko) 2010-12-17
JP4890563B2 (ja) 2012-03-07
CN101563718A (zh) 2009-10-21
JPWO2008069271A1 (ja) 2010-03-25

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