WO2008067098A3 - Applications de tranches polycristallines - Google Patents

Applications de tranches polycristallines Download PDF

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Publication number
WO2008067098A3
WO2008067098A3 PCT/US2007/082904 US2007082904W WO2008067098A3 WO 2008067098 A3 WO2008067098 A3 WO 2008067098A3 US 2007082904 W US2007082904 W US 2007082904W WO 2008067098 A3 WO2008067098 A3 WO 2008067098A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
applications
polycrystalline wafers
polycrystalline
wafers
Prior art date
Application number
PCT/US2007/082904
Other languages
English (en)
Other versions
WO2008067098A2 (fr
Inventor
Michael Goldstein
Irwin Yablok
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN2007800438160A priority Critical patent/CN102067311A/zh
Priority to DE112007002906T priority patent/DE112007002906T5/de
Priority to KR1020097010724A priority patent/KR101225822B1/ko
Publication of WO2008067098A2 publication Critical patent/WO2008067098A2/fr
Publication of WO2008067098A3 publication Critical patent/WO2008067098A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Une tranche de silicium polycristallin est utilisée dans des applications diverses, y compris comme tranche de manipulation, tranche d'essai, tranche factice, ou comme substrat de puce collé. L'utilisation de matériaux polycristallins au lieu de matériaux monocristallins peut réduire les coûts.
PCT/US2007/082904 2006-11-27 2007-10-29 Applications de tranches polycristallines WO2008067098A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800438160A CN102067311A (zh) 2006-11-27 2007-10-29 多晶晶片的应用
DE112007002906T DE112007002906T5 (de) 2006-11-27 2007-10-29 Anwendungen polykristalliner Wafer
KR1020097010724A KR101225822B1 (ko) 2006-11-27 2007-10-29 다결정 웨이퍼들의 응용들

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/563,626 US20080122042A1 (en) 2006-11-27 2006-11-27 Applications of polycrystalline wafers
US11/563,626 2006-11-27

Publications (2)

Publication Number Publication Date
WO2008067098A2 WO2008067098A2 (fr) 2008-06-05
WO2008067098A3 true WO2008067098A3 (fr) 2011-06-16

Family

ID=39471659

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/082904 WO2008067098A2 (fr) 2006-11-27 2007-10-29 Applications de tranches polycristallines

Country Status (6)

Country Link
US (1) US20080122042A1 (fr)
KR (1) KR101225822B1 (fr)
CN (1) CN102067311A (fr)
DE (1) DE112007002906T5 (fr)
TW (1) TW200847346A (fr)
WO (1) WO2008067098A2 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101755075A (zh) * 2007-07-20 2010-06-23 Bp北美公司 从籽晶制造浇铸硅的方法和装置
JP5279828B2 (ja) * 2008-07-10 2013-09-04 Ｊｘ日鉱日石金属株式会社 ハイブリッドシリコンウエハ及びその製造方法
WO2011055672A1 (fr) * 2009-11-06 2011-05-12 Jx日鉱日石金属株式会社 Tranche de silicium hybride
KR101382918B1 (ko) * 2009-11-06 2014-04-08 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 하이브리드 실리콘 웨이퍼
JPWO2011161975A1 (ja) * 2010-06-25 2013-08-19 Ｄｏｗａエレクトロニクス株式会社 エピタキシャル成長基板及び半導体装置、エピタキシャル成長方法
JP5512426B2 (ja) * 2010-07-08 2014-06-04 Ｊｘ日鉱日石金属株式会社 ハイブリッドシリコンウエハ及びその製造方法
US8252422B2 (en) 2010-07-08 2012-08-28 Jx Nippon Mining & Metals Corporation Hybrid silicon wafer and method of producing the same
US8647747B2 (en) 2010-07-08 2014-02-11 Jx Nippon Mining & Metals Corporation Hybrid silicon wafer and method of producing the same
JP5606189B2 (ja) * 2010-07-08 2014-10-15 Ｊｘ日鉱日石金属株式会社 ハイブリッドシリコンウエハ及びその製造方法
US20230031662A1 (en) * 2021-04-02 2023-02-02 Innoscience (Suzhou) Technology Co., Ltd. Iii nitride semiconductor wafers

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JPH0964051A (ja) * 1995-08-23 1997-03-07 Shin Etsu Handotai Co Ltd シリコンウエーハ及びその製造方法
KR20020026670A (ko) * 2000-10-02 2002-04-12 윤종용 일괄 식각 장치에서 더미 웨이퍼를 사용한 금속배선 형성방법
US6388290B1 (en) * 1998-06-10 2002-05-14 Agere Systems Guardian Corp. Single crystal silicon on polycrystalline silicon integrated circuits
US20060097266A1 (en) * 2002-07-11 2006-05-11 Mitsui Engineering & Shipbuilding Co., Ltd Large-diameter sic wafer and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3968695B2 (ja) * 1999-12-27 2007-08-29 信越半導体株式会社 ウェーハ外周部の加工能力評価方法
US7098047B2 (en) * 2003-11-19 2006-08-29 Intel Corporation Wafer reuse techniques

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JPH0964051A (ja) * 1995-08-23 1997-03-07 Shin Etsu Handotai Co Ltd シリコンウエーハ及びその製造方法
US6388290B1 (en) * 1998-06-10 2002-05-14 Agere Systems Guardian Corp. Single crystal silicon on polycrystalline silicon integrated circuits
KR20020026670A (ko) * 2000-10-02 2002-04-12 윤종용 일괄 식각 장치에서 더미 웨이퍼를 사용한 금속배선 형성방법
US20060097266A1 (en) * 2002-07-11 2006-05-11 Mitsui Engineering & Shipbuilding Co., Ltd Large-diameter sic wafer and manufacturing method thereof

Also Published As

Publication number Publication date
DE112007002906T5 (de) 2009-09-24
TW200847346A (en) 2008-12-01
US20080122042A1 (en) 2008-05-29
WO2008067098A2 (fr) 2008-06-05
KR20090084892A (ko) 2009-08-05
KR101225822B1 (ko) 2013-01-23
CN102067311A (zh) 2011-05-18

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