WO2008058440A1 - Système et procédé de démodulation numérique de signal en modulation de fréquence dans un système numérique de radiocommunications mobiles - Google Patents

Système et procédé de démodulation numérique de signal en modulation de fréquence dans un système numérique de radiocommunications mobiles Download PDF

Info

Publication number
WO2008058440A1
WO2008058440A1 PCT/CN2007/000699 CN2007000699W WO2008058440A1 WO 2008058440 A1 WO2008058440 A1 WO 2008058440A1 CN 2007000699 W CN2007000699 W CN 2007000699W WO 2008058440 A1 WO2008058440 A1 WO 2008058440A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
module
carrier
data
output
Prior art date
Application number
PCT/CN2007/000699
Other languages
English (en)
Chinese (zh)
Inventor
Xiaobo Zhang
Original Assignee
Shenzhen Hyt Science & Technology Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Hyt Science & Technology Co., Ltd. filed Critical Shenzhen Hyt Science & Technology Co., Ltd.
Publication of WO2008058440A1 publication Critical patent/WO2008058440A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
    • H04L27/152—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
    • H04L27/1525—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements using quadrature demodulation

Definitions

  • This invention relates to digital radio intercom technology and, more particularly, to a system and method for digitally demodulating a frequency modulated signal in a digital radio intercom system. Background technique
  • the DMR (Digital Mobile Radio) standard is a new digital trunking standard introduced by the European Telecommunications Standards Institute.
  • the DMR standard is based on digital wireless systems, but it is also explicitly required to be compatible with existing analog wireless systems. Therefore, for the current general FM (modulation) analog modulation and demodulation mode, how to implement it on the DMR-based digital platform will be a technical difficulty that must be overcome by the DMR system productization.
  • FPGA field programmable logic gate array chip
  • the present invention solves the problem of compatible analog FM demodulation in a digital mobile walkie-talkie system, and implements analog FM demodulation based on an FPGA hardware platform.
  • the technical solution adopted by the present invention to solve the technical problem thereof is to provide a system for digitally demodulating a frequency modulated signal in a digital wireless walkie-talkie system, which comprises: sampling and outputting an input analog frequency modulated signal a data sampling module for demodulating data; a carrier removing module for performing carrier removal processing on the to-be-demodulated data to output an IQ two-way de-carrier signal; configured to parse and process the IQ two-way de-carrier signal And a baseband analysis module for restoring the modulated signal; and a low-pass filtering module for performing low-pass filtering processing on the signal output by the baseband analysis module to output a demodulation result signal.
  • the data sampling module of the present invention includes: an analog to digital conversion module for converting an analog FM signal into an n-bit digital signal, and for converting the n-bit continuous type binary data into n-bit complement code Binary data, thereby obtaining a digital conversion module of the data to be demodulated, wherein n is an integer greater than or equal to 8, and less than or equal to 16;
  • the carrier removing module of the present invention includes: a carrier generating module for generating an IQ two-way carrier signal, and an I-way multiplier for multiplying the data to be demodulated and the I-channel carrier signal for use in demodulating a Q-way multiplier for multiplying data by a Q-channel carrier signal, a linear transform module for linearly transforming the output of the I-way multiplier and the Q-way multiplier, and an output for the linear transform module Performing low-pass filtering processing to output a low-pass filter of the IQ two-way carrier signal;
  • the baseband parsing module of the present invention includes: an inverse tangent operation module for performing an inverse tangent operation on the IQ two-way de-carrier signal to obtain a corresponding phase value thereof, and performing differential operation on the phase value To restore the differential operation module of the modulated J signal.
  • a clock module for outputting a system clock signal and a sample enable clock signal to the carrier removal module, the baseband analysis module, and the low pass filter module, and outputting the sample clock signal to the data sampling module is further included.
  • the clock module, the carrier removal module, the baseband analysis module, and the low pass filtering module are implemented by a field programmable logic gate array chip.
  • the present invention also provides a method for digitally demodulating a frequency modulated signal in a digital radio intercom system, including the following steps:
  • a low-pass filter module that performs low-pass filter processing on the signal output by the baseband analysis module to output a demodulation result signal.
  • the step (S1) of the method of the present invention includes: (S11), first converting an analog FM signal into an n-bit digital signal, and similarly, the n is an integer greater than or equal to 8, and less than or equal to 16; And converting the n-bit continuous binary data into n-bit complement binary data to obtain data to be demodulated.
  • an IQ two-way carrier signal having the same carrier frequency as the data to be demodulated is first generated, and then the data to be demodulated is respectively compared with the IQ two-way carrier signal. Multiply, then linearly transform the output of the IQ two-way multiplication, and then linearly transform the output into The line is low-pass filtered to output the IQ two-way de-carrier signal.
  • the IQ two-way de-carrier signal is first subjected to an arctangent operation to obtain a corresponding phase value, and the phase value is further subjected to a differential operation to restore the modulated signal.
  • the steps (S2), (S3), and (S4) can be implemented by a field programmable logic gate array chip, and are subjected to the same system clock signal and sampling enable clock signal. Controlled; the step (S1) is controlled by a sampling clock signal sent by the field programmable logic gate array chip.
  • the present invention realizes compatibility with analog FM demodulation in the digital mobile walkie-talkie system, realizes digital processing of the analog signal, and thus can achieve the purpose of enhancing the anti-interference ability of the signal. More importantly, the present invention implements the FM demodulation function based on the FPGA hardware platform, and completes an important part of the DMR system development.
  • 1 is a flow chart of digitally demodulating a frequency modulated signal in the present invention
  • FIG. 2 is a schematic block diagram of digital demodulation of a frequency modulated signal in the present invention
  • FIG. 3 is a diagram showing the pin design of the clock module shown in Figure 2;
  • Figure 4 is a diagram showing the pin design of the data sampling module shown in Figure 2;
  • FIG. 5 is a schematic block diagram of the carrier removal module shown in Figure 2;
  • FIG. 6 is a pin design diagram of the carrier removal module shown in FIG. 2;
  • Figure 7 is a diagram showing the pin design of the baseband analysis module shown in Figure 2;
  • Figure 8 is a diagram showing the pin design of the low pass filter module shown in Figure 2;
  • FIG. 9 is a diagram showing the connection relationship between modules implemented by an FPGA
  • Figure 10 is a waveform diagram of a modulated signal in one embodiment of the present invention.
  • Figure 11 is a waveform diagram of the reduction signal after being modulated as shown in Figure 10 and demodulated by the system of the present invention. detailed description
  • the demodulation process of the present invention is shown in FIG. 1 , wherein first, the analog input enters data sampling to obtain a signal to be demodulated, and the representative expression is ⁇ os ⁇ 0 ⁇ + jk f m(t)dt , which can The difference is in the form of the product of two trigonometric functions; from the structure of the input signal, it can be seen that in the demodulation process, the carrier signal is first removed (based on ⁇ ); then the arctan (anti-tangent) algorithm is used to filter In addition to the I, Q two useful signals after the carrier to obtain the angle,
  • the modulated signal of the integral format is obtained; then the differential signal is obtained by the differential calculation 3 ⁇ 4" m(t); finally, the modulated signal m(t) of the output is low-pass filtered to obtain the restored signal.
  • FIG. 2 a schematic block diagram of the above algorithm is implemented.
  • the present invention implements the above solution on an FPGA (Field Programming Gate Airay) digital platform.
  • FPGA Field Programming Gate Airay
  • the present invention implements FM demodulation digitization based on clock control.
  • the thin arrow line in Figure 2 represents the clock signal and the thick arrow line represents the processed signal.
  • clock module 201 (1), clock module 201
  • 6144KHZ can be used as the system operating clock, 614. 4KHz as the sampling clock, and 153.6KHz as the intermediate frequency carrier frequency.
  • the sampling clock of 614. 4 Hz can be generated by the enable clock.
  • This part of the circuit is mainly composed of DCM (Digital Clock Manager).
  • AD Analog to Digital
  • 614 4KHz sampling frequency to receive the external input analog signal, and then sent to the internal demodulation, where n is usually an integer greater than or equal to 8, and less than or equal to 16, in this embodiment, take 12, when n is the value For 8, 16, or other values, the corresponding modules in this system should be adapted.
  • the first step into the demodulation circuit is to remove the carrier signal.
  • the STM is first multiplied by the intermediate frequency carrier of I and Q respectively, and then the IF signal is filtered by a low-pass filter to obtain the I and Q baseband signals with useful components. No., where the cutoff frequency of the low pass filter uses the upper limit of voice 4KHz.
  • two baseband signals of I and Q are obtained. Similar to the modes of sin ⁇ and cos ⁇ , the arc angle ⁇ can be obtained by the inverse tangent algorithm. In the actual processing, a is the integral component with m(1), and is differentiated. By operation, the modulated signal m(t) is obtained.
  • the input analog signal is m (t) : sin (200 ⁇ t) + 2sin (600 t), the carrier frequency is 153.6 KHz, and the sampling clock is 4 times the sampling clock frequency to verify the entire design flow.
  • the clock module First, the clock module.
  • the clock module 201 in Figure 2 is the reference for the operation of the entire system, and each subsequent module uses the clock signal to its output.
  • the pin design is shown in Figure 3.
  • the function of each pin is shown in Table 1.
  • the IPcore Intelligent Property Core
  • the IPcore Intellectual Property Core
  • various clock signals such as 6144 KHz and 614. 4 KHz are obtained.
  • the output of the actual circuit is tested with a frequency meter. 614.
  • the frequency value of the 4KHz test signal is 614. 4012KHz.
  • the cause of the error is caused by two aspects: First, there is an error in the 75-leg z signal of the crystal oscillator. The test result is 74.999 legs z, and the second is the DCM frequency conversion. Error; the error of the output result is accurate to three decimal places, which can meet the requirements of the system. Second, the data sampling module
  • the pin design of the data sampling module 202 in Figure 2 is shown in Figure 4. Its function is to convert the analog RF signal into a digital signal through the AD conversion module for input to subsequent modules implemented by the FPGA.
  • the AD conversion module uses a TI model of TI ADS807 (corresponding to the module on the left side in FIG. 4), and converts the analog RF signal received by the wireless receiving circuit into a 12-bit digital quantity
  • the foregoing clock module also provides a sampling clock and other control signals to the AD conversion module.
  • a circuit for processing the analog RF signal such as an input stage, a filter stage, a differential op amp stage, and the like, is not described in detail because it is a mature prior art.
  • the requirement for the analog input is that the DC component is 5V or less, and the peak-to-peak value of the AC component is IV, so that the analog input can be converted into a minimum digital quantity from 12 0 to a maximum of 12, and then Provided to the subsequent processing module.
  • the AD conversion block On the left side of Figure 4 is the AD conversion block, and on the right is the digital conversion module inside the FPGA.
  • the latter function is to convert continuous binary data into complement binary data.
  • the analog signal is input from the 'ad-in' port, converted into a 12-bit digital signal by the AD device in the AD conversion module, and then converted into a 12-bit twos complement format by the internal digital conversion module, thereby completing the simulation.
  • the 'acLdata_in (ll: 0) ' in Figure 4 indicates that this is a data bus with a data width of 12 bits. The highest bit is ad_data_in [11] and the lowest bit is ad_data_in [ 0].
  • the output is the data to be demodulated, that is, the modulated result of the source signal m(t), with carrier information, and the signal format is M.
  • the carrier generation module 501 in order to remove the carrier, the carrier generation module 501 generates two carrier signals, namely sin( ⁇ t) and cos(t); then, the two signals are to be demodulated by the IQ two multipliers 502, 503.
  • the STM is multiplied by the two channels (i.e., I and Q), and the filter (not shown in Figure 5) is used to filter out the high frequency carrier, that is, the corresponding ⁇ ,] and a sin ⁇ are obtained. t] signal.
  • the linear transform module 504 a simple linear arithmetic conversion process is performed on the two signals by the linear transform module 504, and the IQ two-way signal can be obtained.
  • the IQ two way, I means In_phase (the same
  • the linear transformation here is equivalent to two multiplication operations and one positive and negative reversal. This process has no effect on the waveform of the two signals, but only changes the magnitude of the amplitude.
  • the low-pass filter 505 is required to filter out the high-frequency components introduced by the multiplication operation to preserve the low-frequency effective IQ two-way processing output result, and the low-pass filter module 205 shown in FIG. To achieve smooth shaping of the output waveform, its function is not with the low-pass filter 505 of the figure. The same.
  • the pin design of the carrier removal module 204 is as shown in FIG. 6, and the pin identification is as shown in Table 1 below.
  • the corresponding IQ two-way signal can be obtained, that is, ⁇ [ ⁇ (0 ⁇ 1 and ⁇ [(0).
  • Demodulation requires the phase value corresponding to the IQ two-way signal, so ° must pass the above
  • the obtained IQ two-way signal performs the arctangent operation of arctan to obtain the corresponding phase value.
  • the main module for completing the arctangent transformation is the IP core of the CORDIC (cordic-coordinate rotation digital computer), and the input is 25 bits.
  • the precision IQ two-way signal is converted by C0RDIC to obtain a 12-bit precision signed phase output.
  • the essence is to calculate the tangent of the corresponding argument by calculating the input two-way positive/cosine signal sin_ 0 ut/ cos-out. Then, according to the tangent value, by finding the table set in advance, the corresponding phase angle is found, which is equivalent to finding cos[k f m(t)dt].
  • the phase output value is differentiated to obtain m(t).
  • the differential operation is relatively simple, and only the current sample phase value needs to be subtracted from the previous sample phase value. Is the corresponding differential output because
  • phase phase/ ⁇ t (phase2 ⁇ phasel) / (t2— tl)
  • t2- tl is the time unit of a period, which is equal to 1, the above calculation is equivalent to subtracting the previous phase value from the current phase value (the angle).
  • the whole differential operation is the subtraction of the adjacent phase values.
  • the integration in the FPGA is the accumulation of adjacent phase values.
  • the function of the low pass filtering module 205 is to perform digital low pass filtering on the demodulated signal in order to avoid interference of out-of-band Gaussian white noise and also anti-aliasing filtering. The role.
  • the experimental simulation results show that the last digital filtering is indispensable and plays an important role in improving the quality of the demodulated signal.
  • FIR Finite Impulse Response
  • the filter order is designed to be 32 steps.
  • the delay of the filter in the system module is about a dozen system clocks, which is about 0. lms, which has no effect on the signal quality, but only in time than the original signal. There is a slight delay that will have no effect in actual use. Therefore, the delay caused by the filter is not considered in the algorithm, which simplifies the algorithm design. ⁇
  • the pin design of the low-pass filter module 205 is shown in Figure 8.
  • the functions of each pin are shown in Table 5.
  • each module unit may also be a separate circuit or chip, or some or all of the modules may be integrated to form a dedicated chip.
  • the signal-to-noise ratio between the FM signal and the Gaussian white noise is 10 dB, assuming that the input analog signal is m(t) two sin (200 ⁇ t) + 2sin (600 t), the common waveform As shown in Figure 3, when the sampling frequency is 614. 4KHz, the demodulated output is shown in Figure 4. As can be seen from the figure, there is a delay difference between the two waveforms, but it does not affect the call quality. It can be seen that the digital demodulation of the FM signal in the digital radio intercom system in this embodiment has good signal reductivity.
  • the invention is mainly applicable to the field of wireless communication standards of the DMR industry established by the European Telecommunications Standards Association, and is applied to the physical layer modulation and demodulation processing of the DMR communication system, and can be further extended to all FSK (Frequency Shift Keyword) modulation modes.
  • FSK Frequency Shift Keyword

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Système et procédé de démodulation numérique de signal en modulation de fréquence dans un système numérique de radiocommunications mobiles, compatible avec la démodulation analogique en démodulation de fréquence dans un tel système. Le procédé est le suivant: un module d'échantillonnage de données échantillonne l'entrée de signal analogique en modulation de fréquence; un module de suppression de porteuse lance cette suppression pour les données à démoduler; un module d'analyse en bande de base lance l'analyse du signal sans porteuse à deux lignes IQ pour reproduire le signal modulé; un module de filtrage passe-bas lance ce filtrage pour fournir le signal de démodulation résultant. Le module d'horloge, le module de suppression de porteuse, le module d'analyse en bande de base et le module de filtrage passe-bas dans le système sont mis en oeuvre par le biais d'une configuration en matrice FPGA. L'invention permet d'assurer la compatibilité avec la démodulation analogique en modulation de fréquence dans un système numérique de radiocommunications mobiles et le traitement numérique du signal analogique, induisant entre autres un renforcement de la capacité antibrouillage du signal.
PCT/CN2007/000699 2006-11-13 2007-03-05 Système et procédé de démodulation numérique de signal en modulation de fréquence dans un système numérique de radiocommunications mobiles WO2008058440A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2006101568173A CN101184255B (zh) 2006-11-13 2006-11-13 用于数字无线对讲机系统中对调频信号进行数字式解调的系统和方法
CN200610156817.3 2006-11-13

Publications (1)

Publication Number Publication Date
WO2008058440A1 true WO2008058440A1 (fr) 2008-05-22

Family

ID=39401311

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2007/000699 WO2008058440A1 (fr) 2006-11-13 2007-03-05 Système et procédé de démodulation numérique de signal en modulation de fréquence dans un système numérique de radiocommunications mobiles

Country Status (2)

Country Link
CN (1) CN101184255B (fr)
WO (1) WO2008058440A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109451372A (zh) * 2018-12-29 2019-03-08 广州市森锐科技股份有限公司 一种数字对讲机控制系统
CN110061699A (zh) * 2019-05-10 2019-07-26 山东铂晶智能科技有限公司 一种采用fpga控制的数字功放调制器及方法
US10904055B2 (en) 2019-01-18 2021-01-26 Analog Devices International Unlimited Company Digital mobile radio with enhanced transceiver
CN115001592A (zh) * 2022-05-26 2022-09-02 江苏科大亨芯半导体技术有限公司 一种多载频调顶的解调方法及系统
CN115189991A (zh) * 2022-05-20 2022-10-14 南昌大学 一种用于相位调制同步解调的装置及方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102045284B (zh) * 2010-01-21 2013-06-05 清华大学 Fsk解调装置
CN101820295B (zh) * 2010-03-29 2013-07-31 安徽亚际电子技术有限责任公司 一种能和数字通讯系统、模拟通讯系统相互兼容的通讯系统及方法
US8983003B2 (en) 2010-03-31 2015-03-17 Hytera Communications Corp., Ltd. Method and system for adaptively identifying signal bandwidth
US8213577B2 (en) * 2010-08-31 2012-07-03 Fluke Corporation Phone test set modem
CN103067323B (zh) * 2012-12-23 2016-03-30 浙江宏睿通信技术有限公司 一种应用于对讲机的中频解调装置
CN105471789B (zh) * 2014-09-05 2018-10-26 上海华虹集成电路有限责任公司 解调电路
CN104300999A (zh) * 2014-11-03 2015-01-21 陈松初 一种通过手机实现对讲机功能的外部装置及其控制方法
CN117998227B (zh) * 2024-04-02 2024-07-02 杭州海康威视数字技术股份有限公司 一种对讲系统、方法及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0818613A (ja) * 1994-06-30 1996-01-19 Matsushita Electric Ind Co Ltd 変調装置
JPH09153835A (ja) * 1995-11-30 1997-06-10 Matsushita Electric Ind Co Ltd 受信機及び受信信号のサンプリング方法
US5862457A (en) * 1995-12-21 1999-01-19 Lucent Technologies, Inc. Multichannel predistortion linearizer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1163514A (zh) * 1995-10-17 1997-10-29 帕拉德尼有限公司 用于射频接收机的改进的采样系统

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0818613A (ja) * 1994-06-30 1996-01-19 Matsushita Electric Ind Co Ltd 変調装置
JPH09153835A (ja) * 1995-11-30 1997-06-10 Matsushita Electric Ind Co Ltd 受信機及び受信信号のサンプリング方法
US5862457A (en) * 1995-12-21 1999-01-19 Lucent Technologies, Inc. Multichannel predistortion linearizer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109451372A (zh) * 2018-12-29 2019-03-08 广州市森锐科技股份有限公司 一种数字对讲机控制系统
US10904055B2 (en) 2019-01-18 2021-01-26 Analog Devices International Unlimited Company Digital mobile radio with enhanced transceiver
CN110061699A (zh) * 2019-05-10 2019-07-26 山东铂晶智能科技有限公司 一种采用fpga控制的数字功放调制器及方法
CN115189991A (zh) * 2022-05-20 2022-10-14 南昌大学 一种用于相位调制同步解调的装置及方法
CN115189991B (zh) * 2022-05-20 2024-06-11 南昌大学 一种用于相位调制同步解调的装置及方法
CN115001592A (zh) * 2022-05-26 2022-09-02 江苏科大亨芯半导体技术有限公司 一种多载频调顶的解调方法及系统
CN115001592B (zh) * 2022-05-26 2024-01-30 江苏科大亨芯半导体技术有限公司 一种多载频调顶的解调方法及系统

Also Published As

Publication number Publication date
CN101184255A (zh) 2008-05-21
CN101184255B (zh) 2011-05-04

Similar Documents

Publication Publication Date Title
WO2008058440A1 (fr) Système et procédé de démodulation numérique de signal en modulation de fréquence dans un système numérique de radiocommunications mobiles
US5621345A (en) In-phase and quadrature sampling circuit
WO2002067522A1 (fr) Circuit de detection de phase et recepteur
US20140159929A1 (en) Delta-modulation signal processors: linear, nonlinear and mixed
CN103973620A (zh) 一种全数字fm/am信号解调与分析方法
CN1897468A (zh) 射频接收器与射频接收方法
JPH0823231A (ja) Ｆｍ変調回路
JPH0677737A (ja) 位相検波器及びこれに用いる位相検波方式
JP2764635B2 (ja) 復調装置
TWI430629B (zh) 用以補償同相－正交相不匹配之補償裝置、補償模組、補償參數計算模組及其接收器
JPH07162383A (ja) Ｆｍステレオ放送装置
EP1339167A3 (fr) Dispositif convertisseur de signaux de fréquence intermédiaire en signaux de bande de base, et procédé
CN111683028B (zh) 一种数字等报幅cw信号解调方法
Xue et al. A new method of an IF I/Q demodulator for narrowband signals
Zhao et al. A IF Signal Precessing System Design Based on Software Radio Platform
JP2000068839A (ja) シグマデルタ型ａ／ｄ変換器、復調器、受信機及びディスク装置
JPH0870332A (ja) クロック再生装置
JP3454724B2 (ja) 復調回路
EP1217724A1 (fr) Démodulateur en quadrature
Carni et al. $ SigmaDelta $ ADC-Based Frequency-Error Measurement in Single-Carrier Digital Modulations
JP3148319B2 (ja) 変調位相検出装置及び復調装置
JPH08149170A (ja) 変調装置
JPH06216650A (ja) 単側波帯信号の位相信号と包絡線信号を抽出するためのディジタル回路
JP3369383B2 (ja) 変調装置
KR20010059648A (ko) 디지털 중간주파수 수신기

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07720320

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07720320

Country of ref document: EP

Kind code of ref document: A1