WO2008038663A1 - Procédé de fabrication d'une carte à câblage imprimé - Google Patents

Procédé de fabrication d'une carte à câblage imprimé Download PDF

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Publication number
WO2008038663A1
WO2008038663A1 PCT/JP2007/068676 JP2007068676W WO2008038663A1 WO 2008038663 A1 WO2008038663 A1 WO 2008038663A1 JP 2007068676 W JP2007068676 W JP 2007068676W WO 2008038663 A1 WO2008038663 A1 WO 2008038663A1
Authority
WO
WIPO (PCT)
Prior art keywords
catalyst
printed wiring
wiring board
plating
substrate body
Prior art date
Application number
PCT/JP2007/068676
Other languages
English (en)
Japanese (ja)
Inventor
Hajime Sato
Kazuo Obara
Yoshihiro Taguchi
Kunio Mori
Hidetoshi Murakami
Original Assignee
Alps Electric Co., Ltd.
Daisho Denshi Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co., Ltd., Daisho Denshi Co., Ltd. filed Critical Alps Electric Co., Ltd.
Priority to CN2007800353355A priority Critical patent/CN101606445B/zh
Priority to JP2008536392A priority patent/JP4751933B2/ja
Priority to KR1020097008478A priority patent/KR101127547B1/ko
Publication of WO2008038663A1 publication Critical patent/WO2008038663A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/185—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method by making a catalytic pattern by photo-imaging
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor

Definitions

  • the present invention relates to a method for manufacturing a printed wiring board on which various electronic components are mounted.
  • printed wiring boards with through holes are generally manufactured by the following procedure.
  • a copper clad laminate 4 having a copper foil 3 provided on both main surfaces of a substrate portion (substrate body) 2 made of epoxy resin or the like is prepared. Then, as shown in FIG. 7, films 8 are provided on both surfaces of the copper foil 3.
  • pattern films 9 for forming a conductor pattern are provided on both surfaces of the film 8.
  • ultraviolet rays UV
  • Part of this ultraviolet light is blocked by the pattern film 9, and the other part reaches the film 8 through the transmission part 10.
  • the portion of the film 8 where the ultraviolet rays have reached is cured.
  • the pattern film 9 is removed.
  • reference numeral 12 denotes a cured portion that is a cured portion of the film 8.
  • the film 8 other than the cured portion 12 and the copper foil 3 other than the cured portion 12 are removed through a development process and an etching process. Further, as shown in FIG. 11, the hardened portion 12 is peeled off. Then, as shown in FIG. 12, a layer portion 14 made of an epoxy resin is provided on both main surfaces of the substrate portion 2 so as to cover the copper foil 3. Then, as shown in FIG. 13, copper foils 15 are provided on both surfaces of the layer portion 14.
  • the substrate portion 2 and the like are degreased to attach the catalyst.
  • the entire surface is plated with copper to provide a plating layer 18.
  • the clasp layer 18 is also provided on the inner wall of the through hole 17 so that the front and back surfaces are conductive.
  • a pattern layer 20 is provided on the entire front and back surfaces of the substrate portion 2 provided with the plating layer 18. Then, as shown in FIG. 17, a pattern film 21 for forming a conductor pattern is provided on the surface of the pattern layer 20. In the exposure step, ultraviolet rays (UV) are irradiated through the pattern film 21. Then, as shown in FIG. 18, when the pattern film 21 is removed, a cured portion 22 is generated in a part of the pattern layer 20 as described above.
  • UV ultraviolet rays
  • the pattern layer 20 other than the cured portion 22 and the plating layer 18 other than the cured portion 22 are removed. Further, as shown in FIG. 20, the hardened portion 22 is peeled off.
  • the printed wiring board 1 shown in FIG. 20 is obtained. Further, if necessary, the above series of steps is repeated to laminate each layer into several layers.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2003-338690
  • the present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for manufacturing a printed wiring board capable of quickly and easily obtaining a printed wiring board.
  • the present invention has the following aspects, for example.
  • a first aspect is a method for manufacturing a printed wiring board, which includes a degreasing process for degreasing a board body, and a conductive pattern formed on the board body degreased by the degreasing process.
  • a plating process for plating is
  • the substrate body is degreased by the degreasing step, and the ultraviolet light is irradiated to the portion corresponding to the position where the conductor pattern of the substrate body is not formed, and the catalyst attaching step. As a result, the catalyst adheres to the substrate body. Furthermore, the substrate body is plated by a plating process.
  • the second aspect is a method for producing the printed wiring board, preferably the catalyst is a Sn-Pd colloid.
  • the catalyst can be reliably attached to the substrate body, and the nail can be easily provided via the catalyst.
  • the third aspect is a method for manufacturing the printed wiring board, and preferably, the plating force is electroless copper plating or electroless nickel plating.
  • the fourth aspect is a method for producing the printed wiring board, wherein the substrate body is preferably an epoxy substrate, polybutylene terephthalate, polyphenylene sulfide, polysulfone sulfide, polyethylene terephthalate, polyarylate. , Polyimide, polyamide, liquid crystal polymer, glass or ceramics.
  • the number of processes can be drastically reduced by irradiating ultraviolet rays onto the substrate body on which the pattern film is installed, and applying the plating with the force and catalyst attached thereto. Therefore, a printed wiring board can be obtained quickly and easily.
  • FIG. 1 is a diagram showing an embodiment of a method for producing a printed wiring board according to the present invention, and is a side cross-sectional view of a printed wiring board showing a state where a copper layer portion is removed by an etching process It is a figure.
  • Figure 2 shows a pattern film placed in the layered area of Figure 1 and It is a sectional side view of the printed wiring board which shows a mode that an ultraviolet-ray is irradiated.
  • FIG. 3 is a side sectional view of a printed wiring board showing a state where the pattern film of FIG. 2 is removed and plating is performed.
  • FIG. 4 is an explanatory diagram showing a state in which the coating layer disappears due to the irradiation of ultraviolet rays and the plating layer is not formed.
  • FIG. 5 is an explanatory view showing a state in which a plating layer is formed in a layer portion.
  • FIG. 6 is a view showing a conventional method for manufacturing a printed wiring board, and is a side sectional view showing a copper-clad laminate.
  • FIG. 7 is a side sectional view showing a state in which a film is provided on the surface of the copper foil of FIG.
  • FIG. 8 is a side sectional view showing a state in which a pattern film is placed on the surface of the film of FIG. 7, and ultraviolet rays are irradiated through the pattern finer.
  • FIG. 9 is a side sectional view showing a state where the pattern film of FIG. 8 is removed.
  • FIG. 10 is a side sectional view showing a state in which a predetermined portion of film and copper foil are removed from the substrate of FIG. 9 and the like by development and etching.
  • FIG. 11 is a side sectional view showing a state where the hardened portion of FIG. 10 is peeled off.
  • FIG. 12 is a side sectional view showing a state in which a layer portion is provided on the substrate of FIG.
  • FIG. 13 is a side sectional view showing a state in which a copper layer portion is provided on the surface of the layer portion in FIG.
  • FIG. 14 is a side sectional view showing a state in which through holes are formed in the substrate of FIG.
  • FIG. 15 is a side sectional view showing a state in which a plating layer is provided in the through hole of FIG.
  • FIG. 16 is a side sectional view showing a state in which pattern layers are provided on both surfaces of the plating layer in FIG.
  • FIG. 17 is a side sectional view showing a state in which a pattern film is placed on the surface of the pattern layer in FIG. 16, and ultraviolet rays are irradiated through the pattern film.
  • FIG. 18 is a side sectional view showing a state where the pattern film of FIG. 17 is removed!
  • FIG. 19 shows a pattern of a predetermined portion by development and etching on the substrate of FIG. It is a sectional side view which shows a mode that the layer and the plating layer were removed.
  • FIG. 20 is a side sectional view showing a state where the hardened portion in FIG. 19 is peeled off.
  • an etching process is provided as shown in FIG. 1 either before or after the through-hole forming process.
  • the copper foil 15 is removed by etching.
  • the whole is degreased.
  • a coating layer 27 made of an amine such as triethanolamine is provided on the surface of the layer portion 14.
  • the coating layer 27 is provided for attaching the catalyst.
  • the pattern film 26 is installed on the film layers 27 on both surfaces of the layer portion 14.
  • the coating layer 27 is omitted, but actually, the coating layer is provided on both surfaces of the layer portion 14 as shown in FIG.
  • the layer portion 14 is irradiated with ultraviolet rays (UV) through the pattern film 26. At this time, the ultraviolet rays do not reach the through hole 17 and its surroundings by the mask formed by the pattern film 26.
  • UV ultraviolet rays
  • the pattern film 26 is removed, and the entire substrate is immersed in a catalyst such as Sn—Pd colloid. Thereby, a catalyst adheres to a predetermined part. Furthermore, as shown in Fig. 3, electroless copper plating is applied to the entire substrate in the plating process. As a result, the plated layer 29 is formed in the portion not irradiated with the ultraviolet ray, and the printed wiring board 30 in which the conductive pattern is formed on the front and back surfaces is obtained.
  • a catalyst such as Sn—Pd colloid.
  • the action of forming the plating layer 29 in a predetermined portion by irradiating with ultraviolet rays is considered as follows.
  • the catalyst adheres on the coating layer 27, and in the part where the catalyst adheres, the plating layer 29 by electroless copper plating is provided, The catalyst does not adhere to the part where the coating layer 27 is not provided, so the plating Layer 29 is also not formed.
  • FIG. 4 is an explanatory view showing a state in which the coating layer 27 disappears due to ultraviolet irradiation.
  • the coating layer 27 is decomposed into carbon dioxide (C02) and water (H20) and disappears.
  • the catalyst S does not adhere to the surface of the layer portion 14. Therefore, even if electroless copper plating is applied in the plating step, the plating layer 29 is not formed in the portion where the catalyst S without the coating layer 27 does not adhere.
  • FIG. 5 is an explanatory view showing a state in which the plating layer 29 is formed.
  • the ultraviolet rays do not reach the other predetermined portion of the coating layer 27 provided by the degreasing process due to the mask of the pattern film 26. Therefore, the coating layer 27 is left on the layer portion 14.
  • the catalyst S adheres to the surface of the remaining coating layer 27. Accordingly, the electroless copper plating is applied in the plating process, whereby the plating layer 29 is formed on the coating layer 27 via the catalyst S.
  • the mask with the pattern film 26 prevents the ultraviolet rays from reaching the through hole 17 and its periphery, so that the through hole 17 and the surrounding coating layer 27 remain. Thus, the other coating layer 27 is lost. Therefore, in the catalyst adhesion process, the catalyst adheres to the through hole 17 and the surrounding coating layer 27, and the catalyst does not adhere to the other portions. Therefore, as shown in FIG. 3, in the plating process, the adhesion layer 29 is formed in the through hole 17 and its periphery via the catalyst, and is not formed in the other portions.
  • the printed wiring board 30 can be obtained quickly and easily.
  • the catalyst is a Sn—Pd colloid, the catalyst can be reliably attached to the coating layer 27, and the plating layer 29 can be easily provided.
  • the plating is electroless copper plating
  • the plating layer 29 can be reliably provided.
  • the substrate portion 2 in the present embodiment is made of at least one of an epoxy substrate, polybutylene terephthalate, polyphenylene sulfide, polysulfone sulfide, polyethylene terephthalate, polyarylate, polyimide, polyamide, liquid crystal polymer, glass, or ceramics. is there. Thereby, the printed wiring board 1 can be obtained reliably.
  • a printed wiring board can be obtained quickly and easily.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

L'invention concerne un procédé de fabrication de cartes à câblage imprimé grâce auquel les cartes à câblage imprimé peuvent être obtenues rapidement et facilement. Le procédé est doté d'une étape de dégraissage consistant à dégraisser une section de substrat, une étape d'irradiation de la section de substrat, laquelle a été dégraissée dans l'étape de dégraissage, avec un rayonnement ultraviolet sur une surface équivalente à une position où aucun motif conducteur ne doit être formé, une étape de collage d'agent catalyseur consistant à coller un agent catalyseur sur la section de substrat après l'irradiation par rayonnement ultraviolet, ainsi qu'une étape de placage consistant à plaquer la section de substrat sur laquelle l'agent catalyseur a été collé dans l'étape de collage d'agent catalyseur.
PCT/JP2007/068676 2006-09-26 2007-09-26 Procédé de fabrication d'une carte à câblage imprimé WO2008038663A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800353355A CN101606445B (zh) 2006-09-26 2007-09-26 印制线路板的制造方法
JP2008536392A JP4751933B2 (ja) 2006-09-26 2007-09-26 プリント配線板の製造方法、プリント配線板、及びプリント配線板の製造装置
KR1020097008478A KR101127547B1 (ko) 2006-09-26 2007-09-26 프린트 배선판의 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006260800 2006-09-26
JP2006-260800 2006-09-26

Publications (1)

Publication Number Publication Date
WO2008038663A1 true WO2008038663A1 (fr) 2008-04-03

Family

ID=39230099

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/068676 WO2008038663A1 (fr) 2006-09-26 2007-09-26 Procédé de fabrication d'une carte à câblage imprimé

Country Status (4)

Country Link
JP (1) JP4751933B2 (fr)
KR (1) KR101127547B1 (fr)
CN (1) CN101606445B (fr)
WO (1) WO2008038663A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04326719A (ja) * 1991-04-18 1992-11-16 Geo Centers Inc 固体基板に高解像度パターンを形成する方法
JPH07183659A (ja) * 1993-12-22 1995-07-21 Toppan Printing Co Ltd プリント配線板及びその製造方法
JPH08253869A (ja) * 1995-03-14 1996-10-01 Sharp Corp 樹脂の無電解メッキ方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1088361A (ja) * 1996-09-18 1998-04-07 Furukawa Electric Co Ltd:The 高分子成形体への無電解メッキ方法
JP4064801B2 (ja) * 2002-12-12 2008-03-19 新光電気工業株式会社 金属膜形成処理方法、半導体装置及び配線基板
JP3894327B2 (ja) * 2004-02-04 2007-03-22 セイコーエプソン株式会社 配線基板の製造方法及び電子デバイスの製造方法
TW200621850A (en) * 2004-10-07 2006-07-01 Shinetsu Chemical Co Polyimide-based photo-curable resin composition, pattern forming method and substrate protecting film
JP4559936B2 (ja) * 2004-10-21 2010-10-13 アルプス電気株式会社 無電解めっき方法およびこの方法を用いた回路形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04326719A (ja) * 1991-04-18 1992-11-16 Geo Centers Inc 固体基板に高解像度パターンを形成する方法
JPH07183659A (ja) * 1993-12-22 1995-07-21 Toppan Printing Co Ltd プリント配線板及びその製造方法
JPH08253869A (ja) * 1995-03-14 1996-10-01 Sharp Corp 樹脂の無電解メッキ方法

Also Published As

Publication number Publication date
KR20090099049A (ko) 2009-09-21
CN101606445B (zh) 2012-02-22
CN101606445A (zh) 2009-12-16
JP4751933B2 (ja) 2011-08-17
KR101127547B1 (ko) 2012-03-23
JPWO2008038663A1 (ja) 2010-01-28

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