WO2008026573A1 - Substrat d'affichage et procédé de fabrication de substrat d'affichage - Google Patents

Substrat d'affichage et procédé de fabrication de substrat d'affichage Download PDF

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Publication number
WO2008026573A1
WO2008026573A1 PCT/JP2007/066623 JP2007066623W WO2008026573A1 WO 2008026573 A1 WO2008026573 A1 WO 2008026573A1 JP 2007066623 W JP2007066623 W JP 2007066623W WO 2008026573 A1 WO2008026573 A1 WO 2008026573A1
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WIPO (PCT)
Prior art keywords
pixel
display substrate
insulating layer
control element
signal line
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Application number
PCT/JP2007/066623
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English (en)
Japanese (ja)
Inventor
Masaaki Kurita
Takeshi Asano
Original Assignee
Brother Kogyo Kabushiki Kaisha
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Publication date
Application filed by Brother Kogyo Kabushiki Kaisha filed Critical Brother Kogyo Kabushiki Kaisha
Publication of WO2008026573A1 publication Critical patent/WO2008026573A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/42—Arrangements for providing conduction through an insulating substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/129—Chiplets

Definitions

  • the present invention relates to a display substrate and a display substrate manufacturing method, and more particularly to a display substrate and a display substrate manufacturing method that improve productivity and reduce costs while suppressing display unevenness.
  • the active matrix driving method is a method in which a TFT (Thin Film Transistor) as a switching element is provided in each pixel to drive each pixel.
  • a TFT Thin Film Transistor
  • a gate line for supplying an address signal, a data line for supplying a data signal, and a TFT are arranged on the display substrate, and writing of the data signal is permitted to the pixel at the address specified by the address signal.
  • the TFT functions as a switching element that permits writing of the data signal supplied from the data line only at the address specified by the address signal supplied from the gate line.
  • TFTs have been fabricated directly on a substrate by sequentially depositing an insulating film, a semiconductor film, etc. on a glass substrate.
  • TFTs cannot be formed using conventional semiconductor manufacturing processes if the substrate is made of heat-resistant plastic or plastic film. There was a problem.
  • an organic transistor may be used instead of TFT. Since the organic transistor has a low process temperature, it can be formed on a flexible plastic substrate. However, organic transistors have low transistor performance (mobility) and are organic. There was a problem of lack of stability and reliability.
  • FIG. 6 is a plan view showing a conventional display substrate 100. As shown in FIG. 6, for example, by disposing one chip 102 in the center of the pixel electrode 101 in 2 rows and 6 columns and connecting each pixel electrode 101 and the chip 102, 12 chips in one chip 102 are provided. The power S can be controlled. As described above, when the plurality of pixel electrodes 101 are controlled by one chip 102, the number of chips to be arranged as a whole can be reduced. As a result, the labor required for chip placement can be reduced, productivity can be improved, and costs can be reduced.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2004-184978
  • the pixel electrode 101 the data line 104, and the gate line
  • the pixel wiring 108 and the pixel wiring 108 connecting the chip 102 and the pixel electrode 101 are all formed in the same layer, so as shown in FIG. 6, the pixel electrode 101, the data line 104, the gate line 106, The pixel wirings 108 had to be arranged so as not to overlap each other. That is, the pixel wiring 108 must be disposed in an empty space where the pixel electrode 101, the data line 104, and the gate line 106 are not disposed. Therefore, although a large number of pixels can be driven by one chip 102, in practice, the number of pixel wirings 108 that can be arranged in an empty space is actually limited, and a large number can be achieved by one chip 102. This pixel could not be driven. As a result, a large number of chips 102 must be placed on the substrate, and productivity There was a problem that did not improve.
  • the present invention has been made to solve the above problems, and provides a display substrate and a display substrate manufacturing method that improve productivity and reduce costs while suppressing display unevenness.
  • the display substrate according to claim 1 includes a pixel electrode formed for each pixel constituting an image displayed on the display, and a pixel connected to each of the pixel electrodes.
  • Wiring, a pixel control element that controls a plurality of pixel electrodes via a plurality of pixel wirings, and a signal line that supplies a signal for controlling each pixel electrode to the pixel control element are disposed on the substrate body.
  • a first insulating layer laminated on the pixel wiring is provided, and the pixel electrode is formed on the first insulating layer.
  • the display substrate according to claim 2 wherein the display substrate according to claim 1 includes a second insulating layer stacked on the signal line, and the pixel wiring is disposed on the second insulating layer. It is characterized by being.
  • the display substrate according to claim 3 is the display substrate according to claim 2, wherein the substrate body has flexibility.
  • the display substrate according to claim 4 is the display substrate according to any one of claims 1 to 3, wherein an insulating spacer layer is provided on the substrate body, and the spacer layer includes: A recess for arranging the pixel control element is provided.
  • the display substrate according to claim 5 is the display substrate according to claim 4, wherein the signal line is disposed on the spacer layer, and the pixel control element includes the signal line and the signal line.
  • the contact terminals of the pixel control element are disposed in the recess with the surface provided with the connection terminals facing upward.
  • a wire having a conductive pattern is connected to the wire.
  • the display substrate according to claim 6 is the display substrate according to claim 5, wherein the connection terminal of the pixel control element and the signal line on the spacer layer have a height from the substrate body. It is almost equal! /
  • a method for manufacturing a display substrate includes: a pixel electrode formed for each pixel constituting an image displayed on the display; a pixel wiring connected to each of the pixel electrodes; A display substrate in which a pixel control element that controls a plurality of pixel electrodes via a pixel wiring and a signal line that supplies a signal for controlling each pixel electrode to the pixel control element is disposed on the substrate body.
  • a method for manufacturing comprising: a first disposing step of disposing a signal line, a pixel control element, and a pixel wiring on the substrate body; a first insulating layer covering the disposed pixel wiring; And a second arrangement step of disposing a pixel electrode formed on the insulating layer.
  • the signal line, the pixel control element, and the pixel wiring are disposed on the substrate body” means that the signal line, the pixel control element, and the pixel wiring are directly disposed on the upper surface of the substrate body.
  • the signal line, the pixel control element, and the pixel wiring are formed on the substrate body via an insulating layer formed on the upper surface of the substrate body.
  • the display substrate manufacturing method according to claim 8 is the display substrate manufacturing method according to claim 7, wherein the first disposing step disposes a signal line on the substrate body.
  • the display substrate manufacturing method is the display substrate manufacturing method according to claim 8, wherein the first disposing step includes a recess having a recess for disposing the pixel control element.
  • the installation process is on the spacer layer.
  • a signal line is provided.
  • the display substrate of claim 1 since the first insulating layer is laminated on the pixel wiring and the pixel electrode is formed on the first insulating layer, regardless of the arrangement of the pixel electrode. In the lower layer of the first insulating layer, the pixel wiring can be freely wired. Therefore, since a large number of pixel wirings can be arranged for one pixel control element, the number of pixel electrodes that can be controlled by one pixel control element increases. As a result, it is possible to reduce the number of pixel control elements used, improve productivity, and reduce costs. In addition, since it is not necessary to provide a space for pixel wiring between the pixel electrodes, the gap between the pixel electrodes can be reduced, and display unevenness can be suppressed.
  • pixel means a minimum unit for displaying an image.
  • one pixel is divided into, for example, the three primary colors of red (R), green (G), and blue (B), and the smallest divided unit may be referred to as a “sub-pixel”.
  • R red
  • G green
  • B blue
  • Each “sub-pixel” corresponds to the “pixel” in the claims and the specification.
  • the second insulating layer is laminated on the signal line, and the pixel wiring is arranged on the second insulating layer. Therefore, the pixel wiring can be freely arranged in the upper layer of the second insulating layer regardless of the arrangement of the signal lines. Therefore, since more pixel wirings can be connected to one pixel control element, the number of pixel control elements used can be further reduced, productivity can be improved, and cost can be reduced. effective.
  • the substrate body has flexibility, so in the flexible display substrate.
  • an insulating spacer layer is provided on the substrate body, and the spacer is provided.
  • the sub-layer has a recess for arranging the pixel control element.
  • connection terminal of the pixel control element disposed in the recess of the spacer layer and the signal line are connected by a film having a conductive pattern, so that even if there is a gap between the connection terminal of the pixel control element and the signal line, a film having a conductive pattern is passed over the gap, Contact points between the signal lines and the pixel control electrodes can be easily taken, and the productivity can be improved and the cost can be reduced.
  • connection terminal of the pixel control element and the signal line on the spacer layer are separated from the substrate body. Since the heights of the two are almost equal, it is easy to place a film having a conductive pattern between the connection terminals of the pixel control element and the signal line on the spacer layer, which improves productivity and reduces cost. There is an effect that can be made.
  • the signal line, the pixel control element, and the pixel wiring are disposed on the substrate body by the first disposing step, and the second disposing step, A first insulating layer covering the pixel wiring and a pixel electrode formed on the first insulating layer are disposed. That is, since the first insulating layer is interposed between the pixel electrode and the pixel wiring, the pixel wiring can be freely wired in the lower layer of the first insulating layer regardless of the arrangement of the pixel electrode. Therefore, since a large number of pixel wirings can be provided, the number of pixel electrodes that can be controlled by one pixel control element increases.
  • the number of used pixel control elements is reduced, and the productivity is improved and the cost is reduced.
  • the gap between the pixel electrodes can be reduced, and a display substrate with reduced display unevenness can be manufactured.
  • the method for manufacturing a display substrate according to claim 8 in addition to the effect exerted by the method for manufacturing a display substrate according to claim 7, on the signal line connected to the pixel control element by the pixel wiring arrangement step. Since the second insulating layer covering the pixel and the pixel wiring formed on the second insulating layer are arranged, the pixel wiring can be freely arranged in the upper layer of the second insulating layer regardless of the arrangement of the signal lines. Therefore, since a larger number of pixel wirings can be arranged, the number of pixel control elements used can be further reduced, and the productivity can be improved and the cost can be reduced.
  • FIG. 1 (a) is a schematic plan view of a display substrate according to an embodiment of the present invention, and (b) is a diagram showing electrodes disposed on the display substrate 10.
  • FIG. 2 is a schematic plan view of the chip and an enlarged view of one of the switch elements formed on the chip.
  • FIG. 3 (a) is a plan view showing a display substrate for one block, and (b) is an Illb-Ilb sectional view of the display substrate shown in (a).
  • FIG. 4 is a diagram for explaining a manufacturing process of a display substrate.
  • A shows a state in which a spacer layer, a gate line, a data line, and a chip are arranged on the substrate body.
  • B is a view showing a state in which a lower insulating layer and a pixel wiring are disposed thereon, and
  • c is an upper insulating layer and a pixel on the upper insulating layer. It is a figure which shows the state in which the electrode was formed.
  • FIG. 5 (a) is a top view of the spacer layer provided on the substrate body, (b) is a view showing the chip disposed in the recess, and (c) is the position. It is a figure which shows the position of the chip
  • FIG. 6 is a plan view showing a conventional display substrate.
  • FIG. 1A is a schematic plan view of a display substrate 10 according to an embodiment of the present invention
  • FIG. 1B is a diagram showing electrodes disposed on the display substrate 10.
  • the display substrate 10 of the present embodiment includes a goat line 12, a data line 14, a chip 16, and a pixel wiring 18 (FIG. 1). (see (b)) and a pixel electrode 20 are disposed.
  • the longitudinal direction of the gate line 12 is referred to as “row”, and the longitudinal direction of the data line 14 is referred to as “column”.
  • FIG. 1 (a) a display substrate 10 in a range including pixel electrodes 20 for 10 rows and 10 columns is shown.
  • one chip 16 is provided in each of the lower layers in the approximate center of the 5 ⁇ 5 (25) pixel electrodes 20.
  • a set of pixel electrodes 20 connected to one chip 16 (in this embodiment, 5 ⁇ 5 pixel electrodes 20) is referred to as one block of pixel electrodes 20.
  • FIG. 1 (b) in order to make the drawing easy to see, only the pixel electrode 20 for one block is shown by an imaginary line. Also, the pixel wiring 18 is connected between one chip 16 and the pixel electrodes 20 for five rows and five columns. In FIG. 1 (b), the drawing is easy to see. For this reason, only the pixel wiring 18 connected to the pixel electrode 20 for one block is shown.
  • the gate line 12 is a line arranged in the horizontal direction of the display substrate 10, and is a row (address). ) Is a line for supplying an address signal for selecting to the chip 16.
  • the data line 14 is a line arranged perpendicular to the gate line 12 and is a line for supplying a data signal written to the pixel electrode 20 to the chip 16. Since the chip 16 of this embodiment controls the pixel electrodes 20 for 5 rows and 5 columns, the gate lines 12 for 5 rows and the data lines 14 for 5 columns are connected to one chip 16.
  • a gate driver that supplies an address signal to the gate line 12 and a data driver that supplies a data signal to the data line 14 may be provided in the display substrate 10, but this is a known configuration. The illustration and description are omitted.
  • the chip 16 is a highly integrated circuit for controlling a plurality (5 rows and 5 columns in this embodiment) of pixel electrodes 20.
  • This chip 16 is, for example, a Si chip having a high mobility in which an electronic device is formed on a silicon wafer.
  • the chips 16 are regularly arranged in a matrix form on the display substrate 10! /.
  • the chip 16 has a gate line pad 16 a for making contact with the gate line 12, a data line pad 16 b for making contact with the data line 14, and a pixel wiring 18 on the upper surface thereof.
  • a data electrode 16c (see FIG. 2) for connection to the pixel electrode 20 is formed.
  • FIG. 1B only the gate line pad 16a and the data line pad 16b are shown, and the data electrode 16c is not shown for easy understanding of the drawing.
  • the gate line pad 16a, the data line pad 16b, and the data electrode 16c will be described later with reference to FIG. Note that the force connected between the gate line pad 16a and the gate line 12 and between the data line pad 16b and the data line 14 by a film 27 having a conductive pattern (see FIG. 3). This will be described later with reference to FIG. 3, and illustration and description thereof are omitted in FIG.
  • the pixel wiring 18 is a wiring connected to each of the pixel electrodes 20, and is an electrode that connects the data electrode 16 c (see FIG. 2) of the chip 16 and the pixel electrode 20 controlled by the chip 16. is there.
  • the pixel wiring 18 will be described later with reference to FIG.
  • the pixel electrode 20 is a rectangular electrode formed for each pixel constituting an image displayed on the display, and is arranged in a matrix. Each pixel electrode 20 is electrically connected to the data electrode 16c of the chip 16 via the pixel wiring 18, and the data supplied from the chip 16 is connected. Data signal is written.
  • the display substrate 10 of the present embodiment when an address signal is supplied from the gate line 12 and a data signal is supplied from the data line 14, the pixel electrode 20 in the row selected by the address signal is A data signal supplied from the data line 14 is written, and the pixel electrode 20 generates an electric field.
  • the display substrate 10 is used for constituting a display. That is, a transparent substrate (not shown) is placed opposite to the display substrate 10 and a display material such as liquid crystal or an electrophoretic display element is sandwiched between the display substrate 10 and the transparent substrate to constitute a display. can do.
  • a display signal such as an electrophoretic display element can be driven by writing a data signal to an arbitrary pixel electrode 20 and generating an electric field, so that a desired image is displayed. That's the power S.
  • the display substrate 10 of the present invention is suitably used for a reflective display that displays an arbitrary image by reflecting external light incident from the oppositely disposed transparent substrate side on the display substrate 10. It is done. It is also suitable for self-luminous displays in which display materials such as organic EL (electral mouth luminescence) emit light.
  • display materials such as organic EL (electral mouth luminescence) emit light.
  • FIG. 2 is a schematic plan view of the chip 16 and an enlarged view of one of the switch elements 17 formed on the chip 16.
  • a gate line pad 16a, a data line pad 16b, a data electrode 16c, an in-chip gate electrode 16d, and an in-chip data electrode 16e are disposed on the upper surface of the chip 16.
  • the same number (25 in this embodiment) of data electrodes 16c as the pixel wirings 18 connected to the chip 16 are arranged in a matrix.
  • the intra-chip gate electrode 16d is electrically connected to the gate line 12 (see FIG. 1) via the gate line pad 16a, and supplies an address signal received from the gate line 12 to each switch element 17 described later. Is a line.
  • the in-chip data electrode 16e is a line that conducts to the data line 14 (see FIG. 1) via the data line pad 16b and supplies a data signal received from the data line 14 to each switch element 17 described later.
  • the switch element 17 includes a gate portion G that branches from the in-chip gate electrode 16d, an overhang portion 16f that protrudes from the in-chip data electrode 16e, and a data This is a transistor formed by the data electrode 16c.
  • this switch element 17 Since this switch element 17 has a known configuration, detailed description and illustration thereof are omitted.
  • a data signal flows from the overhanging part 16f to the data electrode 16c. That is, by applying an address signal for each gate line 12 (see FIG. 1) for each row, the switch element 17 for each row is turned on, and the data signal given from the data line 14 is given to the data electrode 16c. . As a result, a data signal can be written to the pixel electrode 20 (see FIG. 1) via the pixel wiring 18 (see FIG. 1) connected to the data electrode 16c. On the other hand, the switch elements 17 in the row not designated by the address signal are turned off, and the once written data signal remains stored.
  • the switch element 17 is provided in the vicinity of each intersection of the in-chip gate electrode 16d and the in-chip data electrode 16e.
  • the switch elements 17 for five rows and five columns, that is, 25 switch elements 17 are provided on the chip 16, so that a maximum of 25 pixel electrodes 20 can be controlled by one chip 16.
  • FIG. 3 (a) is a plan view showing the display substrate 10 for one block (range of pixel electrodes 20 in 5 rows and 5 columns), and Fig. 3 (b) is a display shown in (a).
  • FIG. 6 is a cross-sectional view of the substrate 10 viewed from the Illb—Ilb level. In order to make the drawing easier to understand, FIG. 3A shows a state where the pixel wiring 18 is seen through.
  • the display substrate 10 further includes a substrate body 24, a spacer layer 26, and a film 27 having a conductive pattern.
  • the lower insulating layer 28 and the upper insulating layer 30 are provided.
  • the substrate body 24 is a flexible plate-like member, and examples of the material thereof include synthetic resins such as polyethylene naphthalate, polyethylene terephthalate, polyether sulfone, and polyimide, natural resins, and paper.
  • synthetic resins such as polyethylene naphthalate, polyethylene terephthalate, polyether sulfone, and polyimide, natural resins, and paper.
  • the spacer layer 26 is an insulating layer provided on the substrate body 24, and includes a spacer substrate 26a made of a plastic film and a recess 26b.
  • a gate line 12 and a data line 14 are disposed on the spacer substrate 26a, and a chip 16 is disposed in the recess 26b.
  • the spacer substrate 26a has a substantially uniform height T with the chip 16. For example, if the height (thickness) force m of the chip 16 is set, the height (thickness) of the spacer substrate 26a is set to 100 ⁇ m.
  • Recess 26b is configured to be slightly larger than chip 16. As a result, a gap S is formed between the spacer substrate 26a and the chip 16, and the chip 16 is easily arranged.
  • the film 27 having a conductive pattern is called a flexible printed circuit board (FPC), and has a structure in which a conductive foil is formed on a flexible film-like insulator.
  • the contact between the gate line pad 16a and the gate line 12 or the data line 14 on the upper surface of the chip 16 is made by a finrem 27 having a conductive pattern spanned between the upper surface of the spacer substrate 26a and the upper surface of the chip 16. Therefore, even if there is a gap S, you can easily take these contacts with force S.
  • the lower insulating layer 28 is an insulating layer stacked on the gate line 12, the data line 14, and the chip 16, and has a thickness of, for example, about several inches.
  • the pixel wiring 18 is disposed on the lower insulating layer 28.
  • the lower insulating layer 28 includes a through hole 28a in which a conductor is formed in a through hole, and the data electrode 16c on the upper surface of the chip 16 and the pixel wiring 18 are electrically connected through the through hole 28a.
  • the upper insulating layer 30 is an insulating layer stacked on the pixel wiring 18 and has a thickness of about several meters, for example.
  • a pixel electrode 20 is formed on the upper insulating layer 30.
  • the upper insulating layer 30 includes a through hole 30a in which a conductor is formed in the through hole, and the pixel wiring 18 and the pixel electrode 20 are electrically connected through the through hole 30a.
  • the pixel wiring 18 is preferably wired along the boundary of the pixel electrode 20. In this way, the influence of the capacitance formed between the pixel wiring 18 and the pixel electrode 20 can be reduced, and signal delay is suppressed.
  • the upper insulating layer 30 is stacked on the pixel wiring 18, and the pixel electrode 20 is formed on the upper insulating layer 30.
  • a lower insulating layer 28 is stacked on the gate line 12 and the data line 14, and a pixel wiring 18 is formed on the lower insulating layer 28. Therefore, regardless of the arrangement of the gate line 12, the data line 14, and the pixel electrode 20, the pixel wiring 18 can be freely arranged between the lower insulating layer 28 and the upper insulating layer 30. Therefore, since a large number of pixel wirings 18 can be disposed, the number of pixel electrodes 20 that can be controlled by one chip 16 increases. As a result, the number of chips 16 used can be reduced, productivity can be improved, and cost can be reduced.
  • the gap between the pixel electrodes 20 can be reduced, and display unevenness can be suppressed.
  • the area without the pixel electrode 20 cannot drive a display material such as a liquid crystal or an electrophoretic display element, and is a non-display area. It appears as display unevenness.
  • FIG. 4 is a diagram for explaining the manufacturing process of the display substrate 10.
  • FIG. 4 (a) shows a spacer layer 26, a gate line 12, and a data line 14 (see FIG. 1) on the substrate body 24. ) And a state where the chip 16 is disposed
  • FIG. 4B is a diagram illustrating a state where the lower insulating layer 28 and the pixel wiring 18 are disposed thereon
  • FIG. 4 (c) is a diagram showing a state in which the upper insulating layer 30 and the pixel electrode 20 are formed thereon.
  • the series of steps described with reference to FIGS. 4 (a) to 4 (b) corresponds to the first arrangement step described in the claims, and will be described with reference to FIG. (C).
  • the step of performing corresponds to the second arrangement step described in the claims.
  • the spacer layer 26 is disposed on the substrate body 24.
  • the spacer layer 26 is provided by attaching a spacer substrate 26a having a recess 26b to the substrate body 24 (spacer layer forming step).
  • the gate line 12 and the data line 14 are arranged on the spacer substrate 26a (signal line arranging step), and the chip 16 is arranged in the recess 26b.
  • the chip 16 is disposed in the recess 26b with the surface on which the gate line pad 16a, the data line pad 16b, and the data electrode 16c are provided on the upper side, and is fixed at an appropriate position (chip (pixel Control element) fixing process). This pixel control element fixing step will be described in detail later with reference to FIG.
  • the lower insulating layer 28 and the pixel wiring 18 are disposed thereon (pixel wiring arranging step). Specifically, for example, the following procedure is performed. First, a resin film constituting the lower insulating layer 28 is prepared, and the pixel wiring 18 is previously patterned on one surface thereof. So Then, a through hole is formed in the lower insulating layer 28 with a laser, and the through hole is filled with a conductive paste to form a through hole 28a. Then, with the surface on which the pixel wiring 18 is wired as the upper surface, the gate wiring 12 and the data line 14 are stacked as they are, and electrical contact is made between the through hole 28a and the data electrode 16c with a bar heater or the like.
  • the upper insulating layer 30 and the pixel electrode 20 formed on the upper insulating layer 30 are disposed on the pixel wiring 18.
  • the pixel electrode 20 is patterned in advance on one side of the resin film constituting the upper insulating layer 30, and a through hole 30a is formed by a laser from the upper insulating layer 30 side, and the through hole 30a is electrically conductive.
  • the force described as the lower insulating layer 28 and the pixel wiring 18 are stacked together and the upper insulating layer 30 and the pixel electrode 20 are stacked together. They can be manufactured to be laminated one after another.
  • the photosensitive resin is uniformly applied to the lower insulating layer 28 or the upper insulating layer 30 by a spin coating method using centrifugal force caused by rotation
  • the through hole 28a or the through hole 30a is formed by a photolithography method.
  • the pixel wiring 18 or the pixel electrode 20 may be formed by a known method such as sputtering, etching, or inkjet.
  • FIG. 5 (a) is a top view of the spacer layer 26 provided on the substrate body 24 (see FIG. 4). As shown in FIG. 5 (a), the spacer layer 26 is provided with a plurality of recesses 26b in a matrix. By arranging the chips 16 one by one in the recess 26b, the chips 16 are roughly arranged.
  • FIG. 5 (b) is a diagram showing the chip 16 disposed in the recess 26b.
  • the recess 26b when the recess 26b is configured to be slightly larger than the chip 16, the work of placing the chip 16 in the recess 26b is facilitated.
  • the operation of placing the chip 16 in the recess 26b can be automatically performed by, for example, a chip mounter equipped with a stage on which the substrate is placed and a robot hand for transferring the chip 16 to the substrate.
  • Figure 5 (b) is easy to understand. For this purpose, the force shown by emphasizing the difference in size between the recess 26b and the chip 16 Actually, the recess 26b only needs to be slightly larger than the outer dimensions of the chip 16.
  • the chips 16 are aligned next.
  • the recess 26b is configured to be slightly larger than the chip 16
  • FIG. 5 (c) is a diagram showing the position of the chip 16 after alignment. In this way, since all the chips 16 can be aligned at once using the recess 26b, the chip 16 can be accurately positioned by providing the recess 26b at an accurate position of the spacer layer 26. It can be easily placed at the position.
  • a UV (ultraviolet) curable resin is filled between the inner wall of the recess 26b and the chip 16 and irradiated with UV. Then, the chip 16 is fixed.
  • the gate lines 12 and the data lines 14 arranged on the spacer layer 26a and the gate lines on the chip 16 are arranged.
  • the contact between the pad 16a and the data line pad 16b can be easily taken using a fin 27 having a conductive pattern.
  • the pixel wiring 18 may be arranged in multiple layers.
  • a further insulating layer is formed on the pixel wiring 18 and the pixel wiring 18 is also provided on the insulating layer, and the pixel wiring 18 has a multilayer structure, a larger number of pixel wirings 18 are provided.
  • the number of chips 16 can be further reduced.
  • 25 pixel electrodes 20 are controlled by one chip 16.
  • the number of pixel electrodes 20 controlled by one chip 16 is not limited to this. As the number of pixel electrodes 20 controlled by one chip 16 increases, the number of chips 16 to be used can be reduced, thereby improving productivity and reducing costs.
  • the present invention can also be applied to a case where a substrate body 24 that is not flexible, such as a force S described as the substrate body 24 having flexibility, for example, a glass substrate, is used.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un substrat d'affichage et un procédé de fabrication de substrat d'affichage permettant de supprimer les irrégularités d'affichage, d'améliorer la productivité et de réduire le coût. Selon un substrat d'affichage (10), une couche isolante supérieure (30) est appliquée sur un câblage de pixel (18) et une électrode de pixel (20) est formée sur la couche isolante supérieure (30). De plus, une couche isolante inférieure (28) est appliquée sur une ligne de grille (12) et une ligne de données (14). Un câblage de pixel (18) est formé sur la couche isolante inférieure (28). En conséquence, il est possible d'agencer librement le câblage de pixel (18) entre la couche isolante inférieure (28) et la couche isolante supérieure (30) indépendamment de l'agencement de la ligne de grille (12), de la ligne de données (14) et de l'électrode de pixel (20). Ainsi, il est possible d'agencer un grand nombre de câblages de pixel (18), ce qui à son tour augmente le nombre d'électrodes de pixel (18), qui peut être contrôlé sur une puce (16). En conséquence, le nombre requis de puces (16) est réduit, ce qui améliore la productivité et réduit le coût.
PCT/JP2007/066623 2006-08-30 2007-08-28 Substrat d'affichage et procédé de fabrication de substrat d'affichage WO2008026573A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006233534A JP4737009B2 (ja) 2006-08-30 2006-08-30 ディスプレイ基板およびディスプレイ基板の製造方法
JP2006-233534 2006-08-30

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WO2008026573A1 true WO2008026573A1 (fr) 2008-03-06

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JP (1) JP4737009B2 (fr)
WO (1) WO2008026573A1 (fr)

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WO2010053533A1 (fr) * 2008-11-04 2010-05-14 Global Oled Technology Llc. Dispositif doté de puces et d’interconnexions adaptables
WO2012112173A1 (fr) * 2011-02-16 2012-08-23 Global Oled Technology, Llc Dispositif d'affichage à puce comportant des connecteurs d'électrode

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US8456387B2 (en) * 2009-02-18 2013-06-04 Global Oled Technology Llc Display device with chiplet drivers
US8698391B2 (en) * 2009-04-29 2014-04-15 Global Oled Technology Llc Chiplet display with oriented chiplets and busses
JP2012181445A (ja) 2011-03-02 2012-09-20 Seiko Epson Corp 電気装置
JP5824844B2 (ja) * 2011-04-18 2015-12-02 大日本印刷株式会社 電子ペーパー用背面電極基材および電子ペーパー
US10451943B2 (en) 2015-04-20 2019-10-22 Pi-Crystal Inc. Method for manufacturing active matrix array device, and active matrix array device manufactured thereby

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JPH0764110A (ja) * 1993-08-30 1995-03-10 Kyocera Corp アクティブマトリックス基板
JP2004184978A (ja) * 2002-11-19 2004-07-02 Hideki Matsumura 平面ディスプレイ基板

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JPH0764110A (ja) * 1993-08-30 1995-03-10 Kyocera Corp アクティブマトリックス基板
JP2004184978A (ja) * 2002-11-19 2004-07-02 Hideki Matsumura 平面ディスプレイ基板

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010053533A1 (fr) * 2008-11-04 2010-05-14 Global Oled Technology Llc. Dispositif doté de puces et d’interconnexions adaptables
US7830002B2 (en) 2008-11-04 2010-11-09 Global Oled Technology Llc Device with chiplets and adaptable interconnections
CN102246304A (zh) * 2008-11-04 2011-11-16 全球Oled科技有限责任公司 具有小芯片和可适性互连的器件
CN102246304B (zh) * 2008-11-04 2013-03-27 全球Oled科技有限责任公司 具有小芯片和可适性互连的器件
WO2012112173A1 (fr) * 2011-02-16 2012-08-23 Global Oled Technology, Llc Dispositif d'affichage à puce comportant des connecteurs d'électrode
US8599118B2 (en) 2011-02-16 2013-12-03 Global Oled Technology Llc Chiplet display with electrode connectors

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JP4737009B2 (ja) 2011-07-27

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