WO2008026338A1 - Dispositif d'affichage et son procédé de commande - Google Patents

Dispositif d'affichage et son procédé de commande Download PDF

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Publication number
WO2008026338A1
WO2008026338A1 PCT/JP2007/055812 JP2007055812W WO2008026338A1 WO 2008026338 A1 WO2008026338 A1 WO 2008026338A1 JP 2007055812 W JP2007055812 W JP 2007055812W WO 2008026338 A1 WO2008026338 A1 WO 2008026338A1
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WIPO (PCT)
Prior art keywords
video signal
signal line
signal lines
image
display
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PCT/JP2007/055812
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English (en)
Japanese (ja)
Inventor
Noriyuki Nakane
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Sharp Kabushiki Kaisha
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Publication of WO2008026338A1 publication Critical patent/WO2008026338A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present invention relates to an active matrix display device, and more specifically, a plurality of video signal lines for transmitting a video signal to a plurality of pixel formation portions for forming an image to be displayed.
  • the present invention relates to a display device in which (for example, three) are grouped into a plurality of video signal line groups as one set, and video signals are sequentially output from the drive circuit to the grouped video signal line groups one by one.
  • an active matrix liquid crystal display device includes a display unit including two substrates that sandwich a liquid crystal layer, and one of the two substrates has a video signal line as a video signal line.
  • a plurality of data lines and a plurality of gate lines as scanning signal lines are arranged in a grid pattern, and a plurality of pixels are arranged in a matrix corresponding to the intersections of the plurality of data lines and the gate lines.
  • a forming part is provided.
  • Each pixel formation part constitutes a display part of the device.
  • a TFT Thin Film Transistor which is a switching element in which a gate terminal is connected to a gate line and a source terminal is connected to a data line, and the TFT And a pixel electrode connected to the drain terminal.
  • the substrate including these pixel formation portions is called a TFT substrate.
  • the other substrate facing the TFT substrate of the two substrates has a common electrode which is a common electrode provided in common for the plurality of pixel forming portions and a color for forming a display color.
  • a filter (CF: Color Filter) is provided. This substrate is called a CF substrate.
  • Such an active matrix liquid crystal display device includes a data driver for driving the data line of the display unit, a gate driver for driving the gate line of the display unit, and the common electrode.
  • a common electrode driving circuit for driving the common electrode driving circuit.
  • the resolution depends on the resolution of the image to be displayed.
  • the time for sampling the video signal to be given to each data line becomes shorter.
  • the time (charge time) for applying the video signal to each data line is shortened. As a result, the video signal cannot be sampled accurately and an accurate voltage cannot be applied to the data line.
  • phase expansion driving method phase expansion processing method
  • This phase development process is a high-frequency, high-frequency, image-signal-represented image in order to display an appropriate image per dot or duration per pixel (hereinafter “signal per dot”).
  • signal per dot This is a process that lengthens the “duration” or “signal duration per pixel”) and lowers the frequency of the image signal supplied to the liquid crystal panel.
  • FIG. 17 is a partial configuration diagram of a data driver that is a circuit for driving data lines in a liquid crystal display device in which two-phase expansion is performed.
  • This data driver has six analog video signals AV generated by two-phase expansion for each color of R (red), G (green), and B (blue) in a predetermined phase expansion circuit. Supplied by wire.
  • the shift register 91 sequentially outputs sampling pulses from the respective flip-flop circuits FF1, FF2,.
  • the analog video signal AV sent from the phase expansion circuit is supplied to the liquid crystal panel for every two color pixels, and image display is performed (where one color pixel represents each of the adjacent R, G, and B colors). It shall be displayed by the three pixel forming parts to be displayed).
  • connection pitch the pitch of the connection portion between the output terminal of the drive circuit and the signal line of the display panel
  • two or more video signal lines are grouped into a group of video signal lines. Assign one output terminal of the video signal line drive circuit to the multiple video signal lines that make up each group, and time-division video is displayed on the video signal lines in each group within one horizontal running period in image display.
  • a liquid crystal display device configured to apply a signal has been proposed (see, for example, Japanese Patent Laid-Open No. 6-138851).
  • the charging time for each video signal line depends on the number of video signal lines constituting each set, that is, the number of time divisions by the switching switch. If the number of time divisions is m, the charging time for each video signal line is 1 / m in the case of a normal liquid crystal display device that is not a video signal line time division drive system. However, by forming a switching switch with the time division number of m on the liquid crystal panel substrate, the connection pitch between the output terminal of the video signal line driving circuit and the video signal line is m times that of a normal liquid crystal display device. Can be.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2003-58119
  • Patent Document 2 Japanese Unexamined Patent Publication No. 2005-141169
  • Patent Document 3 Japanese Patent Laid-Open No. 6-138851
  • Patent Document 4 Japanese Unexamined Patent Publication No. 2003-233086
  • the liquid crystal display device that performs the phase expansion process may cause fluctuations in the voltage of the video signal to be written in the pixel formation portion due to the parasitic capacitance between adjacent video signal lines.
  • this phenomenon will be described with reference to FIG.
  • FIG. 17 is a diagram simply showing a partial configuration of a video signal line driving circuit in a conventional liquid crystal display device.
  • the corresponding video signal is applied to the video signal lines SL:! To SL6 by the sampling pulse from the flip-flop circuit FF1.
  • the potential of the video signal line SL:! To SL6 is the desired potential.
  • the voltage value must be written as a pixel value in the corresponding pixel formation portion.
  • the corresponding video signal is applied to the video signal lines SL7 to SL12 (here, the video signal line SL7 in particular) by the sampling pulse from the flip-flop circuit FF2, so that the video signal line
  • the potential of the video signal line SL6 to be held also changes according to the change in the potential of SL7. This is because the video signal lines SL6 and SL7 are capacitively coupled.
  • the parasitic capacitance between the adjacent video signal lines includes a direct capacitance between the signal lines and an indirect capacitance formed through the pixel formation portion.
  • a conventional liquid crystal display configured to assign one output terminal of a video signal line driving circuit to a plurality of video signal lines and apply video signals to the video signal lines in each set in a time-division manner
  • the potential of the other video signal line to be held also changes according to the potential change of the adjacent video signal line due to the parasitic capacitance between the adjacent video signal lines.
  • undesired effects such as a display color shift and the occurrence of a vertical stripe pattern associated therewith occur.
  • a conventional liquid crystal display device having a liquid crystal panel in which the parasitic capacitance between pixel electrodes of adjacent pixel forming portions is set to have different values in each display row is provided.
  • a conventional liquid crystal display device having a liquid crystal panel in which the parasitic capacitance between pixel electrodes of adjacent pixel forming portions is set to have different values in each display row is provided.
  • undesired effects such as display color deviation and blurring are scattered over the entire screen. For this reason, this favorable effect and influence are reduced as a whole.
  • a large number of video signal lines such as the above-described phase expansion drive system are grouped into a plurality of video signal line groups with a plurality (for example, three) as one set, and are gnolled.
  • a display device in which video signals are output from the drive circuit one by one to the video signal line group, and the display luminance (typically display color) shift caused by parasitic capacitance between adjacent video signal lines, and this It is an object of the present invention to provide a display device that can reduce or eliminate deterioration of display quality such as generation of vertical stripes with a simple device configuration.
  • a first aspect of the present invention includes a plurality of pixel forming portions that are arranged in a matrix and form an image to be displayed, and a plurality of video signal lines for transmitting a signal representing the image to be displayed.
  • a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of pixel forming portions correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively.
  • An active matrix display device arranged in a matrix, wherein the scanning signal line driving circuit selectively drives the plurality of scanning signal lines, and two or more video signal lines among the plurality of video signal lines.
  • a display control circuit for supplying an image signal to be supplied to the group to the video signal line driving circuit
  • the display control circuit is configured to detect the plurality of scanning signal lines by the scanning signal line driving circuit. Each time one of them is selectively driven, the order in which the order is reversed is repeated as a new order.
  • a third aspect of the present invention provides, in one aspect of the present invention,
  • the display control circuit is characterized in that for each frame period in which the image is displayed, the order in which the order is reversed is repeated as a new order.
  • a fourth aspect of the present invention provides, in one aspect of the present invention,
  • the display control circuit generates an image signal expanded in a predetermined number of phases from image data input as data representing the image to be displayed, and supplies the generated image signal to the video signal line driving circuit.
  • the video signal output circuit includes:
  • a shift register circuit that sequentially outputs a predetermined sampling pulse in either a predetermined direction or a shift direction opposite to the predetermined direction;
  • a plurality of switch circuits that selectively receive the phase-developed image signal supplied from the display control circuit to the corresponding video signal line by receiving each sampling pulse output from the shift register circuit;
  • the display control circuit controls a shift direction of the shift register so that the image signals are supplied to the plurality of video signal lines in the order.
  • a sixth aspect of the present invention in one aspect of the present invention, is a sixth aspect of the present invention.
  • the video signal line driving circuit includes the plurality of video signal line groups in which two adjacent video signal lines are used as one unit, and two or more units adjacent to each other are set as one set.
  • An image signal input as a signal representing the image to be displayed is applied to each of a plurality of sets of video signal lines obtained by grouping video signal lines in a predetermined order.
  • the video signal line drive circuit uses, as one unit, three adjacent video signal lines respectively connected to three types of pixel forming portions that display predetermined three primary colors among the plurality of video signal line groups.
  • a signal representing the image to be displayed in a predetermined order one by one with respect to a plurality of video signal line groups obtained by gnoleating the plurality of video signal lines with one unit or more as one set.
  • An input image signal is applied.
  • An eighth aspect of the present invention is the seventh aspect of the present invention.
  • the video signal line driving circuit includes a plurality of sets of video signals obtained by gnoleating the plurality of video signal lines by setting two or more units adjacent to each other at a distance of one unit from the plurality of video signal line groups.
  • an image signal input as a signal representing the image to be displayed is applied to the signal line group one by one in a predetermined order.
  • a ninth aspect of the present invention provides, in one aspect of the present invention,
  • the video signal line driving circuit has a plurality of output terminals to which one set of a plurality of video signal line groups obtained by grouping the plurality of video signal lines can be connected,
  • the display control circuit connects the plurality of output terminals to any one of the plurality of sets of video signal line groups and a set of videos connected to the plurality of output terminals. It is characterized in that the signal line group is controlled to be switched according to time division between a plurality of video signal line groups.
  • a tenth aspect of the present invention is the ninth aspect of the present invention.
  • the video signal line driving circuit includes the plurality of video signals so as to include only one type of any of the three types of adjacent video signal lines respectively connected to the three types of pixel forming portions that display predetermined three primary colors. It has a plurality of output terminals that can connect one set out of three video signal line groups obtained by grouping lines.
  • the display control circuit connects the plurality of output terminals to any one of the three sets of video signal line groups and a set of video connected to the plurality of output terminals. Control is performed so that the signal line group is switched between the three sets of video signal line groups according to time division.
  • An eleventh aspect of the present invention is the ninth aspect of the present invention.
  • the video signal line driving circuit has three types of pixel forming portions that display predetermined three primary colors.
  • the plurality of video signal lines are grouped so as to include only one of the three types of adjacent video signal lines connected to each other and the three types of adjacent video signal lines adjacent to the video signal line.
  • the display control circuit connects the plurality of output terminals to any one of the six video signal line groups and one set of video connected to the plurality of output terminals. Control is performed so that the signal line group is switched between the six video signal line groups in accordance with time division.
  • a plurality of pixel forming portions arranged in a matrix and forming an image to be displayed, and a plurality of video signal lines for transmitting a signal representing the image to be displayed
  • a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of pixel forming portions correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively.
  • a scanning signal line driving step for selectively driving the plurality of scanning signal lines, and grouping the plurality of video signal lines by using two or more video signal lines as a set among the plurality of video signal lines.
  • a display control step for controlling to supply an image signal to be supplied to a set of video signal line groups in the video signal line driving step
  • one set is displayed in a predetermined order for a plurality of sets of video signal lines obtained by grouping two or more video signal lines as one set.
  • An image signal input as a signal representing the image to be applied is applied, and a plurality of sets of images in the above order are applied.
  • the image signal is given to the video signal line drive circuit with a new order that is the reverse of the above order.
  • a number of video signal lines such as the phase expansion drive method and the video signal line time-division drive method are grouped into a plurality of video signal line groups, and a group of video signal lines is grouped into a group of video signal lines.
  • the display brightness display color in the case of color
  • the display brightness shifts due to fluctuations, it differs from the conventional configuration by the pixel formation unit connected to one video signal line (specific color in the case of a color image). Since vertical stripes do not occur, display quality deterioration caused by parasitic capacitance between video signal lines in contact with P and the resulting deterioration in display quality such as vertical stripes should be reduced or eliminated with a simple device configuration. Can do.
  • the image signal is converted into a new order by changing the order in which the order is reversed.
  • Display brightness based on potential fluctuations due to parasitic capacitance alternately in each row in two adjacent video signal lines at the boundary between one set and the adjacent set (typically Display color), and vertical stripes that do not concentrate the display brightness on one display column do not occur, so the deterioration of display quality can be reduced or eliminated with a simple device configuration. it can.
  • the image signal is given to the video signal line drive circuit with the reverse order as the new order for each frame period in which the image is displayed.
  • an image signal phase-expanded to a predetermined number of phases is generated from image data input as data representing an image to be displayed, and the video signal line driving circuit is generated. Therefore, this phase expansion process can lower the frequency of the image signal, so that the image represented by the image signal with a higher frequency can be displayed properly, and vertical stripes due to a shift in display luminance occur. Since there is no such thing, display quality can be easily degraded. It can be reduced or eliminated by the configuration.
  • the video signal output circuit includes the shift register circuit capable of reversing the shift direction, and the shift direction of the shift register is controlled by the display control circuit.
  • the order can be reversed, and deterioration of display quality can be reduced or eliminated with a simple device configuration.
  • the sixth aspect of the present invention when two adjacent video signal lines are used as one unit, a plurality of units obtained by grouping two or more units adjacent to each other with one unit apart are grouped. Since video signals are applied to each set of video signal lines in a predetermined order and then in the reverse order, the two video signal lines that constitute one unit are both based on potential fluctuations due to parasitic capacitance. A display brightness shift occurs, resulting in a display brightness shift across the entire screen, so that the display brightness shift can be felt and display quality such as the occurrence of vertical stripes due to the display brightness shift. Can be reduced or eliminated with a simple device configuration.
  • the parasitic capacitance between the video signal lines is almost the same.
  • the display brightness deviations are all the same, so the display brightness (typically display color) deviation is completely eliminated (specifically, the screen only becomes brighter or darker). is there).
  • the display quality of the display device is improved.
  • the seventh aspect of the present invention since three adjacent video signal lines respectively connected to the three types of pixel forming portions for displaying the predetermined three primary colors are set as one unit, the display luminance is reduced. Since the shift does not cause vertical stripes as a display color shift, the deterioration of display quality can be reduced or eliminated with a simple device configuration.
  • two or more adjacent units separated by one unit are grouped as one set.
  • adjacent video signal lines The display color shift caused by the parasitic capacitance between the lines occurs every other line, and the display color shifts.
  • the color pixels are not adjacent to each other in the display row or display column direction. Therefore, display quality deterioration such as display color shift and the occurrence of vertical stripes can be reduced or eliminated with a simple device configuration.
  • the checker pattern has odd and even lines. If the two consecutive frames are observed together, the checker pattern disappears and the display color shifts uniformly. Therefore, it becomes difficult to perceive this shift, and the occurrence of the vertical stripes can be completely suppressed.
  • the display control circuit connects the plurality of output terminals to any one of the four video signal line groups, and the plurality of video signal line groups. Since a set of video signal lines connected to the output terminal of the video signal line is controlled to be switched according to time division, for example, the same potential is applied to each video signal line from the video signal line driving circuit. If the parasitic capacitances between the video signal lines are almost the same, the display brightness shift is less likely to be felt if the adjacent display lines are observed together when the above order is reversed for each display line.
  • the occurrence of vertical stripes due to this shift can be eliminated, and for example, when the above order is reversed for each display frame, if two consecutive frames are observed together, a shift in display luminance can not be felt at all. This again The occurrence of vertical stripes due also can be completely eliminated.
  • the tenth aspect of the present invention only one of the three types of adjacent video signal lines respectively connected to the three types of pixel forming portions that display the predetermined three primary colors is included. Since the plurality of video signal lines are made into a gnole, for example, when all the RGB have the same luminance, the display color shift is hardly felt or not felt at all as in the ninth aspect of the present invention. Generation of vertical stripes due to this shift can be eliminated. Even when a natural image is displayed, it is possible to feel the display color shift.
  • the eleventh aspect of the present invention three types of adjacent video signal lines respectively connected to three types of pixel forming portions that display predetermined three primary colors and adjacent to the video signal lines. Since it will be grouped to include only one of the three types of adjacent video signal lines, the number of output terminals can be halved compared to the case of the tenth aspect of the present invention and displayed in the same way. Since the color shift becomes difficult to be felt or cannot be felt at all, the occurrence of vertical stripes due to this shift can be eliminated. Further, even when a natural image is displayed, it is possible to make it difficult to perceive a display color shift.
  • FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 2 is a block diagram showing a configuration of a display control circuit in the embodiment.
  • FIG. 3 is a diagram schematically showing a configuration of a display unit in the embodiment.
  • FIG. 4 shows an equivalent circuit of the pixel formation portion P (n, m) in the display portion in the embodiment.
  • FIG. 5 is a diagram schematically showing a partial configuration of a video signal line driving circuit in the embodiment.
  • FIG. 6 is a diagram showing an example of a correspondence relationship between image data included in a digital image signal and a corresponding source clock signal number for explaining a driving method in the liquid crystal display device according to the embodiment.
  • FIG. 7 is a diagram showing another example of the correspondence relationship between the image data included in the digital image signal and the corresponding source clock signal number for explaining the driving method in the liquid crystal display device according to the embodiment. .
  • FIG. 8 is a diagram showing a change in potential of a video signal applied to video signal lines SL3 to SL7 of the display unit in the embodiment.
  • FIG. 9 is a diagram showing a display color shift in each pixel formation portion within a range from the pixel formation portion P (1, 1) to the pixel formation portion P (3, 9) in the embodiment.
  • FIG. 10 is an example of a correspondence relationship between image data included in a digital image signal and a corresponding source clock signal number for explaining a driving method of a liquid crystal display device according to a first modification of the embodiment.
  • FIG. 10 is an example of a correspondence relationship between image data included in a digital image signal and a corresponding source clock signal number for explaining a driving method of a liquid crystal display device according to a first modification of the embodiment.
  • FIG. 11 shows the correspondence between the image data contained in the digital image signal and the corresponding source clock signal number for explaining the driving method of the liquid crystal display device in the first modification of the embodiment. It is a figure which shows an example.
  • FIG. 12 is an example of a correspondence relationship between image data included in a digital image signal and a corresponding source clock signal number for explaining a driving method of a liquid crystal display device according to a second modification of the embodiment.
  • FIG. 12 is an example of a correspondence relationship between image data included in a digital image signal and a corresponding source clock signal number for explaining a driving method of a liquid crystal display device according to a second modification of the embodiment.
  • FIG. 13 illustrates a driving method for a liquid crystal display device according to a second modification of the embodiment. It is a figure which shows another example of the correspondence of the image data contained in the digital image signal for clarification, and the number of the corresponding source clock signal.
  • FIG. 14 is a schematic diagram showing a configuration of a display unit in a liquid crystal display device according to a second embodiment of the present invention.
  • FIG. 16 is a diagram showing in detail the potential change of the video signal applied to the video signal lines SL3 to SL7 of the liquid crystal display device in the embodiment.
  • GCK Clock signal for gate
  • FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to the first embodiment of the present invention.
  • This liquid crystal display device includes a display control circuit 200, a video signal line drive circuit (also referred to as “column electrode drive circuit” or “data driver”) 300, and a scanning signal line drive circuit (“row electrode drive circuit”). 400 (also referred to as a “gate driver”), an active matrix display portion (liquid crystal panel) 500, and a well-known common electrode driving circuit (not shown).
  • the display unit 500 as a display unit in the liquid crystal display device includes a plurality of scanning signal lines (rows) each corresponding to a horizontal scanning line in an image represented by image data Dv received from a CPU or the like in an external computer. Electrode), multiple video signal lines (column electrodes) intersecting with each of the multiple scanning signal lines, and intersections of the multiple scanning signal lines and multiple video signal lines, respectively. And a plurality of pixel formation portions provided in the same manner. The configuration of each pixel formation portion is basically the same as that in a conventional active matrix liquid crystal display device (details will be described later).
  • image data (in a narrow sense) representing an image to be displayed on the display unit 500 and Further, data for determining the timing of the display operation (for example, data indicating the frequency of the display clock) (hereinafter referred to as “display control data”) is sent to the display control circuit 200 from a CPU or the like in an external computer (hereinafter referred to as “display control data”).
  • These data Dv sent from outside are called “broad image data”). That is, an external CPU or the like supplies image data and display control data (in a narrow sense) constituting the image data Dv in a broad sense to the display control circuit 200 by supplying an address signal ADw, which will be described later in the display control circuit 200. Write to display memory and register respectively.
  • the display control circuit 200 based on the display control data written in the register, and the source clock signal SCK and the source start pulse signal SSP given to the video signal line driving circuit 300 for display, and the display control circuit run for display. ⁇ Generates various signals including the gate clock signal GCK and gate start pulse signal GSP given to the signal line driver circuit 400. Since these signals are publicly known, detailed description is omitted.
  • the display control circuit 200 sequentially reads out (in a narrow sense) image data written in the display memory by an external CPU or the like from the display memory so as to be phase-expanded into four phases for each color. After that, it is output as a digital image signal Da.
  • the display control circuit 200 gives a shift direction control signal (not shown) for inverting the shift direction of a shift register (described later) included in the video signal line driving circuit 300 to each display row.
  • the phase-expanded data representing the image to be displayed on the display unit 500 is supplied to the video signal line driving circuit 300 as a digital image signal Da in units of pixels, and at the same time.
  • a source clock signal SCK and a source start panelless signal SSP are supplied as signals indicating the above.
  • the video signal line driving circuit 300 is a video signal for driving the display unit 500 (hereinafter referred to as “driving video signal”). )) This is applied to each video signal line of the display unit 500.
  • the scanning signal line driving circuit 400 is configured to select each scanning signal line in the display unit 500 sequentially for each horizontal scanning period based on the gate clock signal GCK and the gate start panel signal GSP. Generates the strike signals Gl, G2, G3, ... to be applied to the signal lines, and applies one active strike signal to each strike signal line in order to select each of the strike signal lines in turn. The scanning period is repeated as a cycle.
  • the video signal lines Sl, S2, S3, ... for driving based on the digital image signal Da are applied to the video signal lines by the video signal line driving circuit 300 as described above.
  • the driving signal Gl, G2, G3,... Is applied to the driving signal line by the driving signal line driving circuit 400.
  • the display unit 500 displays an image represented by the image data Dv received from an external CPU or the like.
  • FIG. 2 is a block diagram showing a configuration of the display control circuit 200 in the liquid crystal display device.
  • the display control circuit 200 includes an input control circuit 20, a display memory 21, a register 22, a timing generation circuit 23, a memory control circuit 24, and a phase development control unit 25.
  • the display control circuit 200 receives a signal (hereinafter also referred to as “Dv”) indicating an image data Dv in a broad sense received from an external CPU or the like, and an address signal ADw are input control circuit 20 Is input. Based on the address signal ADw, the input control circuit 20 distributes the broad image data Dv into the image data DA and the display control data Dc. Then, the image data DA is displayed by supplying a signal representing the image data DA (hereinafter, these signals are also represented by the sign “DA”) to the display memory 21 together with the address signal AD based on the address signal ADw. Write to 21 and display control data Dc to register 22.
  • the display control data Dc includes timing information designating the frequency of the clock signal including the source clock signal SCK and the horizontal scanning period and the vertical scanning period for displaying the image represented by the image data Dv.
  • a timing generation circuit (hereinafter abbreviated as “TG”) 23 generates a source clock signal SCK and a source start pulse signal SSP based on the display control data held in the register 22.
  • TG23 also has display memory 21, memory control circuit 24, and phase expansion control Generates a timing signal to operate unit 25 in synchronization with the source clock signal SCK.
  • the memory control circuit 24 reads out data representing an image to be displayed on the display unit 500 from the image data DA input from the outside and stored in the display memory 21 via the input control circuit 20.
  • the address signal ADr and a signal for controlling the operation of the display memory 21 are generated.
  • the address signal ADr and the control signal are supplied to the display memory 21, whereby data representing an image to be displayed on the display unit 500 is read from the display memory 21 and supplied to the output buffer 26.
  • the phase expansion control unit 25 controls the memory control circuit 24 so that the data read from the display memory 21 is expanded in four phases for each RGB color.
  • the output buffer 26 receives these 4-phase expanded data and outputs it from the control circuit 200 as a signal digital image signal Da which is a 4-phase expanded signal.
  • the digital image signal Da is supplied to the video signal line drive circuit 300 as described above.
  • FIG. 3 schematically shows a configuration of the display unit 500 in the present embodiment
  • FIG. 4 shows an equivalent circuit of the pixel formation unit P (n, m) in the display unit 500.
  • each pixel forming portion P (n, m) has a gate terminal connected to the scanning signal line GL (n) passing through the corresponding intersection and passes the intersection.
  • N is 240
  • M is 320 X 3 (RGB).
  • the resolution of a display device having such color pixels is called QVGA.
  • each pixel formation portion P (n, m) has a red (R), green (G), or blue (B) color, or a shifted color.
  • pixel forming portions P (n, m) that display the same color are arranged along the video signal lines SL (1) to SL (M), and They are arranged in the order of RGB in the direction along the scanning signal lines GL (1) to GL (N).
  • the pixel formation part representing these RGB3 colors is shown as one pixel, so that one color pixel is composed of three pixel formation parts representing the RGB3 colors that are in contact with each other. Actually, this color pixel is visually recognized as one pixel. These colors are typical three primary colors, but may be other three primary colors.
  • alternating drive is performed in order to suppress deterioration of the liquid crystal and maintain display quality
  • pixels are arranged as a typical alternating drive method.
  • a so-called line inversion drive method is adopted in which the positive and negative polarity of the voltage applied to the liquid crystal layer to be formed is inverted for each signal line and for each frame.
  • a frame inversion driving method which is a driving method for inverting the positive / negative polarity of the voltage applied to the pixel liquid crystal only for each frame, or for each scanning signal line and for each video signal line
  • a so-called dot inversion drive method may be employed in which the image is inverted (and also inverted every frame). The reason will be described later.
  • a liquid crystal capacitor is formed by the pixel electrode Epix and a common electrode Ecom that is opposed to the pixel electrode Epix, and an auxiliary capacitor Cs is formed in the vicinity thereof. Has been.
  • the TFT 10 When the scanning signal G (n) applied to the scanning signal line GL (n) becomes active, the TFT 10 is selected and becomes conductive.
  • the driving video signal S (m) is applied to the pixel electrode Ep via the video signal line SL (m).
  • the voltage of the applied drive video signal S (m) (not shown, voltage based on the potential of the common electrode Ec set by the common electrode drive circuit) force includes the pixel electrode Ep It is written as a pixel value in the pixel formation part P (n, m).
  • FIG. 5 is a diagram simply showing a partial configuration of the video signal line driving circuit 300.
  • the video signal line driving circuit 300 includes the display control circuit 2 described above.
  • the digital image signal Da generated by the four-phase development for each color of R (red), G (green), and B (blue) by the phase development control unit 25 at 00 becomes 12 signal lines VR1, VG1,. Supplied by VB1, ..., V B4. These signal lines are referred to as 4-phase expanded signal lines below.
  • the shift register 31 is a bidirectional shift register that can shift in both directions (left and right directions), and has a configuration in which a plurality of stages of flip-flop circuits are connected in series.
  • the shift register 31 sequentially transfers (shifts) the source start pulse signal SSP in each of the stages in the forward direction or the reverse direction in synchronization with the source clock signal SCK.
  • Output pulses sequentially. That is, when shifting in the forward direction (right direction), the sampling pulses are sequentially output from the flip-flop circuits FF1, FF2,... From the left end to the right end, and shifted in the reverse direction (left direction). In this case, sampling pulses are sequentially output from each flip-flop circuit in the order of the right end force and the left end.
  • shift direction of the source start pulse signal SSP is referred to as a shift direction of the shift register 31, and a forward shift direction and a reverse shift direction are not shown in the display control circuit 200 for each display row, as will be described later. They are set alternately based on the direction control signal.
  • analog switches and wirings for switching signals to be applied to each flip-flop are not described in order to realize bidirectional shift, but these configurations are well known and will not be described. .
  • sampling pulse is supplied to the control terminal of each sampling switch (including SW1 shown in FIG. 5) provided corresponding to each stage of the shift register circuit 31.
  • the sampling switch is turned on and the digital image signal Da is given to each video signal line.
  • the sampling pulse from the flip-flop circuit FF1 is given to the sampling switch SW1
  • the signal line VR1 and the video signal line SL1 are connected and the video signal line SL1 is equal to the potential of the video signal applied to the signal line VR1. Is charged.
  • the sampling pulse from the flip-flop circuit FF1 is generated by three video signal lines connected to three adjacent pixel forming portions for displaying RGB colors.
  • 1 unit is left for each sampling switch corresponding to 4 units (12 lines in total) of video signal lines.
  • adjacent The unit that is given to the sampling switch corresponding to the video signal line of 4 units instead of 4 units is the display color shift due to the potential fluctuation due to the parasitic capacitance. This is because it is evenly scattered on the top (specifically, it is a check pattern here). Details will be described later with reference to FIG.
  • FIG. 6 is a diagram showing an example of a correspondence relationship between the image data included in the digital image signal Da and the number of the corresponding source clock signal SCK for explaining the driving method in the present liquid crystal display device.
  • Rl, Gl, B1,..., R320, G320, and B320 are image data for one row corresponding to each column.
  • R320 is the color of the 320th column of a certain row. It represents image data to be displayed on the pixel.
  • the four-phase expanded signal line VR1 has red (R) of the first color pixels. Image data R1 is applied, and green (G) image data G1 of the first color pixel is applied to the four-phase expanded signal line VG1.
  • the sampling panel is output from the flip-flop circuit FF1 as described above with reference to FIG. 5, and the video signal line SL1 Is given to 12 corresponding analog switches, including the analog switch connected to the.
  • the shift direction of the shift register 31 is the forward direction.
  • the scanning signal G (n) applied to the scanning signal line GL (n) of the corresponding row. n) is active. Therefore, the TFT 10 included in the corresponding pixel formation portion is selected and becomes conductive, and the driving video signal S (m), which is the image data, is transmitted to the pixel electrode Ep via the video signal line SL (m). Applied. As a result, the voltage of the applied driving image signal S (m) is written as a pixel value in the pixel formation portion P (n, m) including the pixel electrode Ep.
  • FIG. 7 is a diagram showing another example of the correspondence between the image data included in the digital image signal Da and the number of the corresponding source clock signal SCK for explaining the driving method in the present liquid crystal display device. is there. At this time, the shift direction of the shift register 31 is the reverse direction.
  • the four-phase expanded signal line VR1 has red (R) of the 314th color pixels.
  • Image data R314 is applied, and the green (G) image data G314 of the 314th color pixel is applied to the four-phase expanded signal line VG1.
  • the shift direction of the shift register 31 is alternately inverted to reduce display quality deterioration such as display color shift and vertical stripes caused by parasitic capacitance between adjacent video signal lines. can do. This will be described in detail below.
  • FIG. 8 is a diagram showing a change in the potential of the video signal applied to the video signal lines SL 3 to SL 7 in the display unit 500.
  • the amount of voltage fluctuation caused by the parasitic capacitance is shown larger than the actual amount of fluctuation.
  • the video signal from the video signal line driving circuit 300 to the video signal lines SL3 and SL7 at time tl (refer to FIG. 5 and FIG.
  • the image data B1 and the image data R3) are applied to the video signal line SL7 and the video signal lines SL3 and SL7, respectively.
  • this potential is maintained, so that the corresponding pixel formation portion, i.e. the pixel shape with reference to FIG.
  • the voltage values must be written as pixel values in the components P (l, 3) and P (l, 7)
  • the potential of SL3 also changes, and the potential of the video signal line SL7 to be held also changes according to the potential change of the video signal line SL6.
  • the parasitic capacitance between the adjacent video signal lines includes a direct capacitance between the signal lines and an indirect capacitance formed through the pixel formation portion.
  • the potential difference ⁇ is ideally generated between the potential to be held and the actual potential, thereby causing undesirable effects such as a shift in display color (blue in this case) and blurring.
  • the above problems are the same as those of the conventional display device.
  • the video signal is first applied from the video signal line driving circuit 300 to the video signal lines SL4 to SL6 at time t6. After that, since the video signal is applied from the video signal line driving circuit 300 to the video signal lines SL3 and SL7 at time t7, the potentials of the video signal lines SL4 and SL5 adjacent to the video signal lines SL3 and SL7 are also changed. It will change according to.
  • the potential difference AV is generated between the potential to be ideally held and the actual potential as described above, and referring to FIG. 9, the pixel forming portions ⁇ (2, 4), ⁇ (2 , 6) unfavorable effects such as deviation and blurring of the display color (red and green here).
  • the video signal is always applied to the video signal lines SL2 and SL5 at the same time regardless of the shift direction of the shift register 31, the video signal line adjacent to the video signal line SL4 after the video signal is applied to the video signal line SL4.
  • the potential does not change due to the potential change.
  • display color shifts and blurs that occur in the conventional display device all occur in the same display area IJ (pixel formation portion connected to the same video signal line) in each display row, so vertical stripes, etc. There is a problem that is easy to see in the form of.
  • display color shifts and blurring in this display device occur every other line, and the power to cause such display color shifts.
  • the large pixels are not adjacent in the vertical and horizontal directions. Therefore, in this display device, since the display color shift is not visually recognized in the form of vertical stripes, and the color pixels having the display color shift are close to each other in the oblique direction, the display color shift over the entire display screen. As a result of the distribution, the deviation itself is hardly visible. As a result, the display quality of the display device is improved. This will be briefly described with reference to FIG.
  • FIG. 9 is a diagram illustrating a display color shift in each pixel formation portion within a range from the pixel formation portion P (1, 1) to the pixel formation portion P (3, 9).
  • the hatched lines in the figure indicate that the display color is shifted in the pixel formation portion to which it is attached.
  • a square thick line frame attached so as to include three pixel forming portions indicates a single pixel in which the display color is shifted (consisting of three RGB colors).
  • the pixel forming portion P (2, 4) is supplied with the potential changed according to the potential fluctuation of the video signal line SL3 via the video signal line SL4, and the pixel forming portion P Since (2 and 6) is supplied via the video signal line SL6 with the potential changed according to the potential fluctuation of the video signal line SL7, it is displayed by these pixel formation part and pixel formation part P (2, 5).
  • the display colors of the color pixels are shifted so that red and blue have higher luminance.
  • such a display color shift also occurs in the color pixels displayed by the pixel forming portions P (l, 7), P (l, 8), P (l, 9), for example.
  • the color pixels in which the display color is shifted have a so-called checker pattern as a whole without being adjacent in the display row or display column direction. I understand. Therefore, the display color shift is less likely to be visually recognized.
  • the shift register is displayed for each display row. Since the shift direction of 31 is reversed, the display color shift caused by parasitic capacitance between adjacent video signal lines occurs every other line, and the video signal lines connected to the three pixel forming portions forming the color pixels At the same time, since the video signal is applied, the color pixels in which the display color is shifted do not adjoin the display row or the display column direction, and present a so-called checker pattern (checkered pattern) as a whole. Therefore, it is possible to reduce or eliminate display quality deterioration such as display color shift and the occurrence of vertical stripes with a simple apparatus configuration.
  • the image data to be applied to the four-phase expanded signal line when each source clock signal SCK is applied to the shift register 31.
  • FIG. 6 and FIG. The image data to be applied to the 4-phase expanded signal line when the even-numbered clock signal SCK shown in FIG. 4 is applied to the shift register 31 may be interchanged with that when the odd-numbered clock signal SCK is applied. Les.
  • FIG. 10 is a diagram illustrating the source clock signal SCK corresponding to the image data included in the digital image signal Da for explaining the method of driving the liquid crystal display device according to the above-described modification of the first embodiment. It is a figure which shows an example of the correspondence with a number. At this time, the shift direction of the shift register 31 is the forward direction.
  • FIG. 11 is a diagram showing another example of the correspondence between the image data included in the digital image signal Da and the number of the corresponding source clock signal SCK for explaining the driving method in the liquid crystal display device. is there. At this time, the shift direction of the shift register 31 is the reverse direction.
  • the shift direction of the shift register 31 is inverted for each display row as in the case of the first embodiment.
  • Display color shifts caused by parasitic capacitance between the display lines occur every other line, and video signals are simultaneously applied to the video signal lines connected to the three pixel formation units forming the color pixels, resulting in display color shifts.
  • the displayed color pixels do not adjoin in the display row or display column direction, and as a whole exhibit a so-called checker pattern. Therefore, it is possible to reduce or eliminate the deterioration of display quality such as a display color shift and the occurrence of vertical stripes with a simple apparatus configuration.
  • the force is a configuration in which four-phase expansion processing is performed for each RGB image data.
  • the four-phase expansion processing does not necessarily have to be performed for each RGB image data.
  • a configuration in which a four-phase expansion process is performed for every two image data to be given to adjacent pixel forming units in the same row may be used.
  • the phase expansion processing is performed for each RGB image data, when the same potential is applied to each video signal line from the video signal line drive circuit (that is, when all RGB have the same luminance).
  • the display color shifts are all the same, so the shifts are not visually recognized and the display quality of the display device is improved.
  • FIG. 12 is a diagram illustrating the source clock signal SCK corresponding to the image data included in the digital image signal Da for explaining the driving method of the liquid crystal display device in the above-described modification of the first embodiment. It is a figure which shows an example of the correspondence with a number. At this time, the shift direction of the shift register 31 is the forward direction.
  • FIG. 13 shows another example of the correspondence relationship between the image data included in the digital image signal Da and the number of the corresponding source clock signal SCK for explaining the driving method in the liquid crystal display device.
  • the shift direction of the shift register 31 is the reverse direction.
  • the shift direction of the shift register 31 is inverted for each display row as in the case of the first embodiment.
  • a display color shift caused by parasitic capacitance or the like occurs every other line. Because of this, the display color shift is not the same in the adjacent display lines. Deterioration of display quality such as vertical stripes can be reduced or eliminated with a simple device configuration.
  • the shift direction of the shift register 31 is the forward direction in the example shown in FIG. 6, and the shift direction of the shift register 31 is the reverse direction in the example shown in FIG. You can be. The same applies to the first and second modified examples.
  • the line inversion driving method is adopted as described above, but the frame inversion driving method may be adopted.
  • the shift direction of the shift register 31 may be inverted every frame.
  • the checker pattern as shown in Fig. 9 does not occur, but if two consecutive frames are observed together, the display color will be shifted almost uniformly. Therefore, it becomes difficult to feel this shift, and the occurrence of the vertical stripes can be completely suppressed.
  • a dot inversion driving method may be employed instead of the line inversion driving method.
  • the polarity of the video signal applied to the adjacent video signal line (with respect to the common electrode potential) is inverted, so the parasitic capacitance affects the potential of the video signal line to be affected.
  • the common electrode potential that is, to reduce the display luminance of the pixel formation portion to which the potential is applied.
  • the display color shift is the same as a result, and the generation position is the same. Therefore, it can be considered in the same way as the case of the first embodiment, and it is possible to achieve the same effect S.
  • the first embodiment is connected to three adjacent pixel forming portions that display RGB colors.
  • the video signal lines are simultaneously given to four units (total of 12 video signals) with one unit each open. It may be 4 units in a row, or a configuration in which 2 units or more are available.
  • 4 units of video signal lines are set as one set and video signals are simultaneously given to this set, two video signals adjacent at the boundary between this set and the adjacent set.
  • the display color shifts due to potential fluctuations due to parasitic capacitance in the lines, but unlike conventional configurations, there are no vertical stripes of specific colors, so this configuration also reduces display quality degradation. be able to.
  • the configuration of the liquid crystal display device according to the present embodiment is substantially the same as the configuration of the liquid crystal display device according to the first embodiment shown in FIG. 1, the same reference numerals are given to the same components, and Description is omitted, and only different points will be described below.
  • the so-called line inversion driving method is adopted as the alternating drive method, but a so-called frame inversion method or dot inversion driving method may be adopted. The reason will be described later.
  • the display control circuit 200 employs the video signal line time-division driving method instead of the reciprocal driving method, so that the video signal line is time-division driven.
  • Switch control signals GSa to GSc (hereinafter, these signals are also referred to as “switch control signal GS”) and output them. These switching control signals GSa to GSc are supplied to a connection switching circuit described later in the display unit 500.
  • the display control circuit 200 is not provided with the phase expansion control unit 25 provided in the case of the first embodiment, but is provided with a signal line switching control circuit that generates the switching control signal GS. It has been.
  • This signal line switching control circuit generates switching control signals GSa to GSc for time division driving of the video signal lines based on the timing signal from TG23.
  • These switching control signals GSa to GSc are used to horizontally apply the video signal line to which the video signal output from the video signal line driving circuit 300 is applied in order to drive the video signal line in a time-sharing manner as will be described later. This is a control signal for switching within the scavenging period.
  • each horizontal scanning period (period in which the scanning signal is active) is divided into three equal periods from the first period to the third period.
  • a signal that alternately becomes H level (every horizontal scanning period) and becomes L level in other periods is generated as the switching control signal GSa, and becomes H level in the second period and becomes L level in other periods.
  • Is generated as the switching control signal GSb, and a signal that alternately becomes H level in the third or first period (every horizontal scanning period) and becomes L level in the other periods is generated as the switching control signal GSc.
  • FIG. 14 is a schematic diagram showing a configuration of the display unit 500 in the present embodiment.
  • the display unit 500 is connected to a plurality of video signal lines connected to the video signal line driving circuit 300 and a scanning signal line driving circuit 400 via a connection switching circuit 501 including analog switches SW1, SW2, SW3,. A plurality of scanning signal lines.
  • the video signal lines Ls in the display unit are grouped into a plurality of video signal line groups, with three as one set, and each video signal line group (three video signal lines in the same set) These are connected to one output terminal TSj in the video signal line driving circuit 300 through three analog switches in the same set.
  • the output terminal TSj of the video signal line driving circuit 300 is associated with the video signal line group on a one-to-one basis. It is connected to the same set of video signal line groups (three video signal lines) via the three analog switches in the same set.
  • FIG. 15 is a timing chart for explaining a driving method in the present liquid crystal display device.
  • scanning signals Gl, G2, G3,... are sequentially applied to the scanning signal lines in the display unit 500.
  • the scanning signals Gl, G2, G3,... Sequentially become H level for each horizontal scanning period (one scanning line selection period).
  • each scanning signal line becomes a selected state (active) when an H level is applied, and is connected to the selected scanning signal line.
  • the TFT 10 in the part P is turned on.
  • the TFT 10 in the pixel forming part P connected to the scanning signal line in the non-selected state becomes in the off state. Become.
  • the analog switch SW (3j-2) connected to the (3 ⁇ 42) -th video signal line is turned on when the switching control signal GSa is at the H level. Turns OFF when the switching control signal GSa is at L level.
  • the analog switch SW (3j 1) connected to the (3 ⁇ 4 1) th video signal line is turned on when the switching control signal GSb is at the H level, and turned off when the switching control signal GSb is at the L level.
  • the analog switch SW3j connected to the third video signal line is turned on when the switching control signal GSc is at the H level and turned off when the switching control signal GSc is at the L level.
  • each output terminal TSj of the video signal line drive circuit 300 is connected to the (# 1-2) th video signal line in the first period of the odd-numbered horizontal scanning period, for example, and the odd-numbered horizontal In the second period of the scanning period, it is connected to the (3 ⁇ 41) th video signal line, and in the third period of the odd-numbered horizontal scanning period, it is connected to the 3 ⁇ 4th video signal line.
  • the video signal to be output from the output terminal TS1 in the video signal line driving circuit 300 SI and the video signal S2 to be output from the output terminal TS2 are signals as shown in FIG.
  • the timing chart in FIG. 15 showing these video signals SI and S2 is composed of two upper and lower stages, and the upper part is the color to be displayed on the pixel forming portion P by the video signals SI and S2 (actually, The lower part shows the video signal lines to which the video signals Sl and S2 should be applied.
  • the video signal line driving circuit 300 first causes the TFT 10 to be activated by the scanning signal Gk in the pixel formation portion P of the (3 ⁇ 4_2) -th pixel column in the pixel matrix.
  • the pixel values to be written in the pixel forming portion P to be turned on here, the pixel values for displaying R
  • the video signal Sj corresponding to these pixel values is output from the output terminal TSj.
  • the pixel values for display) are sequentially input from the display control circuit 200, and in the second period of the odd-numbered horizontal scanning period, video signal examples corresponding to these pixel values are output from the output terminal TSj.
  • the pixel value to be written to the pixel formation portion P in which the TFT 10 is turned on by the scanning signal Gk in the pixel formation portion P of the third pixel column in the pixel matrix (here, the pixel value for displaying B) ) are sequentially input from the display control circuit 200, and in the third period in the odd-numbered horizontal scanning period, video signals corresponding to those pixel values are output from the output terminal TSj.
  • the video signal line driving circuit 300 supplies pixel values corresponding to the respective colors to the pixel forming portions P via the video signal lines in the order of R ⁇ G ⁇ B in the odd-numbered horizontal scanning period. Since the writing operation is performed, the voltage of the video signal to be written to the pixel formation portion that forms red (R) and the pixel formation portion that forms green (G) due to the parasitic capacitance between the adjacent video signal lines described above. If this happens, the display quality may deteriorate, such as the occurrence of vertical stripes due to the display color shift similar to the conventional video signal line time division drive type liquid crystal display device.
  • the video signal line drive circuit 300 in the present embodiment provides pixels corresponding to the respective colors to the respective pixel formation portions P via the respective video signal lines in the order of B ⁇ G ⁇ R in the even-numbered horizontal scanning period.
  • the TFT 10 is turned on by the scan signal Gk in the pixel formation part P of the (3 ⁇ 4 _ 1) th pixel column in the pixel matrix.
  • the pixel value to be written to the pixel forming portion P, and in the third period of the even-numbered horizontal scanning period, the pixel value of the pixel forming section P of the (3 ⁇ 4_2) -th pixel column in the pixel matrix is determined by the driving signal Gk.
  • TFT10 is on
  • FIG. 16 is a diagram showing in detail the potential change of the video signal applied to the video signal lines SL3 to SL7 of the liquid crystal display device shown in FIG. For the sake of explanation, the figure shows the amount of voltage fluctuation caused by the parasitic capacitance and the like larger than the actual fluctuation amount.
  • the video signal line drive circuit power is applied to the video signal line SL4 at time tl, which is the time when the odd-numbered horizontal scanning period starts.
  • time tl the time when the odd-numbered horizontal scanning period starts.
  • the potential of the video signal line SL4 becomes a desired potential.
  • the voltage value must be written as the pixel value in the corresponding pixel formation portion P.
  • the video signal lines SL3 and SL4 are also capacitively coupled, when a video signal is applied to the video signal line SL3 from the video signal line drive circuit at time t3, the video signal line The potential of the video signal line SL4 changes according to the potential change of SL3. This results in an ideal In reality, the potential difference AV4 between the potential to be held and the actual potential causes the potential difference AV5a to occur on the video signal line SL5 for the same reason, and the display color (here red and green). ) Unfavorable effects such as deviation and blurring.
  • each pixel forming unit P is associated with each color via each video signal line in the order of B ⁇ G ⁇ R. Since the pixel value is written, the potential of the video signal line SL6 becomes a desired potential at time t4 when the even-numbered horizontal scanning period starts. However, when the potential of the video signal line SL5 changes at time t5 and the potential of the video signal line SL7 changes at time t6, the potential of the video signal line SL6 changes according to these potential changes for the reasons described above. Therefore, a potential difference ⁇ 6 occurs between the potential to be held and the actual potential.
  • the potential of the video signal line SL5 also changes according to the change in the potential of the video signal line SL4 at time t6, and a potential difference AV5b is generated between the potential to be held and the actual potential. Therefore, here, unlike the case of the odd-numbered horizontal scanning period, a blue and green shift occurs. Note that the voltage value changed after the video signal is applied from the video signal line drive circuit to the video signal line SL4 at time t6 is not written as the pixel value in the corresponding pixel formation portion P.
  • the line inversion driving method is adopted.
  • the polarity is at least for each frame.
  • the order in which the pixel values corresponding to the respective colors are written to the respective pixel forming portions P via the respective video signal lines is reversed (replaced). That is, as described above, in a certain frame, in the order of odd-numbered horizontal running periods, the order is R ⁇ G ⁇ B, and in the case of even-numbered horizontal running periods, the order is B ⁇ G ⁇ R.
  • the operation is performed in the order of B ⁇ G ⁇ R for the odd-numbered horizontal running period, and in the order of R ⁇ G ⁇ B for the even-numbered horizontal running period. Reverse the above order to be done.
  • the display color deviation in this specification is the luminance balance of red (R), green (G), and blue (B) in the original ideal display color (given from the outside of the device).
  • Luminance ratio is in a collapsed state. If this luminance is increased or decreased while this balance is maintained, it can be said that display color shift does not occur visually.
  • the length of one frame in this embodiment is 1Z60 [seconds] (that is, the drive frequency is 60 [Hz]) or more, the difference in luminance is the limit of time that is not visually recognized as flicker. Two frames will be displayed within [seconds]. Therefore, in this case, no flicker occurs in the display device.
  • each video signal line is supplied with the same potential from the video signal line driving circuit (that is, when all RGB have the same luminance).
  • the parasitic capacitance between the video signal lines is almost the same, if the adjacent display rows are observed together, it will be difficult to feel the display color shift, and the occurrence of vertical stripes due to this shift will be eliminated.
  • the display color will not be noticed at all, and the occurrence of vertical stripes due to this difference can be completely eliminated.
  • the color image to be displayed is a general natural image or the like, it is rare that the same potential is applied to each video signal line from the video signal line drive circuit (that is, all R GBs). However, it is rare that the same luminance is the same luminance), but a certain color error pixel constituting a general color image is often the same or similar color to neighboring color pixels. RGB luminances are often equal or approximate. Because of this, if the display rows adjacent to each other in the same display column are observed together, the display color shift often differs for each display row. The power to cancel S is possible. In addition, in general moving images and still images that are slow moving, color pixels at the same position in consecutive frames are often the same color. Because of this, the display color shift often becomes almost the same between two consecutive frames, so that if the two consecutive frames are observed together, the display color shift becomes difficult to perceive.
  • the order of writing is reversed in R ⁇ G ⁇ B and B ⁇ G ⁇ R every horizontal scanning period, but without reversing the order every horizontal scanning period, It is possible to reverse the order only for each frame. Even in this configuration, when the same potential is applied to each video signal line from the video signal line driving circuit (that is, when all RGB have the same luminance), the parasitic capacitance between the video signal lines is small. If they are almost the same, observing two consecutive frames together makes it impossible to perceive a display color shift and eliminates vertical stripes caused by this shift.
  • the video signal lines are driven in a time-sharing manner in the order of R, G, B and vice versa, and the driving order S is not limited to this driving order. It may be driven in a time-sharing manner in the order and in the reverse order.
  • a video signal line time-division drive type liquid crystal with a time division number of 3 in which three video signal lines for transmitting a video signal to adjacent three pixels of each RGB color are grouped into a group and is grouped into three groups.
  • the number of time divisions may be four or more. For example, when the number of time divisions is 6, the pixel values to be written to the video signal line connected to each pixel forming unit that displays a color pixel are Rl, Gl, and B1, and the color pixel adjacent to this color pixel is displayed.
  • the order is R1 ⁇ B1 ⁇ G2 ⁇ G1 ⁇ R2 ⁇ B2.
  • the above order is reversed and written in the order B2-> R2-> G1-> G2-> B1-> R1, and these are reversed (replaced) for each frame. Also good.
  • the potential change due to the parasitic capacitance in all the video signal lines is caused by the potential change of the two adjacent video signal lines in the two adjacent horizontal scanning periods. Therefore, the video signal line is driven to each video signal line.
  • the phase expansion drive method in the first embodiment and the video signal line time division drive method in the second embodiment are a set of two or more video signal lines among a plurality of video signal lines. It can be said that this is the same drive system in that the video signal lines are driven by applying video signals in a predetermined order to a plurality of sets of video signal lines obtained by gnoleping.
  • the number of video signal lines of the display device in the first embodiment is 3 Since it is 20 X 3 (RGB) lines, it requires a total of 80 writing operations per horizontal scanning period in order to drive it with 4-phase expansion processing for each RGB image data (for example, Fig. 6). See Figure 7. Therefore, such driving can be regarded as driving with the video signal line time-division driving method in which the number of time divisions is 80.
  • the present invention is applied to an active matrix display device such as a liquid crystal display device using a switching element such as a thin film transistor, and is suitable for an active matrix display device that performs high-definition color display, for example. Yes.

Abstract

Il est possible de réduire ou d'éliminer l'altération d'une couleur d'affichage et les bandes provoquées par une capacité parasite ou similaire entre des lignes adjacentes d'un signal vidéo avec un dispositif de configuration simple, en utilisant le procédé de commande par étalement de phase et le procédé de commande par répartition dans le temps des lignes d'un signal vidéo. Un signal d'image numérique Da, soumis à un étalement sur 4 phases pour chacune des couleurs RVB, est fourni à un circuit de commande de lignes de signal vidéo (300). Un registre à décalage (31) peut être décalé dans les deux sens et produit successivement une impulsion d'échantillonnage à partir de chaque étage. Lorsque trois lignes de signal vidéo reliées à une unité de formatage d'image affichant les couleurs RVB respectives forment une seule unité, l'impulsion d'échantillonnage est fournie à un commutateur d'échantillonnage correspondant à des lignes de signal vidéo de 4 unités (12 lignes au total) laissant chacune un espace de 1 unité. En outre, le sens du décalage est inversé pour chaque ligne d'affichage. Par conséquent, le pixel de couleur dont une couleur d'affichage est altérée présente un motif en damier et la production de cette altération de la couleur d'affichage et des bandes qui accompagnent celle-ci peut être réduite ou éliminée.
PCT/JP2007/055812 2006-08-30 2007-03-22 Dispositif d'affichage et son procédé de commande WO2008026338A1 (fr)

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JP2006-233126 2006-08-30
JP2006233126 2006-08-30

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WO2008026338A1 true WO2008026338A1 (fr) 2008-03-06

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102136241A (zh) * 2010-12-30 2011-07-27 友达光电股份有限公司 移位暂存器电路

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Publication number Priority date Publication date Assignee Title
JP2001166277A (ja) * 1999-12-08 2001-06-22 Mitsubishi Electric Corp 液晶表示装置
JP2002215117A (ja) * 2000-12-29 2002-07-31 Lg Philips Lcd Co Ltd 液晶表示装置の駆動方法
JP2003076334A (ja) * 2001-09-04 2003-03-14 Toshiba Corp 表示装置
JP2006030529A (ja) * 2004-07-15 2006-02-02 Seiko Epson Corp 電気光学装置用駆動回路及び電気光学装置用駆動方法、並びに電気光学装置及び電子機器
JP2006154808A (ja) * 2004-11-05 2006-06-15 Nec Corp 液晶表示装置、プロジェクタ装置、携帯端末装置、液晶表示装置の駆動方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001166277A (ja) * 1999-12-08 2001-06-22 Mitsubishi Electric Corp 液晶表示装置
JP2002215117A (ja) * 2000-12-29 2002-07-31 Lg Philips Lcd Co Ltd 液晶表示装置の駆動方法
JP2003076334A (ja) * 2001-09-04 2003-03-14 Toshiba Corp 表示装置
JP2006030529A (ja) * 2004-07-15 2006-02-02 Seiko Epson Corp 電気光学装置用駆動回路及び電気光学装置用駆動方法、並びに電気光学装置及び電子機器
JP2006154808A (ja) * 2004-11-05 2006-06-15 Nec Corp 液晶表示装置、プロジェクタ装置、携帯端末装置、液晶表示装置の駆動方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102136241A (zh) * 2010-12-30 2011-07-27 友达光电股份有限公司 移位暂存器电路

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