WO2008007613A1 - Wiring board and solid-state imaging device - Google Patents
Wiring board and solid-state imaging device Download PDFInfo
- Publication number
- WO2008007613A1 WO2008007613A1 PCT/JP2007/063494 JP2007063494W WO2008007613A1 WO 2008007613 A1 WO2008007613 A1 WO 2008007613A1 JP 2007063494 W JP2007063494 W JP 2007063494W WO 2008007613 A1 WO2008007613 A1 WO 2008007613A1
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- WO
- WIPO (PCT)
- Prior art keywords
- solid
- state imaging
- imaging device
- wiring board
- charge transfer
- Prior art date
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- 238000003384 imaging method Methods 0.000 title claims abstract description 119
- 238000001514 detection method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/4809—Loop shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0295—Programmable, customizable or modifiable circuits adapted for choosing between different types or different locations of mounted components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09254—Branched layout
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09954—More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/166—Alignment or registration; Control of registration
Definitions
- the present invention relates to a wiring board for mounting a solid-state imaging device, and a solid-state imaging device.
- the front-illuminated solid-state imaging device includes a solid-state imaging device in which a light detection portion and a terminal electrode electrically connected to the light detection portion are provided on one side, and one of the surfaces is a light receiving surface.
- the solid-state imaging device is mounted on the wiring board so that the other side faces the wiring board, and the terminal electrode of the solid-state imaging element and the electrode pad of the wiring board are connected by wire bonding. . (For example, see Patent Document 1).
- a light detection unit and a terminal electrode electrically connected to the light detection unit are provided on one surface, and the other surface is a light receiving surface.
- the terminal electrode of the solid-state imaging device and the electrode pad of the wiring board are connected by bump bonding It is. (For example, see Patent Document 2).
- the back-illuminated solid-state imaging device is more expensive than the front-illuminated solid-state imaging device because the thinned portion is formed in the solid-state imaging device. Therefore, in terms of manufacturing cost, the front-illuminated solid-state image sensor and the back-illuminated solid-state image sensor are commonly used (that is, the process before the thinned portion is formed).
- Patent Document 1 JP-A-10-107255
- Patent Document 2 JP-A-6-45574
- a wiring board is used in the front-illuminated solid-state image sensor and the back-illuminated solid-state image sensor. Since the electrical connection forms with the wire bonding and the bump bonding are different, the electrode pad forming positions on the wiring board are also different. Therefore, it is necessary to prepare a wiring board for mounting a front-illuminated solid-state image sensor and a wiring board for mounting a back-illuminated solid-state image sensor, even when using a solid-state image sensor of a common platform. There was a problem in manufacturing cost.
- the present invention provides a versatile high-density wiring board that can be mounted on either a front-illuminated or back-illuminated solid-state imaging device, and a solid-state imaging device using the wiring board. With the goal.
- the wiring board of the present invention is a wiring board having a planned placement area on which a solid-state imaging device is placed, and includes a plurality of first electrode pads formed in the planned placement area and outside the planned placement area. And a plurality of second electrode pads electrically connected to each of the first electrode pads.
- a plurality of first electrode pads are formed in the planned arrangement area, and a plurality of second electrode pads are formed outside the planned arrangement area. Therefore, when a back-illuminated solid-state imaging device is mounted, the terminal electrode and the first electrode pad can be electrically connected by bump bonding. On the other hand, when a front-illuminated solid-state imaging device is mounted, the terminal electrode and the second electrode pad can be electrically connected by wire bonding. Furthermore, since the corresponding first electrode pad and second electrode pad are electrically connected, a common input / output signal can be transmitted. Therefore, it is possible to provide a highly versatile wiring board that can be mounted on either a front-illuminated or back-illuminated solid-state imaging device.
- the wiring board of the present invention preferably includes an alignment mark indicating a placement planned area.
- the solid-state imaging device can be accurately placed in the planned placement area using the alignment mark as a reference.
- the solid-state imaging device of the present invention is a solid-state imaging device in which a solid-state imaging device is arranged in a planned layout area of a wiring board, and the wiring board is a plurality of first elements formed in the planned layout area.
- the electrode pads are formed outside the planned placement area and are electrically connected to each of the first electrode pads.
- a plurality of second electrode pads that are electrically connected to each other, and the solid-state imaging device includes a light detection unit provided on a surface facing the light receiving surface, and a terminal electrically connected to the light detection unit And the photodetection unit is provided in each of the vertical charge transfer unit, the horizontal charge transfer unit provided on both sides of the vertical charge transfer unit, and the horizontal charge transfer unit, and receives a signal from the horizontal charge transfer unit.
- a signal reading unit for reading a signal, and the terminal electrode is electrically connected to the first electrode pad by bump bonding.
- the solid-state imaging device of the present invention is a solid-state imaging device in which a solid-state imaging device is disposed in a planned placement area of a wiring board, and the wiring board includes a plurality of first elements formed in the planned placement area. And a plurality of second electrode pads formed outside the planned arrangement area and electrically connected to each of the first electrode pads, and the solid-state imaging device is provided on the light receiving surface.
- a photodetecting unit, and a terminal electrode electrically connected to the photodetecting unit wherein the photodetecting unit includes a vertical charge transfer unit, horizontal charge transfer units provided on both sides of the vertical charge transfer unit, A signal reading unit that is provided in each of the horizontal charge transfer units and reads a signal from the horizontal charge transfer unit, and the terminal electrode is electrically connected to the second electrode pad by wire bonding. It is characterized by.
- a front-illuminated solid-state imaging device and a back-illuminated solid-state imaging device can be provided at low cost.
- an electrical insulating layer is provided between the wiring board and the solid-state imaging element in the planned arrangement region.
- the front-illuminated solid-state imaging device and the second electrode pad of the wiring board can be electrically insulated by the electrical insulating layer. Therefore, input / output signals can be reliably transmitted to the front-illuminated solid-state imaging device via the wiring board.
- a versatile high-density wiring board that can be mounted on either a front-illuminated or back-illuminated solid-state imaging device, and a solid-state imaging device using the wiring board. Can do.
- FIG. 1 is a plan view showing an embodiment of a wiring board according to the present invention.
- FIG. 2 is a cross-sectional view taken along line II-II of the wiring board in FIG.
- FIG. 3 is a diagram showing an example of a solid-state imaging device having input / output compatible terminal electrode arrangements of a front-illuminated type and a back-illuminated type.
- FIG. 4 is a plan view showing an embodiment of a solid-state imaging device of the present invention.
- FIG. 5 is a cross-sectional view of the solid-state imaging device in FIG. 4, taken along line V—V.
- FIG. 6 is a plan view showing another embodiment of the solid-state imaging device of the present invention.
- FIG. 7 is a cross-sectional view of the solid-state imaging device in FIG. 6 along the line VII-VII.
- FIG. 1 is a plan view showing an embodiment of a wiring board of the present invention.
- FIG. 2 is a cross-sectional view taken along line II-II of the wiring board in FIG.
- the wiring substrate 1 includes a ceramic multilayer substrate (ceramic material is, for example, aluminum nitride) 11 having a rectangular shape in plan view, and a predetermined position on the surface thereof includes a first electrode pad 12, a second electrode pad 13, and a position.
- An alignment mark 14 is formed.
- internal wiring 15 is formed inside the substrate 11, and external terminals 16 are formed on the side surfaces of the substrate 11.
- a plurality of first electrode pads 12 are formed on the surface of the substrate 11 and inside the planned placement area la.
- the arrangement planned area la is an area in which the solid-state imaging device is arranged, and has a rectangular shape extending in the long side direction of the substrate 11 at the approximate center of the rectangular substrate 11 in plan view.
- the first electrode pads 12 are arranged in a row over the peripheral edge of the rectangular arrangement planned area la. Is arranged.
- the first electrode pad 12 is for bump bonding with the terminal electrode of the back-illuminated solid-state image sensor, and the formation position of the first electrode pad 12 is the back-illuminated solid-state image sensor. Corresponds to the position of the terminal electrode of the element
- a plurality of second electrode pads 13 are formed on the surface of the substrate 11 and outside the planned arrangement region la. That is, they are arranged in a row outside the planned placement area la so as to surround the rectangular placement planned area la. Further, the same number of second electrode pads 13 as the first electrode pads 12 are formed.
- the second electrode pad 13 is used for wire bonding with the terminal electrode of the front-illuminated solid-state image sensor, and the second electrode pad 13 is formed at the position of the front-illuminated solid-state image sensor to be arranged. Corresponds to the terminal electrode formation position.
- the first electrode pad 12 and the second electrode pad 13 are formed by a printing method or a sputtering method using a conductive material such as a metal.
- the alignment mark 14 is formed to indicate a planned arrangement area la in which the solid-state imaging device is arranged. Specifically, four alignment marks 14 are formed between the arrangement of the first electrode pads 12 and the arrangement of the second electrode pads 13. When a solid-state imaging device is arranged, the solid-state imaging device is fixed so that the four corners of the device are aligned with the four alignment marks 14 respectively. Similar to the first electrode pad 12 and the second electrode pad 13, the alignment mark 14 can be formed by a printing method or a method such as sputtering.
- the corresponding first electrode pad 12 and second electrode pad 13 are electrically connected by an internal wiring 15.
- Each internal wiring 15 is electrically connected to a plurality of external terminals 16 formed so as to extend downward from the side surface of the substrate 11.
- a common input / output signal is transmitted to the corresponding first electrode pad 12 and second electrode pad 13 via the internal wiring 15 and the external terminal 16.
- a pulse for vertical charge transfer from the external terminal 16 is used.
- the vertical charge transfer pulse is transmitted to both the first electrode pad 12 and the second electrode pad 13 via the internal wiring 15.
- the lid 13 is appropriately determined according to the arrangement of the terminal electrodes of the front-illuminated solid-state imaging device and the back-illuminated solid-state imaging device arranged on the wiring board.
- the terminal electrode arrangement of each of the front-illuminated solid-state image sensor and back-illuminated solid-state image sensor arranged on the wiring board 1 is a front-illuminated type and back-illuminated type input / output compatible arrangement, a rectangular arrangement is used.
- the first electrode pad 12 and the second electrode pad 13 facing each other across the outer periphery of the planned area la are connected by the internal wiring 15. In this case, since the adjacent electrode pads 12 and 13 are connected to each other, the internal wiring 15 can be handled easily.
- FIG. 3 is a diagram showing an example of a solid-state image sensor having input / output compatible terminal electrode arrangements of a front-illuminated type and a back-illuminated type.
- the solid-state imaging device 2 includes a CCD 20, which has a vertical charge transfer unit 201 and horizontal charge transfer units 202 and 203 on both sides of the vertical charge transfer unit 201.
- signal reading units 204 and 205 are provided in the horizontal charge transfer units 202 and 203, respectively, and signals can be read from either of the signal reading units 204 and 205.
- the terminal electrode 22 (P1V, P2V, P3V, TGA, TGB, OFG, OFD, P1H, P2H, OS, OD, RG, RD, etc. (some not shown)) is arranged in the longitudinal direction of the solid-state imaging device 2 It is arranged so as to be symmetric with respect to the center line 21 extending in the direction of the axis.
- the charge transfer direction (solid arrow indicates the back side S2) when placed on the wiring board from the back surface S2 side and when placed on the wiring board from the front surface S1 side with the center line 21 of this element turned over. This is a common input / output device that does not change the input / output position of the signal.
- the horizontal charge transfer unit may be formed only on one end side of the vertical charge transfer unit.
- a plurality of first electrode pads 12 are formed in the planned placement area la, and a second electrode pad 13 is formed outside the planned placement area la. Yes. Therefore, when a back-illuminated solid-state imaging device is mounted, the terminal electrode and the first electrode pad 12 can be electrically connected by bump bonding. On the other hand, surface incidence When a solid-state image sensor is mounted, the terminal electrode and the second electrode pad 13 can be electrically connected by wire bonding. Further, since the corresponding first electrode pad 12 and second electrode pad 13 are electrically connected, a common input / output signal can be transmitted. Therefore, it is possible to provide a highly versatile wiring board 1 that can be mounted on either a front-illuminated or back-illuminated solid-state imaging device.
- the solid-state imaging device is placed on the planned placement area la with high accuracy by using the alignment mark 14 as a reference. be able to.
- FIG. 4 is a plan view showing an embodiment of the solid-state imaging device of the present invention.
- FIG. 5 is a cross-sectional view taken along line VV of the solid-state imaging device in FIG.
- the back-illuminated solid-state imaging device 3 includes a wiring board 1, a back-illuminated solid-state imaging device 30, and conductive bumps 31.
- the back-illuminated solid-state imaging device 3 is a back-illuminated solid-state imaging device having an input / output compatible terminal electrode arrangement of the front-illuminated type and back-illuminated type shown in FIG. 3 on the wiring board according to the above-described embodiment. Is a device equipped with.
- the back-illuminated solid-state imaging element 30 has a rectangular shape in a plan view having a size corresponding to the planned layout area la of the wiring board 1.
- the back-illuminated solid-state imaging device 30 is composed of, for example, a silicon P + layer and a P epoxy layer formed thereon.
- a CCD 32 as a light detection part is formed on a part of the surface layer on the surface S1 side.
- the CCD 32 has a plurality of pixels arranged two-dimensionally, for example, 1024 pixels ⁇ 128 pixels. Further, the CCD 32 has a vertical charge transfer unit 321 and horizontal charge transfer units 322 and 323 as shown in FIG.
- the back-illuminated solid-state imaging device 30 is formed with a thinned portion 33 which is thinned by etching a region facing the CCD 32 on the back surface S2.
- the thinned portion 33 is a flat light receiving surface S3 having a rectangular shape on the etched side, and the light receiving surface S3 is formed to be approximately the same size as the CCD 32.
- the thickness of the back-illuminated solid-state imaging device 30 is, for example, about 10 to LOO ⁇ m for the thinned portion 33 and about 300 to 600 ⁇ m for the outer edge 34 of the thinned portion 33.
- the thinned part 33 The outer edge portion 34 is a portion thicker than the thinned portion 33 around the thinned portion 33 of the back-illuminated solid-state imaging device 30.
- a terminal electrode 35 is formed on the peripheral edge on the surface S1 of the back-illuminated solid-state imaging device 30.
- the terminal electrode 35 is arranged so as to be input / output interchangeable between a front-illuminated type and a back-illuminated type as shown in FIG. Further, the terminal electrode 35 is electrically connected to the CCD 32 by wiring (not shown). Further, the entire back surface S2 of the back-illuminated solid-state imaging device 30 is covered with an accumulation layer (not shown) including the light receiving surface S3.
- the accumulation layer has the same conductivity type as that of the back-illuminated solid-state image sensor 30, but its impurity concentration is higher than that of the back-illuminated solid-state image sensor 30.
- the back-illuminated solid-state imaging device 30 is mounted on the wiring board 1 by bump bonding.
- the wiring substrate 1 is disposed opposite to the front surface S1 side of the back-illuminated solid-state imaging device 30.
- the back-illuminated solid-state imaging device 30 is adjusted in position by the alignment mark 14 of the wiring board 1 and arranged in the planned arrangement area la.
- the terminal electrode 35 formed on the surface S1 of the back-illuminated solid-state imaging device 30 and the first electrode pad 12 formed in the planned placement area la of the wiring board 1 are respectively connected via the conductive bumps 31. Connected.
- the wiring board 1 is provided with a package (not shown) having an opening at the center so as to cover the back-illuminated solid-state imaging device 30.
- a window member (not shown) is fitted in the opening of the cage.
- the back-illuminated solid-state imaging device 3 can be provided at low cost.
- FIG. 6 is a plan view showing another embodiment of the solid-state imaging device of the present invention.
- FIG. 7 is a cross-sectional view taken along the line VII-VII of the solid-state imaging device in FIG.
- the front-illuminated solid-state imaging device 4 includes a wiring board 1, a front-illuminated solid-state imaging device 40, a conductive wire 41, and an electrical insulating layer 42.
- the front-illuminated solid-state imaging device 4 includes a front-illuminated solid-state image sensor having an input / output compatible terminal electrode arrangement shown in FIG. 3 on the wiring board according to the above-described embodiment. It is the arranged device. [0038]
- the front-illuminated solid-state image sensor 40 is formed with a thinned portion.
- the back-illuminated solid-state image sensor 30 is different from the back-illuminated solid-state image sensor 30 in other respects. is there.
- the front-illuminated solid-state imaging device 40 has a rectangular shape in plan view having a size corresponding to the planned layout area la of the wiring board 1.
- a CCD 43 is formed as a light detection part on a part of the surface layer on the surface S1 side.
- the CCD 43 has a plurality of pixels arranged two-dimensionally, for example, 1024 pixels ⁇ 128 pixels.
- the CCD 43 has a vertical charge transfer unit 431 and horizontal charge transfer units 432 and 433 as shown in FIG.
- the thickness of the front-illuminated solid-state imaging device 40 is, for example, about 300 to 600 ⁇ m.
- a terminal electrode 44 is formed on the periphery of the surface S1 of the surface incident solid-state imaging device 40 on the surface S1.
- the terminal electrode 44 is disposed so as to be input / output compatible with a front-illuminated type and a back-illuminated type as shown in FIG.
- the terminal electrode 44 is electrically connected to the CCD 43 by wiring (not shown).
- the front-illuminated solid-state imaging device 40 is mounted on the wiring board 1 by wire bonding. That is, the wiring board 1 is disposed opposite to the back surface S2 side of the front-illuminated solid-state imaging device 40. At that time, the front-illuminated solid-state imaging device 40 is adjusted in position by the alignment mark 14 of the wiring board 1 and arranged in the planned arrangement area la.
- an electrical insulating layer 42 is formed between the front-illuminated solid-state imaging device 40 and the wiring board 1.
- the electrical insulating layer 42 has a rectangular shape in plan view and has a size enough to cover the back surface of the front-illuminated solid-state imaging device 40.
- the terminal electrode 44 formed on the surface S 1 of the front-illuminated solid-state imaging device 40 and the second electrode pad 13 formed outside the planned layout area la of the wiring board 1 are respectively connected via conductive wires 41. Get connected!
- the wiring board 1 is provided with a package (not shown) having an opening at the center so as to cover the front-illuminated solid-state imaging device 40.
- a window member (not shown) is fitted into the opening of the package.
- the front-illuminated solid-state imaging device 4 can be provided at a low cost.
- the front-illuminated solid-state image pickup device 4 since the front-illuminated solid-state image sensor 31 is mounted on the wiring board 1 via the electrical insulating layer 42, the front-illuminated solid-state image sensor 31 40 and the second electrode pad 13 provided on the wiring board 1 can be electrically insulated. Input / output signals can be reliably transmitted to the front-illuminated solid-state imaging device 4 via the wiring board 1.
- the solid-state imaging device of the present invention is not limited to the above-described embodiment.
- the back-illuminated solid-state imaging device mounted on the wiring board not only the partially thinned element as described above but also a completely thinned element may be used.
- a versatile high-density wiring board that can be mounted on either a front-illuminated or back-illuminated solid-state imaging device, and a solid-state imaging device using the wiring board. Can do.
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07768243A EP2043153A4 (en) | 2006-07-11 | 2007-07-05 | CONNECTION CHART AND SEMICONDUCTOR IMAGING DEVICE |
US12/373,106 US20090243024A1 (en) | 2006-07-11 | 2007-07-05 | Wiring board and solid-state imaging device |
CN2007800263397A CN101490844B (zh) | 2006-07-11 | 2007-07-05 | 配线基板以及固体摄像装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-190475 | 2006-07-11 | ||
JP2006190475A JP4451864B2 (ja) | 2006-07-11 | 2006-07-11 | 配線基板及び固体撮像装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008007613A1 true WO2008007613A1 (en) | 2008-01-17 |
Family
ID=38923174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/063494 WO2008007613A1 (en) | 2006-07-11 | 2007-07-05 | Wiring board and solid-state imaging device |
Country Status (6)
Country | Link |
---|---|
US (1) | US20090243024A1 (ja) |
EP (1) | EP2043153A4 (ja) |
JP (1) | JP4451864B2 (ja) |
KR (1) | KR20090029189A (ja) |
CN (1) | CN101490844B (ja) |
WO (1) | WO2008007613A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013035410A1 (ja) * | 2011-09-05 | 2013-03-14 | 浜松ホトニクス株式会社 | 固体撮像素子及び固体撮像素子の実装構造 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4421589B2 (ja) * | 2006-10-10 | 2010-02-24 | 浜松ホトニクス株式会社 | 光検出装置 |
JP4490406B2 (ja) * | 2006-10-11 | 2010-06-23 | 浜松ホトニクス株式会社 | 固体撮像装置 |
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- 2007-07-05 US US12/373,106 patent/US20090243024A1/en not_active Abandoned
- 2007-07-05 EP EP07768243A patent/EP2043153A4/en not_active Withdrawn
- 2007-07-05 CN CN2007800263397A patent/CN101490844B/zh active Active
- 2007-07-05 KR KR1020087027765A patent/KR20090029189A/ko not_active Application Discontinuation
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WO2013035410A1 (ja) * | 2011-09-05 | 2013-03-14 | 浜松ホトニクス株式会社 | 固体撮像素子及び固体撮像素子の実装構造 |
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Also Published As
Publication number | Publication date |
---|---|
CN101490844A (zh) | 2009-07-22 |
CN101490844B (zh) | 2011-02-16 |
US20090243024A1 (en) | 2009-10-01 |
KR20090029189A (ko) | 2009-03-20 |
JP4451864B2 (ja) | 2010-04-14 |
EP2043153A1 (en) | 2009-04-01 |
EP2043153A4 (en) | 2012-08-15 |
JP2008021724A (ja) | 2008-01-31 |
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