WO2008004301A1 - Unité de transfert de données, unité de traitement, et procédé de transfert de données - Google Patents

Unité de transfert de données, unité de traitement, et procédé de transfert de données Download PDF

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Publication number
WO2008004301A1
WO2008004301A1 PCT/JP2006/313498 JP2006313498W WO2008004301A1 WO 2008004301 A1 WO2008004301 A1 WO 2008004301A1 JP 2006313498 W JP2006313498 W JP 2006313498W WO 2008004301 A1 WO2008004301 A1 WO 2008004301A1
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WIPO (PCT)
Prior art keywords
data
frame
unit
received
buffer
Prior art date
Application number
PCT/JP2006/313498
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English (en)
Japanese (ja)
Inventor
Yuuji Konno
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/313498 priority Critical patent/WO2008004301A1/fr
Publication of WO2008004301A1 publication Critical patent/WO2008004301A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9021—Plurality of buffers per packet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/26—Flow control; Congestion control using explicit feedback to the source, e.g. choke packets
    • H04L47/266—Stopping or restarting the source, e.g. X-on or X-off
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/505—Corrective measures
    • H04L49/506—Backpressure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Definitions

  • Data transfer device arithmetic processing device, and data transfer method
  • the present invention relates to a technique for controlling a frame buffer buffer in a data transfer apparatus such as a cross burst used for inter-CPU communication.
  • a fixed threshold value is set to prevent overflow, and the remaining data amount in the buffer reaches the threshold value.
  • a transmission stop request (back pressure) is output to the frame source. Note that the upper limit of the remaining capacity of the buffer determined by the buffer threshold needs to be secured more than the maximum length of the frame in order to prevent overflow of the noffer.
  • Patent Document 1 discloses a packet switch that executes back pressure for restricting packet input.
  • Patent Document 2 discloses a packet buffer management device that increases the throughput by efficiently using a memory of a nother by processing a received packet by dividing it into a fixed length.
  • FIG. 1 is a diagram showing how threshold values are set by a conventional frame buffering buffer and transmission stop request issuance timing. This figure shows the case where the length of one received frame can be 2 to 4 units.
  • “S” in the frame is The beginning of the frame
  • "E” is the end of the frame
  • nothing is written indicates the frame data.
  • a fixed threshold value 11 is set in the FIFO buffer 10.
  • the threshold value 11 is set so that the remaining frame of the FIFO buffer 10 is the maximum frame length that can be input (in this figure, the length is the size of the frame 12, ie, 4 units).
  • FIG. 1 (a) shows a state where a frame 12 having a long frame length is stored in the FIFO buffer 10.
  • FIG. 1 (b) is a diagram showing a state after the data amount in the FIFO buffer 10 reaches the threshold 11 in FIG. 1 (a).
  • One frame is stored in the FIFO buffer 10 until the transmission stop request is notified to the data transmission source and the frame transmission stops. If the frame capacity stored at this time is a long frame (long frame) 13a, the remaining capacity of the FIFO buffer 10 is exhausted, and further frame reception processing cannot be performed. However, if the frame to be stored is a short frame (short frame) 13b, the remaining amount of the FIFO buffer 10 remains, and frame reception processing is still possible.
  • the data transfer apparatus in FIG. 2 transmits a frame length detection unit 22, a frame buffer buffer 23, a buffer read control unit 25, and a buffer remaining amount notification signal 28 in the order in which frames 27 to 27 are transmitted. It consists of a transmission stop request unit 26 that notifies 21.
  • the frame length detection unit 22 detects the frame length of the frame from the header portion of the reception frame 27.
  • the frame buffer buffer 23 is a memory composed of a FIFO having a function of temporarily buffering a frame.
  • the read control unit 25 is a control block that reads a koffer based on a request from a subsequent frame processing unit (not shown).
  • the transmission stop request unit 26 issues a transmission stop request 28 to the transmission source when the amount of data in the frame buffer buffer 23 reaches a threshold value.
  • the frame 27 transmitted from the transmission source 21 is accumulated in the frame buffer 23 via the frame length detector 22, and sequentially from the frame buffer 23 under the control of the read controller 25. It is read and sent to destination 24.
  • the frame length detection unit 22 also detects the data length of the frame in the information power in the header part of the transmission frame from the data transmission source 21 and notifies the transmission stop request generation unit 26 of this. Based on this, the transmission stop request generating unit 26 changes the value of the threshold value Th set for itself.
  • the threshold value Th of the frame buffer 23 is changed based on the detection result of the frame length detector 22.
  • the threshold Th is changed by taking a low threshold Thl so that the remaining amount of the frame buffer 23 increases when the frame length is long, and conversely when the frame length is short
  • the buffer 23 is changed to take a high value threshold Th2 so that the remaining amount of the buffer 23 becomes small.
  • the threshold value Th is changed so that the remaining amount of the frame buffer 23 becomes an appropriate value. Therefore, the usage rate of the frame buffer 23 is increased, and the frame transmission of the cross burst switch is performed. Processing capacity can be improved.
  • the frame length detection unit 22 constantly monitors the size of the frame input to the frame buffer buffer 23. Further, the transmission stop request generator 26 resets the frame buffer buffer 23. Always monitor the remaining buffer notification 30 generated by the Z write pointer. When this remaining amount reaches the threshold value Th held in the transmission stop request generation unit 22, a transmission stop request 28 is issued to the data transmission source 21.
  • the transmission stop request generation unit 26 receives the frame length notification 29 from the frame length detection unit 22, and dynamically changes the threshold value set to itself according to this frame length.
  • the threshold value of the frame buffer buffer 23 is dynamically changed based on the received frame length. That is, in the frame length detection unit 22, when the received frame length is long, the threshold of the frame buffer 23 is set low, and when the frame length is short, the threshold is set high so that the usage rate of the frame buffer 23 is increased. I give you.
  • the frame buffer is used when the processing for preferentially transferring the frame with the short frame length is performed.
  • the buffer 23 is close to the threshold, for example, when short frames are input continuously, long frames are not processed! Resulting in.
  • FIG. 3 is a diagram showing this live block state.
  • the threshold value of the frame buffer 41 is increased from Thl to Th2, and the short frame 43 is preferentially written to the buffer.
  • the short frame 43 is continuously input when the remaining amount of the frame buffer 23 is near the threshold value, the live block state is generated because even the long frame 42 is not processed.
  • Patent Document 1 JP 2000-22718
  • Patent Document 2 Japanese Patent Laid-Open No. 2000-316024
  • An object of the present invention is to provide a data transfer device, an arithmetic processing device, and a data transfer method capable of increasing the usage rate of a noffer without generating a live block state for a long frame.
  • a data transfer device is a data transfer device that performs data transfer by holding received data, and includes a data length detection unit, a data buffer unit, a data division unit, And a transmission stop request generator.
  • the data length detection unit detects the data length of the received data.
  • the data buffer unit stores received data.
  • the data dividing unit divides the received data and outputs the divided received data to the data buffer unit when the amount of data held by the data transfer device exceeds a predetermined value set in advance.
  • the transmission stop request generation unit outputs a transmission stop request based on the amount of data held by the data transfer apparatus.
  • the data amount held by the data transfer device is based on the data length of the received data detected by the data length detector and the data amount of the data buffer unit after storing the received data. Also good.
  • the data amount held by the data transfer device is based on the data length of the received data detected by the data length detector and the data amount of the data buffer unit before storing the received data It is good.
  • a data length detection unit that detects the data length of received data, a data buffer unit that stores received data, and a data amount stored in the data buffer unit When a preset threshold value is exceeded, the received data is divided and a data dividing unit that outputs the divided received data to the data buffer unit; the data length detected by the data length detecting unit; And a transmission stop request generation unit that outputs a transmission stop request based on the stored data amount of the data buffer unit.
  • the data transfer device further includes a data reproduction unit that merges data output from the data buffer unit, and outputs the divided data stored in the data buffer unit. May be configured to restore the data divided by the data reproduction unit to the data before division and output the data.
  • the present invention also includes an arithmetic processing device and a data transfer method within its scope.
  • the threshold value of the noffer is dynamically changed based on the frame length input to the data buffer unit, and the storage amount of the data buffer unit can always be kept at the maximum. As a result, the frequency of transmission stop requests (back pressure) decreases, and the frame processing performance can be improved.
  • the threshold of the frame buffer is set high by processing a long frame as a short frame. The rate goes up.
  • FIG. 1 is a diagram showing how thresholds are set by a conventional frame buffer and the timing for issuing a transmission stop request.
  • FIG. 2 is a diagram showing a frame transfer method using a FIFO frame buffer buffer whose threshold value is dynamically changed.
  • FIG. 3 is a diagram showing a live block state.
  • FIG. 4 is a diagram showing a concept of processing at the time of frame storage Z reading in the frame buffer buffer in the present embodiment.
  • FIG. 5 is a diagram showing the overall configuration of the system of the present embodiment.
  • FIG. 6 is a block diagram showing a configuration of a cross burst (XB).
  • FIG. 7 is a diagram showing a frame transfer method by a frame buffer buffer in the present embodiment.
  • FIG. 8 is a conceptual diagram showing how a frame length is detected by a frame length detector.
  • FIG. 10 is a diagram showing a detailed example of frame division processing performed by the frame division unit in the present embodiment.
  • FIG. 11 is a diagram showing a detailed example of frame playback processing performed by the frame playback unit in the present embodiment.
  • FIG. 12 is a flowchart showing an operation example of the system controller unit of the data transmission source.
  • FIG. 13 is a flowchart showing an operation example of the cross burst switch.
  • FIG. 14 is a flowchart showing an operation example of a read control unit in the cross burst.
  • FIG. 4 is a diagram showing a concept of processing at the time of frame storage Z reading in the frame buffer buffer in the present embodiment.
  • the threshold value is dynamically changed according to the length of the received frame, as in the configuration shown in FIG.
  • the threshold of the frame buffer 51 when the threshold of the frame buffer 51 is set to the threshold Th 1 of the short frame, and the remaining amount of the frame buffer 51 becomes close to the threshold Th2 (for example, the thresholds Thl and Th2).
  • the long frame 52 is temporarily converted into short frames 53a and 53b and stored in the frame buffer 51.
  • the frames 53a and 53b read from the frame buffer 51 are reproduced as the original long frame 52 and transmitted to the transmission destination.
  • a live block is prevented from occurring, and a long frame 52 is also processed.
  • the long frame 52 is input to the frame buffer buffer 51 as the short frames 53a and 53b, it is possible to input a frame with the frame buffer buffer 51 set to the short frame threshold value Th2, thereby increasing the buffer usage rate. be able to.
  • FIG. 5 is a diagram showing the overall configuration of the system of this embodiment.
  • the casing 61 and the expansion casing 62 have a plurality of system boats SB63-0 to 63-15.
  • Each system board (SB) 63-0 to 63-15 includes a plurality of CPU sections 65 and one system controller (SC) section 66, and between each system board 63-0 to 63-15, Connected by multiple crossbar switches (XB) 64-1 to 64-4.
  • SC system controller
  • the system board 63-0 includes four CPU sections 65, ie, CPU sections 65-0 to 65-3, which are connected to the system controller section 66-0 and are connected to the system board 6-0.
  • 3-4 also includes four CPU sections 65-16 to 65-19, which are connected to the system controller section 66-4.
  • Each CPU unit 65 on the system board 63 is a CPU core having a frame transmission / reception buffer, performs various calculations based on a program in a memory (not shown), and is on a different system board 63. Exchanges data with the CPU part 65
  • the system controller 66 controls the entire system board 63.
  • the system controller 66 handles the transmission request from the CPU 65, and the system controller 66 is used for communication between the CPUs 5.
  • a communication request from the CPU unit 65 is passed to the cross burst 64, and transmission data is received.
  • the system controller 66 receives a transmission stop request (back pressure) from the cross burst 64, it stops frame transmission to the cross burst 64.
  • Each system board 63—0 to 63—15 is connected via a cross burst (XB) 64—1 to 64—4, and communication between the CPU units 65 across the system board 63 is as follows. This is done via the crossbar switches 64-1 to 64-4.
  • XB cross burst
  • FIG. 6 is a block diagram showing a configuration of the cross burst (XB) 64 of FIG. The figure only shows the configuration centered on the FIFO buffer.
  • the cross burst 70 shown in the figure includes a frame length detector 72, a transmission stop request generator 73, It has a frame decomposing unit 74, a first FIFO buffer (FIF01) 75, a second FIFO buffer (FIFO 2) 76, a read control unit 77, a frame reproduction unit 78, and a frame processing unit 79.
  • the frame length detection unit 72 receives the transmission source power from the data Z header identification signal (TAG) and the data bus signal (DATA-BUS) received from the system controller (SC) 71 of the transmission source. The frame length of the frame is detected and notified to the transmission stop request generator 73. The frame data and tag information to which the data Z header identification signal (TAG) and the data bus signal (DATA_BUS) are also input are input to the frame decomposition unit 74 via the frame length detection unit 72.
  • TAG data Z header identification signal
  • DATA-BUS data bus signal
  • the transmission stop request generation unit 73 notifies the remaining amount of the buffer generated by the frame length notification signal (L EN) from the frame length detection unit 72 and the read / write pointer notified from the FIFO buffer 16.
  • the threshold values of the first FIFO buffer 75 and the second FIFO buffer are determined from the signal (RWP). Then, it is determined whether or not to send a frame transmission stop request to this threshold power transmission source 71.
  • a transmission stop request signal (BP) is transmitted to the system controller 71 of the frame transmission source.
  • the frame decomposing unit 74 writes the frame header information into the first FIFO buffer (FIFOl) 75 using the buffer input data WDT1 and the buffer write instruction signal WEN1, and the second FIFO buffer (FIF02) 76 Is written with the buffer input data WDT2 and the buffer write instruction signal WEN2.
  • the frame decomposing unit 74 divides the frame from the frame length detection unit 72 into short frames.
  • the first FIFO buffer (FIFO1) 75 is a first-in first-out buffer in which header information of tag information is stored by the frame decomposing unit 74.
  • the second FIFO buffer (FIF02) 76 is a first-in first-out frame buffer buffer provided in the cross burst 70 in which frame data is stored by the frame decomposing unit 74.
  • the read control unit 77 Based on the buffer read request signal (REQ) from the frame processing unit 79 and the remaining amount notification (EMP) indicating whether or not it is empty from the first FIFO buffer 75, the read control unit 77! Buffer read instruction for first FIFO buffer 75 and second FIFO buffer 76 Signals (REN1, REN2) are output, and output control of the first FIFO buffer 75 and the second FIFO buffer 76 is performed.
  • REQ buffer read request signal
  • EMP remaining amount notification
  • the read control unit 77 When the header information of one frame or more is stored in the first FIFO buffer 75, that is, when the first FIFO buffer 75 is not empty and the EMP signal is 0, the read control unit 77 When there is a read request by the buffer read signal (REQ), read control is performed on the first FIFO buffer 75 and the second FIFO buffer 76.
  • REQ buffer read signal
  • the frame playback unit 78 reads frame data from the second FIFO buffer 76 in units of one frame, and from the header information (RDT1) read from the corresponding first FIFO buffer 75, the second FIFO buffer Whether the buffer output data (RDT2) read from 76 is a frame divided by the frame dividing unit 74 is identified. If it is a divided frame, it is merged and the frame is reproduced.
  • RDT1 header information
  • RDT2 buffer output data
  • the frame processing unit 79 receives the frame data from the frame reproduction unit 78, and controls the distribution of the frame to the transmission destination, the copy of the frame when transmitting the frame to a plurality of transmission destinations, the change of the header information, etc. After performing various processes, the destination system controller
  • the frame is output as the data Z header identification signal (TAG) and data bus signal (DATA_BUS).
  • TAG data Z header identification signal
  • DATA_BUS data bus signal
  • FIG. 7 is a diagram showing a frame transfer method by the frame buffer buffer in the present embodiment.
  • the data transfer device in the figure is described in contrast to the conventional data transfer device in FIG. 2, and components having substantially the same function are denoted by the same reference numerals.
  • the configuration in FIG. 7 is further provided with a frame division unit 81 and a frame reproduction unit 82 as compared with the configuration in FIG.
  • the threshold value of the frame buffer 23 is set to Th2, and the data is accumulated up to the vicinity of the threshold value Th2.
  • the length passed from the frame length detection unit 22 is converted into a short frame and stored in the frame buffer buffer 23. Also, if the frame reproduction unit 82 has been converted into a short frame by the frame force frame division unit 81 read from the frame buffer buffer 23, it returns this to a long frame.
  • the threshold of the frame buffer 23 when the threshold of the frame buffer 23 is set to the short frame threshold Th2, and the data in the frame buffer 23 remains close to the threshold Th2.
  • the long frame transmitted from the transmission source 21 is converted into a short frame by the frame division unit 81 and stored in the frame buffer buffer 23.
  • this frame When this frame is read from the frame buffer 23, it is converted into a long frame by the frame reproducing unit 82 and sent to the transmission destination.
  • the power for determining whether or not the received long frame is split based on only the amount of data stored in the frame buffer 23 is as follows. Whether the frame is divided or not may be determined based on the amount of data held by the entire cross burst or a part of it, not limited to the configuration!
  • a data buffer (not shown) is provided in the frame dividing unit 81 and the like in addition to the frame buffer buffer 23. Therefore, it is configured to determine whether or not the ability to divide a long frame is based on not only the data holding amount of the frame buffer 23 but also the data amount obtained by adding the data held in these buffers. Also good. In this case, whether to divide a long frame is determined based on the amount of data held in the frame buffer buffer 23 and the frame length of the received frame.
  • the received force data is determined based on the amount of data in the frame buffer 23 after storing the received data. Based on the amount of data in the previous frame buffer 23, the received length V may be determined whether to divide the frame!
  • FIG. 8 is a conceptual diagram showing how the frame length detection unit 22 detects the frame length.
  • the header portion 92 of the frame 91 transmitted from the data transmission source 21 includes information indicating the type of frame, and the frame type length can also be obtained from the type strength of this frame.
  • this frame is a frame for peer-to-peer communication, so the frame length is 4 units (1 unit is 32 bits).
  • the opcode power is '1', this frame is a broadcast communication frame, so the frame length is 2 units.
  • the position of the header portion of the frame 91 is determined from the tag information input at the same time as the frame 91.
  • the portion of the frame 91 corresponding to the portion of the tag information 94 whose tag code is 0x4 is the header portion, and the portion of the frame 91 whose tag code is 0x5 is the data portion.
  • the frame length detection unit 22 includes a decoder 93 therein, and the information in the header unit 92 of the frame input from the data transmission source 21 via the data bus signal (DATA-BUS) Using 93, decode as described above to obtain the frame length of the received frame. This is notified to the transmission stop request generator 26 as a frame length notification signal (LEN).
  • LEN frame length notification signal
  • FIG. 9 is a diagram showing the connection of the frame node that connects the system controller of the data transmission source and the cross burst switch.
  • the system controller 111 and the crossbar switch of the data transmission source have a 32-bit data bus signal (DATA—BUS) [31: 0] and a 3-bit header identification signal. (TAG) Connected by [2: 0]!
  • the data transmission source 111 inputs 112 data from the TAG and DATA-BUS simultaneously.
  • the data input from the TAG is the tag information indicating the data part whether it is the data force header part simultaneously input from the DATA_BUS.
  • the frame length detection unit 22 decodes (a part of) the data input as the header part, and detects the frame length of the received frame.
  • FIG. 10 is a diagram showing a detailed example of the frame division processing performed by the frame division unit 74 in the present embodiment.
  • the frame dividing unit 74 includes a 3-bit tag information bus corresponding to DATA-BUS [31: 0] 121 and DATA_BUS [31: 0] 121, which is a dedicated bus for 32-bit frames.
  • TAG [2: 0] 122 is connected, and frame data 123 and tag information 124 corresponding to the frame data 123 are input.
  • the frame division unit 74 transfers the frame data 123 received from the DATA-BUS [31: 0] 121 to the second FIFO buffer 76 and the tag information 124 received from the TAG [2: 0] 122.
  • the header portion 127 is stored in the first FIFO buffer 75.
  • the transmission stop request unit 73 validates the frame division instruction signal (RES) to the frame division unit 74 when the remaining amount of the second FIFO buffer 76 reaches near the threshold. Even if the remaining capacity of the second FIFO buffer 76 does not reach the threshold value, the transmission stop request unit 73 enables the frame division instruction signal (RES) to shorten the long frame to the frame division unit 74. It may be divided into frame lengths. However, in this case, since all long frames are divided, the overhead due to the division processing and the combination processing described later increases.
  • RES frame division instruction signal
  • frame dividing unit 74 increases the header portion of tag information input from TAG [2: 0] 122. For example, when dividing frame data into two, increase the header part of tag information to two. At this time, the tag code of the header part is changed, for example, from 0x4 representing the header of the normal frame to 0x7 representing the header of the divided frame.
  • the input tag information 124 since the input frame data 123 is divided into two frame data 125a and 125b, the input tag information 124 includes tag information 126 having two header parts with a tag code of 0x7. Is converted to Thereafter, the header portion of the tag information 126 is stored in the first FIFO buffer 75, and the corresponding divided frame data 125 a and 125 b are stored in the second FIFO buffer 76.
  • FIG. 11 is a diagram showing a detailed example of frame playback processing performed by the frame playback unit 78 in the present embodiment.
  • the read control unit 77 monitors the remaining amount notification (EMP) indicating whether or not it is empty from the first FIFO buffer 75. If the first FIFO buffer 75 is not empty, the buffer read instruction signals (REN1, REN2) 133 and 134 to the first FIFO buffer 75 and the second FIFO buffer 76 are output, and the first FIFO buffer 75 and the second FIFO buffer 75 are output. Control the output of the FIFO buffer 76 and read the data.
  • EMP remaining amount notification
  • the header portion of the tag is read from the first FIFO buffer 75 as the buffer output data (RD1) 131, and the output data (RD2) 135 from the second FIFO buffer 76 corresponds to the header portion.
  • Frame data is read in units of one frame.
  • the frame reproduction unit 78 receives the frame data 137 corresponding to the header portion as the frame division unit.
  • the corresponding frame data 137 is held while the header portion of the tag information 136 read from the first FIFO buffer 75 is a 0x7 tag code.
  • the long frame 139 is reproduced by combining them, and the tag
  • the tag information 138 is generated by changing the header part of the information from 0x7 to 0x4 tag code and using the other 0x7 header part as the data part.
  • the frame data 139 merged and combined is output to the frame processor 79 as buffer output data (RDT) simultaneously with the tag information 138.
  • the frame reproducing unit 78 reproduces the long frame divided into short frames by the frame dividing unit 74 into the original length and frame.
  • FIG. 12 is a flowchart showing an operation example of the system controller unit of the data transmission source.
  • the system controller checks whether the frame transmission stop request signal (BP) from the cross burst (XB) is active. If the frame transmission stop request signal (BP) is active and there is a transmission stop request (step Sl, Yes), the process returns to step SI, and the frame transmission stop request signal (BP) While active, repeat step S1.
  • BP frame transmission stop request signal
  • XB cross burst
  • the system controller unit of the data transmission source transmits the frame to the cross burst switch, and the transmission stop request is issued. And frame transmission stops.
  • FIG. 13 is a flowchart showing an example of the operation of the cross burst.
  • the cross burst first detects whether or not the received frame has a short frame strength by the frame length detection unit 72 in step S11.
  • the threshold value of the second FIFO buffer 76 is set to the high threshold value Th2 for the short frame as step S18.
  • step S19 it is checked whether or not the remaining amount of the second FIFO buffer 76 has reached the threshold value Th2. If the threshold value Th2 has not been reached (No in step S19), the process returns to step SI 1. If the threshold value Th2 has been reached (step S19, Yes), a transmission stop request is notified to the transmission source as step S20, and the process returns to step S19.
  • step S11 when the received frame is a long frame (step Sl l, No), in step S12, the second FIFO buffer 76 threshold is set to long, frame low, and threshold Thl. To do.
  • step S13 it is checked whether or not the remaining amount of the second FIFO buffer 76 has reached the threshold value. If the threshold value has not been reached (No in step S13), the process returns to step S11, and the threshold value is set. If so (step S13, Yes), configure a long frame as step S14 Judgment is made as to whether or not all the data to be performed are aligned within the frame length detector 72 (step S14, No), the process returns to step SI1 and waits until all the data is aligned. In the case of a system configuration in which it is not necessary to output frames in the order of arrival, while all the long frame data is available, these data are saved in the memory in the frame division unit 74 and the short frame is processed first. May be.
  • step S15 the transmission stop request generation unit 73 activates the frame division instruction signal (RES) to the frame decomposition unit 74 and issues a division instruction. And set the second FIFO buffer 76 threshold to the short frame threshold Th2.
  • RES frame division instruction signal
  • step S16 it is checked whether the remaining amount of the second FIFO buffer 76 has reached the threshold value Th2. If the threshold value Th2 has not been reached (No in step S16), the process returns to step SI 1. If the threshold value Th2 has been reached (step S16, Yes), a transmission stop request is notified to the transmission source as step SI7, and the process returns to step S19.
  • the threshold value of the frame buffer buffer (second FIFO buffer) can be dynamically changed, and the remaining amount of data in the buffer is near the threshold value. Since the long frame is converted to a short frame and buffered, the live block state in which the long frame is not processed can be prevented.
  • FIG. 14 is a flowchart showing an operation example of the read control unit 77 in the cross burst.
  • step S31 the buffer read request signal (REQ) from the frame processing unit 79 becomes active, and it is confirmed whether there is a data read request from the buffer. If there is no result read request (step S31, No), the process returns to step S31.
  • REQ buffer read request signal
  • step S32 one or more data is stored in the first FIFO buffer 75 from the EMP signal from the first FIFO buffer 75. If there is, that is, whether or not data for one frame or more has been accumulated in the second FIFO buffer 76, and if data for one frame or more has not been accumulated as a result (step S32, No), processing is performed. Return to step S31. [0088] If at least one frame of data is not stored in the second FIFO buffer 76 in step S32 (step S32, Yes), then in step S33, the first FIFO buffer 75 is sent to the frame playback unit 78. Then, the data is read from the second FIFO buffer 76, the process returns to step S31, and the above process is repeated thereafter.
  • the read control unit has a frame processing unit power requirement, and if data for one frame or more is accumulated in the frame buffer (second FIFO buffer), Is read in units of one frame.
  • the frame size handled by the cross burst is only two types, a long frame (4 units) and a short frame (2 units). It may be.
  • other frames are divided in accordance with the frame length of the shortest frame.
  • all the frame divisions are divided into short frames.
  • the frames may be divided into two or more types of frames.
  • a frame with a frame length of 5 units may be divided into 2 and 1 unit frames.
  • the tag code in the header part is different for the frame that becomes 1 unit after the division and the frame that becomes 2 units.

Abstract

Cette invention a pour objet une unité de transfert de données pour réaliser un transfert de données en maintenant des données reçues qui est caractérisée par le fait qu'elle comprend une section de détection de longueur de données pour détecter la longueur de données des données reçues, une section de tampon de données pour stocker les donnée reçues, une section de division de données pour diviser les données reçues et émettre les données reçues divisées à la section de tampon de données lorsque la quantité de données détenue par l'unité de transfert de données excède une valeur prédéterminée préréglée, et une section de génération de requête d'arrêt de transmission pour émettre une requête pour arrêter les transmissions conformément à la quantité de données détenues par l'unité de transfert de données.
PCT/JP2006/313498 2006-07-06 2006-07-06 Unité de transfert de données, unité de traitement, et procédé de transfert de données WO2008004301A1 (fr)

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WO2010032314A1 (fr) * 2008-09-19 2010-03-25 富士通株式会社 Système de communication, dispositif de communication, procédé de communication et programme de communication

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JPH08149159A (ja) * 1994-11-25 1996-06-07 Nec Corp データ受信装置およびデータ通信方法
JPH11234347A (ja) * 1998-02-13 1999-08-27 Nec Corp データ通信におけるバッファ管理方法および方式
JP2000022716A (ja) * 1998-07-06 2000-01-21 Nec Corp バックプレッシャ制御方法およびその装置
JP2002164914A (ja) * 2000-11-28 2002-06-07 Mitsubishi Electric Corp パケット交換装置
JP2002208938A (ja) * 2001-01-05 2002-07-26 Fujitsu Ltd パケットスイッチ
JP2006174265A (ja) * 2004-12-17 2006-06-29 Matsushita Electric Ind Co Ltd ストリームパケット受信装置

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Publication number Priority date Publication date Assignee Title
JPH08149159A (ja) * 1994-11-25 1996-06-07 Nec Corp データ受信装置およびデータ通信方法
JPH11234347A (ja) * 1998-02-13 1999-08-27 Nec Corp データ通信におけるバッファ管理方法および方式
JP2000022716A (ja) * 1998-07-06 2000-01-21 Nec Corp バックプレッシャ制御方法およびその装置
JP2002164914A (ja) * 2000-11-28 2002-06-07 Mitsubishi Electric Corp パケット交換装置
JP2002208938A (ja) * 2001-01-05 2002-07-26 Fujitsu Ltd パケットスイッチ
JP2006174265A (ja) * 2004-12-17 2006-06-29 Matsushita Electric Ind Co Ltd ストリームパケット受信装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010032314A1 (fr) * 2008-09-19 2010-03-25 富士通株式会社 Système de communication, dispositif de communication, procédé de communication et programme de communication
US8386671B2 (en) 2008-09-19 2013-02-26 Fujitsu Limited Communication system, communication device and communication method

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