Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
  • G06F3/0638—Organizing or formatting or addressing of data
  • G06F3/0643—Management of files
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
  • G06F3/061—Improving I/O performance
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
  • G06F3/0671—In-line storage system
  • G06F3/0673—Single storage device
  • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

• the present invention relates to a technique for recording data transferred from a host device in a data storage device.
• a file system called FAT is generally used as a file system applied to these data storage devices.
• FAT file system a management area called a file allocation table is secured in the data storage device in order to manage the location of recorded data.
• management information called a cluster chain indicating the structure and recording position of each file to be managed is recorded. Since the file allocation table is very important information, two file allocation tables with the same contents are generally reserved in the data storage device. Therefore, even if one of the file allocation tables is damaged, it becomes possible to read and write data normally by using the other file allocation table (Japanese Patent Laid-Open No.
• the problem to be solved by the present invention is to improve data writing efficiency in a data storage device that records a plurality of pieces of management information having the same contents. Based on the above problems, a data storage device which is one embodiment of the present invention is provided.
• a data storage device for storing data transferred from a host device, having a data area in which the data is recorded, first management information for managing the data, and contents similar to the management information
• a storage device having a management area in which second management information is recorded;
• the data storage device having the above configuration when one management information of the first management information and the second management information having the same contents is received from the host device, the reception of the other management information is not waited for.
• the management information is recorded in the management area of the storage device as first management information and second management information.
• the management information recording unit when the management information recording unit receives the other management information, the management information recording unit does not record the management information in the management area, and indicates that the recording is completed. Means for notifying the host device may be provided. According to such a configuration, it is possible to immediately respond to the host device that the second management information has been written. As a result, the host device is immediately released from the management information writing process, and can immediately start another process (for example, data writing).
• the management information recording unit may record the first management information and the second management information at consecutive positions in the management area. With such a configuration, it is possible to easily write two pieces of management information together in a storage device by one writing process. As a result, write efficiency can be improved.
• the data storage device includes a plurality of the storage devices, and the management information recording unit records the first management information in a single storage device, and the second storage device The management information may be recorded in another storage device.
• the management information recording unit records the first management information in a single storage device, and the second storage device The management information may be recorded in another storage device.
• the data recording unit may record the data in a distributed manner in each storage device. According to such a configuration, data received from the host device can be distributed to a plurality of storage devices and simultaneously recorded in parallel. Therefore, the write efficiency can be further improved. In the data storage device having the above configuration, the data recording unit may record the data in one storage device and record correction data for correcting the data in another storage device. W
• the data recording unit may record ECC data obtained by Hamming encoding the data as the correction data. According to such a configuration, error checking and error correction can be performed using ECC data when reading data. In the data storage device configured as described above, the data recording unit may record data having the same content as the data as the correction data. According to such a configuration, it is possible to easily check errors only by comparing the data to be read with the correction data. Even if an error occurs in one of the data, normal data can be read by using the data on the side where no error has occurred.
• the management information may be data recorded in a file allocation table in a FAT file system.
• file writing efficiency is improved in a FAT file system that uses two file allocation tables as standard.
• the storage device may be a non-volatile semiconductor memory. According to such a configuration, a small data storage device excellent in portability can be provided.
• the nonvolatile semiconductor memory for example, NAND type or NOR type flash memory, EEPROM, or DRAM backed up can be used.
• a hard disk drive can be adopted as the storage device.
• the host device and the data storage device may be connected by a USB interface.
• the data storage device of the present invention can be easily used by simply connecting the data storage device of the present invention to a USB port prepared in a host device such as a computer. Therefore, user convenience can be improved.
• the PCMC IA interface is connected via a serial ATA interface, IEEE 1394 interface, various memory interfaces used in SD memory cards and CompactFlash (registered trademark), etc. It is good also as what is done.
• the present invention can also be configured as a data storage method in which the data storage device stores data transferred from the host device.
• FIG. 1 is an explanatory diagram showing a schematic configuration of a data storage device as a first embodiment.
• FIG. 2 is an explanatory diagram showing the data structure of the data storage device.
• FIG. 3 is an explanatory diagram showing the correspondence between the FAT 1 and 2 areas and the FAT 3 area and the outline of the read / write operation for the FAT 3 area.
• FIG. 4 is an explanatory diagram showing an outline of the operation of the data storage device together with the operation of the host device.
• FIG. 5 is a flowchart of the main process.
• FIG. 6 is a flowchart of the pointer setting process.
• FIG. 7 is a flowchart of the rice processing.
• FIG. 8 is a flowchart of the read process.
• FIG. 9 is an explanatory diagram showing a schematic configuration of a data storage device according to the second embodiment.
• FIG. 10 is an explanatory diagram showing a data structure in the second embodiment.
• FIG. 11 is an explanatory diagram showing a data structure in the third embodiment.
• FIG. 1 is an explanatory diagram showing a schematic configuration of a data storage device 10 as the first embodiment.
• the data storage device 10 of the present embodiment is configured by a USB connector 110, a USB control circuit 120, a flash controller 130, and a flash memory FL.
• the USB connector 110 is exposed from the housing of the data storage device 10 (broken line portion in the figure), and is connected to the USB interface provided in a host device such as a personal computer or a printer.
• the USB control circuit 120 is connected to the US B connector 110 and the flash controller 130.
• the USB control circuit 120 is a circuit that operates the data storage device 10 as a USB mass storage class device, and is a circuit that controls communication with the host device based on the USB protocol.
• the USB control circuit 120 further has a function of converting a US B command received from the host device into an ATA command, and converting data and status received from the flash controller 130 into US B data.
• the ATA command is a command standardized by AN SI (American National Standard Institute).
• various data storage such as a hard disk and a PC card type memory is possible.
• the flash controller 130 is an integrated circuit that interprets the ATA command transferred from the USB control circuit 120 and controls reading / writing of data from / to the flash memory FL.
• the flash controller 130 includes a CPU, ROM, RAM, and the like in order to perform such control.
• ROM a program for controlling the operation of the data storage device 10 is recorded.
• the CPU controls the overall operation of the data storage device 10 by executing this program while using RAM as a work area.
• the flash controller 130 includes a register 1 35, and various address pointers are stored in the register 1 35.
• the flash controller 130 has a function of performing an address conversion of the FAT area, which will be described later, by referring to the address pointer, and efficiently reading and writing the FAT area. Details of this function will be described later. FIG.
• FIG. 2 is an explanatory diagram showing the data structure of the data storage device 10.
• each area as shown on the left side of the figure is generated by the format process based on the FAT file system from the host device.
• the master boot record area hereinafter referred to as the “MBR area”
• the bioparameter block area hereinafter referred to as the ⁇ area
• FAT 1 area FAT 2 An area
• FAT 2 An area FAT 1 area
• FAT 2 An area a root directory area
• a user data area are created.
• the MBR area is the area that is read first when the host device is connected.
• the Information such as bootstrap code and partition table (hereinafter referred to as “MBR information”) is recorded in this area.
• the partition table records information such as the number of partitions created, the start and end sectors of each partition, the offset, and the total number of sectors. In this example, it is assumed that only one partition is created.
• the BPB area is recorded in the first sector of each partition, and information such as the partition format, the number of sectors, and the number of FATs (hereinafter referred to as “BPB information”) is recorded.
• management information representing the location of each file recorded in the user data area and the connection state of clusters constituting the file is recorded. Such management information is usually called cluster information.
• cluster information is usually called cluster information.
• the same management information is recorded in the FAT 1 area and FAT 2 area in order to improve data reliability.
• the file name, extension, and attributes of the file recorded in the user data area and the first cluster number constituting the file are recorded.
• the data storage device 10 performs address conversion on the FAT 1 area and the FAT 2 area among the areas described above by the action of the flash controller 1 30, and these areas are combined into the FAT 3 area as shown on the right side of the figure. Manage as an area.
• the host device recognizes each area as described above by the address map as shown on the left side of FIG. 2, and actually the address as shown on the side of the figure.
• Each area is secured in the reflash memory FL by the Les Map.
• the FAT 1 area, FAT 2 area, and FAT 3 area may be collectively referred to as “FAT area”.
• the flash controller 130 uses the address pointers AP1 to AP3 shown in FIG. 2 when performing address conversion of the FAT area. These address pointers are stored in register 1 35 in flash controller 1 30.
• the address pointer AP 1 indicates the start address Ac of the FAT 1 area
• the address pointer AP 2 indicates the start address Ad of the FAT 2 area.
• the address pointer AP3 indicates the head address Ae of the root directory area.
• the flash controller 1 30 refers to these address pointers, and when the access destination from the host device is the FAT 1 area or the FAT 2 area, performs address conversion, and converts the FAT 3 in the flash memory FL. Read and write to the area.
• FIG. 3 is an explanatory diagram showing the correspondence between the FAT 1 and 2 areas and the FAT 3 area and the outline of the read / write operation for the FAT 3 area.
• the left side of the figure shows the FAT 1 area and the FAT 2 area as seen from the host device, and the right side of the figure shows the FAT 3 area as seen from the flash controller 130.
• one piece of management information which is a unit of FAT area recording, is represented as “# 1 j, ⁇ # 2”, and management information written to the FAT 1 area is represented as “FAT 1 # 1 J”.
• management information about the FAT 1 area is recorded in order from address A c to address A d-1 from the host device. And accessed. Also, the management information about the FAT 2 area is accessed as being recorded in order from the address A d to the address A e 11.
• the flash controller 130 alternately arranges management information about the FAT 1 area and management information about the FAT 2 area with respect to the FAT 3 area as shown on the right side of FIG. In other words, the flash controller 1 30 performs address conversion according to the following formula (1) when the FAT 1 area is accessed, and when the FAT 2 area is accessed, the following formula (2) Perform address translation according to. However, in the following formula, the address accessed from the host device is represented as AD1, and the converted address is represented as AD2.
• AD 2 AP 1 +2 * (AD 1—AP 1) (1)
• the flash controller 1 30 is, for example, “FAT 1 # from the host device to the FAT 1 area shown on the left side of When the management information writing instruction “1” is received, this management information is written to the address converted by the above formula (1) in the FAT 3 area shown on the right side of FIG. Further, management information having the same contents as this management information is written as FAT 2 area management information (FAT 2 # 1) to the next address adjacent to the address. As described above, in the FAT file system, the same management information is normally written in the FAT 1 area and the FAT 2 area.
• management information about FAT 1 and management information about FAT 2 are written in a continuous address, so that management information can be written at high speed.
• FIG. 4 is an explanatory diagram showing an outline of the operation of the data storage device 10 together with the operation of the host device.
• the host device In order for the host device to write a file to the data storage device 10, roughly, (a) write management information to the FAT 1 area, (b) write management information to the FAT 2 area, (c ) The procedure of writing a file entity to the user data area is executed.
• Figure 4 shows this sequence.
• the host device first instructs the data storage device 10 to write management information of the file to be written to the FA area 1 (step S 100). Management information is transmitted from the host device to the data storage device 10 at the same time as this instruction.
• the flash controller 1 30 of the data storage device 10 Upon receiving the above instruction and management information, the flash controller 1 30 of the data storage device 10 writes the management information to the address in the FAT3 area corresponding to the address in the designated FAT 1 area, and then continuously. Information that copies the management information is written to the address (step S 1 1 0).
• step S 110 A specific example of the process in step S 110 will be described with reference to FIG. Assuming that the host device is instructed to write the information shown as “FAT 1 # 1 J” as the management information to the address Ac in the FAT 1 area, the data storage device 10 will have the FAT 3 corresponding to that address. Write “FAT 1 # 1” to address A c in the area. Further, information having the same contents as the information is written as “F AT 2 # 1” in the next address A c + 1.
• F AT 2 # 1 is information that is originally written at the start address Ad of the FAT 2 area. Therefore, the management information written to the FAT 1 area and FAT 2 area is put together in the FAT 3 area at the same time. Will be written. In other words, the FAT file system uses the fact that the same data is recorded in the FAT 1 area and the FAT 2 area. When the management information is written, the management information for the FAT 2 area is written together without waiting for an instruction from the host device.
• the flash controller 1 30 When writing to the FAT 3 area is completed (step S 1 1 5), the flash controller 1 30 returns a write completion notification indicating that writing to the FAT 1 area is completed to the host device (step S 1). 1 20).
• the host device receives the write completion notification from the flash controller 130, it subsequently sends a management information write instruction to the FAT 2 area (step S1 30). However, as described above, at this time, the management information has already been written to the FAT 2 area in step S 110. Therefore, when the flash controller 130 receives this write instruction, it immediately returns a write completion notification to the host device (step S 140).
• the host device instructs the flash controller 130 to write the file entity (step S 150).
• the flash controller 130 writes such a file in the user data area in the flash memory FL (step S 1 60).
• the flash controller 1 30 sends a write completion notification indicating that the file writing is completed to the host device (step S 1 70).
• the data storage device 10 of this embodiment performs writing to the FAT 2 area simultaneously with writing to the FAT 1 area. Therefore, even if the host device issues a FAT 2 area write instruction, a notification that writing has been completed can be sent back immediately. As a result, the host device is quickly released from the writing process to the FAT 2 area, and can immediately start writing the next data.
• the user data area is written after the FAT 1 area and the FAT 2 area are written, but these may be performed in the reverse order.
• FIG. 5 is a flowchart of main processing executed by the data storage device 10. This process is a process in which the flash controller 130 starts executing at the same time when the data storage device 10 is connected to the host device and power is supplied. When this process is started, the flash controller 130 first performs a pointer setting process for setting the values of the address pointers AP1 to AP3 (step S200). Details of this pointer setting processing will be described later. Subsequently, the flash controller 130 determines whether any command is received from the host device via the USB control circuit 120 (step S 21 0).
• step S210: No If a command has not been received (step S210: No), this process is looped until the command is received. On the other hand, when a command is received (step S210: Yes), the type of the command is determined (step S220). If it is determined in step S220 that the received command is a write command for writing data (step S220: “write”), the flash controller 130 can perform write processing described later. (Step S 230). On the other hand, if it is determined that the received command is a read command for reading data (Step S 220: “Read”), a read process described later is performed (Step S 220).
• step S 240 the process returns to step S 210.
• the process according to the command received from the host device is performed until the power supply is stopped.
• FIG. 6 is a flowchart of the pointer setting process executed in step S200 of the main process described above.
• This process is a process for setting the values of address pointers AP 1 to AP 3 shown in FIG. 2 and FIG. 3 when the data storage device 10 is turned on and when the format is completed.
• the flash controller 130 reads the MBR area and the BPB area of the flash memory FL (step S300). Then, it is determined whether MBR information and BP B information have already been written in these areas (step S 3 1 0). If it is determined in step S 3 10 above that the MBR information and BPB information have not been written (step S 3 10: No), the data storage device 10 has not yet been formatted. It will be.
• the flash controller 1 30 sets the values of the address pointers AP 1 to AP 3 as follows.
• the value of the address pointer AP 1 is set as the final address A z of the flash memory FL, and the address pointers AP 2 and AP 3 are not set (step S 320).
• the host device can normally use the data storage device 10 even by a file system other than the FAT file system.
• step S320 when the value of the address pointer AP1 is set, the flash controller 130 records the value in the register 135 (step S330) and ends the pointer setting process.
• step S 3 10 If it is determined in step S 3 10 above that the MBR information and the BP B information have already been written (step S 31 0: Yes), the data storage device 10 is It has already been formatted. Therefore, the flash controller 130 obtains the first address Ac of the FAT 1 area based on information such as the partition table and the number of sectors recorded in the MBR area and the BPB area, and uses this as the value of the address pointer AP 1. (Step S 34 0). Similarly, the flash controller 130 obtains the start address Ad of the FAT 2 area and sets this value as the address pointer AP 2 (step S 350). Further, the flash controller 130 obtains the head address A e of the root directory area, and sets this as the value of the address pointer AP 3 (step S 360). Finally, the flash controller 130 records the values of the address pointers AP1 to AP3 set in this way in the register 135 (step S330), and ends the process.
• FIG. 7 is a flowchart of the write process executed in step S 230 of the main process described above.
• This write process is a process for writing data received from the host device (hereinafter referred to as “write data”) to the flash memory FL.
• the flash controller 130 When this process is executed, the flash controller 130 first analyzes the write command received from the host device via the USB control circuit 120 and analyzes the write destination address (hereinafter “write”). Address WA) (step S 400). Subsequently, the flash controller 1 30 refers to register 1 35 and It is determined whether the toad WA is an address lower than the address indicated by the address pointer AP 1 (step S 41 0). As a result of this determination, if the write address WA is an address lower than the address indicated by the address pointer AP 1 (Step S 4100: Yes), the command received from the host device is accompanied by the format process.
• write write destination address
• the flash controller 130 writes the write data as it is to the write address WA of the flash memory FL without performing any address conversion or the like (step S 420).
• MBR information and BPB information are usually written only once during formatting. Therefore, when data is written to an address lower than the address pointer AP1, the flash controller 130 determines that there is a possibility that a format process has been performed by the host device. The pointer setting process is executed (step S430). By doing so, the address pointers AP 1 to AP 3 can be appropriately set after the formatting is completed. When the pointer setting process is completed, the flash controller 130 sends a write completion notification to the host device (step S440).
• step S 410 If it is determined in step S 410 above that the write address WA is higher than the address indicated by the address pointer AP 1 (step S 410: No), the flash controller 1 30 Then, referring to the register 1 35, it is determined whether or not the write address WA is higher than the address indicated by the address pointer AP3 (step S450). As a result of this determination, the write address WA is higher than the address indicated by the address pointer AP3. If it is determined that there is a step (step S 45 0: Y es), it can be determined that the write is to the root directory area or user data area (see FIG. 2). Therefore, the flash controller 1 30 writes the write data as it is to the write address WA of the flash memory FL without performing any address conversion or the like (step S 4 60).
• the flash controller 13 30 sends a writing completion notification to the host device (step S 44 0). If it is determined in step S 4 50 above that the write address WA is lower than the address indicated by the address pointer AP 3 (step S 4 5 0: No), the write address WA is It will indicate either 1 area or FAT 2 area. Therefore, the flash controller 1 3 0 next refers to the register 1 3 5 to determine whether the write address WA is an address lower than the address indicated by the address pointer AP 2 (step S 4 7 0). As a result of this determination, if it is determined that the write address WA is an address lower than the address pointer AP 2 (step S 47 0: Y es), the write address WA indicates that it is in the FAT 1 area.
• the flash controller 1 3 0 performs address conversion according to the above equation (1) (step S 4 8 0).
• the flash controller 1 30 writes the received write data as management information to the converted address. Further, the flash controller 1 3 0 writes the same data to the next address following the address (step S 4 90). In this way, management information to be written in the FAT 1 area and FAT 2 area can be written together in the FAT 3 area.
• the rush controller 130 sends a write completion notification to the host device (step S440).
• step S 470 If it is determined in step S 470 that the write address WA is higher than the address pointer AP 2 (step S 470: No), the write address WA is an address in the FAT 2 area. Will be shown.
• the information to be written in the FAT 2 area has already been written in step S490 above. Therefore, in this case, the flash controller 130 does not write anything to the flash memory FL, and sends a write completion notification to the host device as it is (step S440).
• the line processing described above in areas other than the FAT area, the data transmitted from the host device is written as it is without performing address conversion or the like.
• data is written to the FAT 3 area by performing a predetermined address conversion only when there is an instruction to write to the FAT 1 area. At this time, since the flash controller 130 collectively writes information to be written to the FAT 2 area into the FAT 3 area, the management information can be efficiently written to the flash memory FL.
• FIG. 8 is a flowchart of the read process executed in step S240 of the main process described above.
• This read process is a process for reading data from the flash memory FL in response to a request from the host device.
• the flash controller 1 30 is connected to the host device. Analyzes the read command received from the device via the USB control circuit 120 and obtains the read destination address (hereinafter referred to as “read address RAJ”) (Step S 500). Referring to register 1 35, it is determined whether read address RA is higher than the address indicated by address pointer AP 1 and lower than the address indicated by address pointer AP 3 (step S 51 0).
• Step S 51 0: No If the result of this determination is that the read address RA is lower than the address pointer AP 1 or higher than the address pointer AP 3 (step S 51 0: No), the read address RA is FAT Therefore, the flash controller 1 30 reads the data from the read address RA as it is. (Step S520) and transfer the read data to the host device (Step S530) In Step S510 above, the read address RA is higher than the address indicated by the address pointer AP1, and the address pointer AP3 If the address is lower than the address indicated by (step S 51 0: Yes), the read address RA indicates the address in the FAT 1 area or FAT 2 area (see Figure 2).
• the flash controller 130 determines whether or not the read address RA is higher than the address indicated by the address pointer AP 2 (step S540) As a result of the determination, the read address RA becomes the address pointer AP. If it is determined that the address is lower than 2 (step S 540: No), the read address RA is the address in the FAT 1 area. Become. Therefore, the flash controller 1 30 performs Adoresu converted by the above formula (1) (step S 550), reads data from the converted address (step S 520) . By doing so, the flash controller 130 can appropriately read management information about the FAT 1 area from the FAT 3 area. When the flash controller 1 30 reads data from the FAT3 area, it transfers it to the host device (step S530).
• step S540 determines whether the read address 8 is higher than the address indicated by the address pointer AP2 (step S540: Yes). If it is determined in step S540 that the read address 8 is higher than the address indicated by the address pointer AP2 (step S540: Yes), the read address RA is in the FAT 2 area. Address. Therefore, the flash controller 130 performs address conversion according to the above equation (2) (step S560), and reads data from the converted address (step S520). By doing so, the flash controller 130 can appropriately read management information about the FAT 2 area from the FAT 3 area. When the flash controller 130 reads data from the FAT 3 area, it transfers it to the host device (step S530). According to the read processing described above, the flash controller 130 can read data from an area other than the FAT area as it is and transfer it to the host. Also, when reading from the FAT 1 area or FAT 2 area, the flash controller 130 reads the management information from the FAT 3 area appropriately by performing address conversion, and Can be transferred to.
• the data storage device 10 also performs data writing to the FAT 2 area when the host device instructs to write data to the FAT 1 area. Therefore, data on the FAT 2 area from the host device Even if there is an instruction to write, a notification that writing has been completed can be sent back immediately.
• management information about the FAT 1 area and the FAT 2 area is collectively written in the adjacent addresses in the FAT 3 area in the flash memory FL. Therefore, data can be written efficiently, and the processing speed can be improved.
• the data storage device 10 of the present embodiment employs a flash memory having a relatively large data write unit as a storage device, so that it is easy to write two adjacent data together in one write operation. Become. As a result, the processing speed can be greatly improved.
• FIG. 9 is an explanatory diagram showing a schematic configuration of the data storage device 10 b as the second embodiment.
• the data storage device 1 Ob of this embodiment includes a USB connector 110, a USB control circuit 120, and a flash controller 130, as in the first embodiment.
• Two flash memories FLa and FLb are provided.
• FIG. 10 is an explanatory diagram showing the data structure of the data storage device 10 b. The left side of FIG. 10 shows an address map of the data storage device 10 0 b as viewed from the host device.
• the address maps of two flash memories F and a and FL b are shown together.
• the addresses forming the address space are (1) flash memory FL a, (2) Assume that flash memory FL b is allocated alternately in this order.
• the first address of the MBR area exists in the flash memory FL a and the second address exists in the flash memory FL b.
• the third address is present in the flash memory FLa, and the fourth address is present in the flash memory FLb.
• the data storage device 10 b can write data to two flash memories in parallel (simultaneously).
• the data storage device 1 Ob includes two flash memories FL a 'FLI? Since the bus width is substantially doubled, the data can be read and written at high speed if data is written in parallel (simultaneously) as described above.
• a FAT 1 area is secured on the flash memory FL a side
• a FAT 2 area is secured on the flash memory FL b side. Therefore, in this embodiment, when there is an instruction to write data to the FAT 1 area from the host device, the flash controller 130 writes the data to the FAT 1 area of the flash memory FL a and the same.
• the flash memory FLa or the flash memory FLb is appropriately read / written.
• the same management information is written in two consecutive addresses in the FAT 3 area in step S490 of the write process shown in FIG.
• the same management information is written in parallel to the FAT 1 area of the memory FL a and the FAT 2 area of the flash memory FL b.
• the address conversion in step S 550 of the read processing in FIG. 8 the address conversion to the FAT 1 area of the flash memory FL a is performed, and in the address conversion in step S 560, the address to the FAT 2 area of the flash memory FLb is performed. Perform each conversion.
• FIG. “I 1 is an explanatory diagram showing a data structure of a data storage device I 0 b in the third embodiment.
• the left side of Fig. 11 shows the address map of the data storage device 1 Ob as seen from the host device.
• the right side of Figure 1 1 shows two flash memories F An address map of L a and FL b is shown.
• the same data is written in the flash memory FL a and the flash memory FL b.
• the FAT area the FAT 1 area is secured in the flash memory FL a and the FAT 2 area is secured in the flash memory FL b as in the second embodiment.
• the writing efficiency for the FAT area can be improved.
• the address map viewed from the host side and the address system viewed from the flash controller 130 are the same. Therefore, data can be read and written in areas other than FAT 2 without performing address conversion. As a result, the processing efficiency can be improved.
• the area shown as "NU LL" is an area where the FAT 2 area should be reserved, and is not an area directly recognized by the host device. Become.
• this NU LL area can be used as a user data area by performing a predetermined address conversion that links this NU LL area to the user data area.
• the same data is written to the flash memory FL a and the flash memory FL b.
• the ECC generated from the data written to the flash memory FL a is stored in the flash memory FL b.
• Data may be written. With such a configuration, it is possible to easily perform error checking and error correction written to the flash memory FL a based on the ECC data written to the flash memory FL b, so the stored data It becomes possible to improve the reliability of the.
• the data storage device 10 is provided with a flash memory as a storage device.
• a flash memory as a storage device.
• another storage device such as a hard disk drive may be provided.
• the data storage device 10 is formatted in the FAT format.
• the format of the format is not limited to this, and may be formatted by another format in which multiple pieces of management information with the same contents are written.
• the host device and the data storage device 10 are connected by the USB interface, but the interface type is not limited to this.
• it may be connected by a PCMCIA interface, or may be connected by a serial ATA interface or an IEEE 1394 interface.
• the data storage location of the flash memory has been described using the term “address”.
• this term is applied to the type of file system, operating system, and storage device that is applied.
• “sector”, ⁇ cluster ”,“ block ”, etc. can be read as appropriate.
• the present invention should not be construed as being limited in any way by the above-described embodiments, modifications, or other embodiments, and the scope of protection of the present invention is of course interpreted in accordance with the claims and the spirit of the present invention. It is.

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• Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
• Techniques For Improving Reliability Of Storages (AREA)

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• 2006
  • 2006-05-18 JP JP2006138781A patent/JP4676378B2/ja active Active
• 2007
  • 2007-05-11 CN CN200780018136.3A patent/CN101449248B/zh active Active
  • 2007-05-11 EP EP07743614A patent/EP2031514A4/en not_active Withdrawn
  • 2007-05-11 US US12/300,789 patent/US8364730B2/en active Active
  • 2007-05-11 WO PCT/JP2007/060179 patent/WO2007135967A1/ja not_active Ceased
  • 2007-05-15 TW TW096117256A patent/TW200809494A/zh unknown

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