Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/0033—Radiation hardening
  • H03K19/00338—In field effect transistor circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/007—Fail-safe circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

• the present invention relates generally to electronic circuit design, and more specifically to fault tolerant asynchronous electronic circuits.
• Asynchronous circuits do not use a clock signal for their operation. Since the clock is not present, it cannot be used to filter "glitches” or data hazards. Therefore asynchronous circuits and in particular asynchronous control circuits do not function correctly if they have any switching hazards on their signals.
• a transient fault can be thought of as a temporary change in a signal value — a change that causes a "glitch” in the circuit. This error can propagate and create functionality issues, including deadlocks and/or incorrect data computation.
• the present invention is a circuit design technique to make asynchronous circuits tolerate transient faults that can be introduced due to a variety of effects, including radiation effects such as single-event upsets (SEUs) or more broadly single- event effects (SEEs).
• SEUs single-event upsets
• SEEs broadly single- event effects
• a fault tolerant asynchronous circuit one apparatus comprising: a first logic circuit for receiving an input signal to generate an output signal; a second logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal; a staticizer circuit, comprising: first and second C-elements each connected to receive the output signal from each of the first and second logic circuits; and third and fourth C-elements each connected to the output of each of the first and second C-elements and to the output of each of the first and second logic circuits.
• a fault tolerant asynchronous circuit one apparatus comprising: a first logic circuit for receiving an input signal to generate an output signal; a second logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal; a third logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal; and a fourth logic circuit comprising a replica of said first logic circuit for receiving the input signal and generating the output signal; a first combining circuit for combining the outputs of each of said first and second logic circuits to generate the output signal; a second combining circuit for combining the outputs of each of said third and fourth output signals to generate the output signal; a staticizer circuit, comprising: first and second C-elements each connected to receive the output signal from each of the first and second combining circuits; and third and fourth C-elements each connected to the output of each of the first and second C-elements and the output of each of the first and
• a staticizer circuit for use with a logic or memory circuit to provide SEE immunity to the logic or memory circuit
• one apparatus comprising: a first circuit branch comprising a first C-element and a first pair of series-chain- connected inverters connected to the output of the first C-element; a second circuit branch comprising a second C-element and a second pair of series-chain-connected inverters connected to the input output of the second C-element; a third circuit branch comprising a third C-element and a third pair of series- chain-connected inverters connected to the output of the third C-element; the two inputs of the first C-element connected to the second and third inverter pairs; the two inputs of the second C-element connected to the first and third inverter pairs; the two inputs of the third C-element connected to the first and second inverter pairs; the first and third circuit branches for receiving an input signal and a duplicate of the input signal, respectively,
• a read circuit comprising: a write circuit; a staticizer circuit, comprising: first and second C-elements each connected to each of the read and write circuits; and third and fourth C-elements each connected to the output of each of the first and second C-elements and to the read and write circuits; whereby the staticizer circuit functions to prevent a single write from changing the overall state of the SRAM during a time-limited fault.
• Figure 1 is a circuit diagram showing of a prior art combinational logic circuit including a holding element in accordance with the prior art.
• Figure 2 is a circuit diagram illustrating a state-holding SEE immune gate in accordance with a first embodiment of the invention.
• Figure 2B is a circuit diagram illustrating a state-holding SEE immune gate in accordance with another embodiment of the invention.
• Figure 3 is a circuit diagram illustrating a state-holding SEE immune gate in accordance with another embodiment of the invention.
• Figure 4 is a circuit diagram showing a generalized C-element keeper in accordance with an embodiment of the invention.
• Figure 5 is a circuit diagram illustrating a state-holding SEE immune gate in accordance with another embodiment of the invention.
• Figure 6 is a circuit diagram of a C-element.
• Figure 7 is a circuit diagram of a fault - tolerant SRAM circuit.
• Figure 8 is a circuit diagram of a state - holding cell for an SRAM circuit.
• the invention is directed to circuit design techniques, and the associated methods and circuits, for making asynchronous circuits tolerate transient faults that can be introduced due to a variety of effects, including radiation effects such as single-event upsets (SEUs) or more broadly single-event effects (SEEs).
• SEUs single-event upsets
• SEEs broadly single-event effects
• a SEE results from a single, energetic particle.
• An SEU is a radiation-induced error in a microelectronic circuit caused when charged particles lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs. An undetected and hence uncorrected SEU can result in a microelectronic circuit generating an incorrect signal value.
• While certain logic chips may include both clocked synchronous circuits and un-clocked asynchronous circuits on the same chip, the asynchronous circuits do not use a clock signal for their operation. Since the clock is not present, it cannot be used to filter "glitches” or data hazards. Therefore asynchronous circuits and in particular asynchronous control circuits cannot have any switching hazards on their signals. A transient fault can be thought of as a temporary change in a signal value — a change that causes a "glitch" in the circuit. This error can propagate and create functionality issues, including deadlocks and/or incorrect data computation.
• the invention is directed to a new circuit technique to combat transient faults, and in particular SEEs.
• SEEs we will use the acronym SEEs to include arbitrary transient faults, including radiation-induced transient faults.
• SEEs to include arbitrary transient faults, including radiation-induced transient faults.
• Example circuit families include speed independent circuits, some self-timed circuits, and quasi delay-insensitive circuits.
• a gate that can be described by a pull-up network (that can set the output high) and a pull-down network (that can set the output low).
• a gate is characterized by the Boolean conditions under which the two networks are conducting.
• a gate is said to be combinational when either the pull-up network or pull-down network is conducting no matter what the state of the system is. Otherwise, if the pull-up network or pull-down network is not conducting, that is, if there is a state where the pull-up or pull-down network is not conducting, a gate is said to be state- holding.
• An SEE can cause the output of the gate to change its value (if the value doesn't change, we can ignore the SEE). This might cause the rest of the asynchronous circuit to malfunction.
• a replica of the gate This replica must be designed in a way that prevents it from being affected by the same SEE as the original gate. Two nodes that must have independent faults in order to each be affected by a fault are said to be independent nodes.
• the present invention is a novel circuit technique for implementing this principle that is significantly more efficient than existing techniques, and provides robustness to SEEs that previously proposed solutions cannot tolerate.
• the gates for xa and xb are the same as the original gate, except all inputs for the gate for xa correspond to nodes that have an "a" label, while all inputs to the gate for xb correspond to nodes that have a "b" label.
• we can apply this to any connected set of combinational gates the entire connected set of gates is duplicated, and one set is labeled "a" while the other set is labeled "b".
• all the signals in one set of combinational logic gates must be independent from all the signals in the other set of combinational logic gates. (Normally, only signals with the same name and differing labels are required to be independent.)
• x is state-holding, then it contains both the pull-up and pull-down network, plus an extra state-holding element called a staticizer or a keeper. Both must be modified for the circuit to be SEE-immune. We describe several different mechanisms to make the gate for x SEE-immune.
• the first mechanism replaces every transistor in the pull-down and pull-up network with two transistors in series. If the gate input to one of the original transistors was g, the inputs to the two transistors that replace it are ga and gb. After this transformation, the gates can be re-ordered as long as they still implement the same Boolean condition for conduction of the pull-up/pull-down network. This part of the first mechanism is previously known. In contrast, the present invention provides a new and improved staticizer circuit. We discuss first the structure shown in Figure 1.
• Figure 1 is representative of the prior art, showing a circuit 100 including an original gate 102, with original inputs 101 and output 104 along with a staticizer 103 that is used to hold state. In accordance with the present invention, both are modified for the circuit to be SEE-immune.
• the original prior art gate 102 is shown, with it original inputs 101 labeled I (inputs may include multiple signals) and output 104 labeled x along with a staticizer (also known as a keeper) 103 that is used to hold state.
• the symbol G( ) is used to denote the function and geometry of the gate and is parameterized by the input signals.
• a SEE immune version of a logic circuit 210 equivalent in function to that of Figure 1 contains a replicated version of the gate 105.
• each transistor in the original gate 102 is replaced by two series transistors in each of gates 105, as described above.
• the intput signals a and b (Ia, Ib) are split between the two double-transistor gates indicated as double Gl and double G2.
• the two transistors are used to/provide the benefit of fault immunity, as is known, whereby if a fault causes the input of one of the transistors to change, the use of two transistors in series (the 'double' Gl and G2) will prohibit the circuit output from changing.
• the duplication of the combinational function through the use of both Gl and G2 is used with the inventive staticizer described below to increase error resistance.
• C is used to indicate a C-element
• wC is used to indicate a weak C-element — a gate with reduced drive strength compared to an ordinary gate. While “C” and “wC” are used throughout to indicate the C-elements, they do not necessarily indicate identical configurations but are as described with respect to each circuit description.
• a C-element is a commonly used asynchronous logic component that applies logical operations on the inputs and may have hysteresis. The output of the C-element reflects the inputs when the states of all inputs match. The output then remains in this state until the inputs all transition to the other state.
• Types include an asymmetric C-element where some inputs only effect the operation in one of the transitions (positive or negative).
• a weak wC C-element the structure and operation of the circuit is the same as a C-element except the current drive strength of the gate is reduced so that it can be overpowered by a normal gate. It will be understood by the reader that 'weak' circuit elements are used where it is desirable for a principal circuit output to 'overpower' a weak circuit element for some period of time.
• Signals xa and xb are individually connected to the inverting input of wCl and wC2, respectively.
• the outputs of Cl and C2 support the signals xa and xb which are connected and cross-connected to wCl and wC2.
• the weak C-elements will correct the output in this scenario if the doubled gates G1/G2 are in a state where they are not driving the output. If they are driving the output, they will correct the output eventually. Similarly, an error on " xa” or " xb" will be corrected by the C-elements driving them. Finally, error propagation is blocked at the next doubled gate. With the doubling of the transistors, the replicating of the gate and the use of the inventive staticizer circuit 106, the circuit is thus seen to be immune to SEE's on both the inputs and outputs.
• a SEE immune version of a logic circuit 210' equivalent in function to that of Figure 1 contains a variation of circuit 210 of Figure 2A, wherein the gates 201, 202 are each identical to gate 102 of Figure 1.
• the cross-coupled C-elements also known as consensus elements
• the symbol "C” is used to indicate a C-element
• "wC” is used to indicate a weak C- element — a gate with reduced drive strength compared to an ordinary gate.
• a slightly modified keeper circuit 301 with the C-elements connected substantially identically to those described above and that has the additional property that the input and output of each C-element in the keeper is spaced by a gate that is combinational, indicated at Wl, W2, W3 and W4. Since inverters are already present in this circuit, we can simply use those signals as the output of the gate without introducing any additional inverter externally. It will be understood that in this configuration only the gate needing to be overpowered by the main gate is a 'weak' gate, here the inverters so they can be overpowered by the logic circuit G.
• the generalized keeper circuit contains k-input
• Gates 401 are all k-input C-elements, having inputs al, a2, ..., ak.
• Gates 402 are also k-input C-elements having inputs bl, b2, ..., bk.
• the "a" inputs are all connected to their corresponding replica gate, as in the dual-path case (shown in Figure 3).
• each keeper branch 404 occurs two-dimensionally in parallel (as shown) and series based on the number of simultaneous faults the circuit must tolerate.
• this SEE-immune circuit as a multi-path logic circuit, as there are multiple paths that compute the same signals in parallel with occasional synchronization and cross-checking between the paths using C-element circuits.
• FIG. 1 Another embodiment of the present invention includes a decomposed version of the SEE-immune gate shown in Figure 1.
• This mechanism does not use the two series transistor substitution as shown in Figure 2A. Instead, the original gate element is replicated four times and C-elements are used to combine the outputs into the final xa and xb signals.
• a general representation 510 of the circuit of Figure 2A is shown decomposed and replicated four times as Gl, G2, G3, G4 in the circuit 520. Each original gate is replicated four times: twice where the inputs are replaced with signals that have the "a" label, and twice when the inputs are replaced with signals that have the "b" label.
• the four gate outputs are xa a , xa b , xb a , xb b where the superscript denotes the labels of the input signals that are used to generate the appropriate output.
• the signals are combined using C-elements to generate the signals xa and xb, and it will be seen that the inverted outputs of the C elements Cl and C2 are i) inverted and fed back to the respective outputs of the gates Gl, G2, G3 and G4 and ii) inverted to generate signals xa, xb.
• a keeper structure 502 described below, is used as a state-holding element for xa and xb.
• the keeper circuit becomes state holding and is unable to restore the output signals to their correct value.
• the input and output of the C-elements are independent; however, this may not be possible to implement because of the physical geometry constraints imposed by a transistor-level implementation — the source/drain region connected to the output of a C-element will be immediately adjacent to a gate that is connected to one of its inputs.
• the keeper circuits including the inverter elements as shown in Figures 3 (circuit 301) and 4 .
• the invert-based keepers Cl, C2 can be combined with any of the keeper circuit 502 solutions described above that contain a C-element keeper, to increase the robustness of the circuit to SEEs, for example 103 ( Figure 1), 106 ( Figure 2A), 203 ( Figure 2B) or 301 ( Figure 3).
• FIG. 7 there is shown an SRAM circuit configuration comprising a hybrid of SEE-immune configurations between the circuits of Figures 2A and 2B above, with double-transistor read circuits (r) and single transistor write circuits (w).
• the staticizer circuit 702 is substantially identical to that of Figures 3 and 4, though it will be understood that in different embodiments the inverters W1-W4 may be omitted.
• the read circuits are connected to the ua, ub signal rails and the write circuits wa, wb to both the ua, ub and ua, ub signal rails.
• Figure 7 shows a single read line r. This signal can also be shared across multiple bit-cells as is common in a conventional SRAM. If there is sufficient capacitance on signal r, then it may be immune to SEE effects; otherwise, the n-transistor chain for r can be replicated to generate two read lines ra and rb.
• da can be connected to db and da can be connected to db.
• the transistor widths for the write transistors are chosen to be large enough to overwrite the state of the cell.
• the C-elements in the circuit are used to cross-check the value of the state.
• the top half and bottom half of the circuit must be separated to prevent simultaneous bit-flips in the two parts of the circuit.
• the amount by which the two halves are separated is a function of the types of errors that the circuit is designed to tolerate. Errors can be caused by a variety of physical effects, such as cross-talk, coupling, cosmic rays, or particle hits. Each physical effect has a certain physical region it can affect, called its region of influence.
• a particle hit would impact a region that is determined by the size of the particle, its energy, and the materials it is interacting with.
• the separation amount for the two halves of the circuit must be chosen so that an individual physical effect will never have a region of influence that includes both halves of the circuit. This can be achieved by physically separating the structure of the two halves of the circuit within the semiconductor substrate in which they are formed.
• the write select signals are set high and either (0,1) or (1,0) is driven on both pairs (da,_da) and (db,_db).
• the cell will be correctly written.
• two nodes are driven low via the write circuitry. In the presence of an upset, only one of those nodes will be correctly written.
• the C-elements in the circuit will prevent a single write from changing the overall state of the SRAM cell. Therefore, as soon as the upset is eliminated both nodes will be written correctly, and the C-elements will allow the state change to proceed.
• the window of time needed to complete the write is governed by the time taken to set the two directly written nodes to ground, followed by the delay required for the feedback loop containing the four C-elements to change state. Removal of the write signals results in the cell holding state even in the presence of additional SEE effects.
• Figure 8 shows an alternative cell for the state-holding part of an SEE- immune SRAM cell. Transistor sizes are selected for the C-elements so that they can overwrite the cross-coupled inverter pairs. Signals ua, ub, _ua, ub correspond to the same signals from Figure 7. Reads and writes to this cell can be performed using the same circuits as shown in Figure 7; these read and write circuits are omitted for clarity.
• C-elements Cl, C3 are cross-connected between the signals ua, ub (Cl), ua, ub (C2) and both to C2.
• Each C-element C 1-3 has an associated parallel-pair set of inverters II, 12 and 13 associated therewith buffering the input signal and the cross- connection to C2.
• the central C-element acts as a 'voting' element to resolve discrepancies between the ua C-element and the ub C-element, as follows:
• Synchronous solutions to the SEE problem involve having multiple copies of the logic and then a voter circuit that resolves discrepancies between the copies.
• a TMR scheme involves three replica circuits and a majority voter.
• a fundamental difference between these techniques and the invention is that the fixed frequency of synchronous logic imposes a timing window of vulnerability — if an upset occurs right near a clock edge, the recovery logic may not be able to correct it.
• the present invention provides methods and systems for SRAM circuits that wait for the upset to be corrected before continuing execution.
• an asynchronous circuit can also use pass-transistor logic.
• a pass transistor connects two nodes in the circuit using either a single n-type transistor or p-type transistor (n-type or p-type transmission gate) or both an n-type and p-type transistor connected in parallel (full transmission gate).
• Synchronous solutions to the SEE problem involve having multiple copies of the logic and then a voter circuit that resolves discrepancies between the copies.
• a TMR scheme involves three replica circuits and a majority voter.
• a fundamental difference between these techniques and the invention is that the fixed frequency of synchronous logic imposes a timing window of vulnerability — if an upset occurs right near a clock edge, the recovery logic may not be able to correct it.
• Our approach involves only two copies (not three — the minimum required for voting), and the asynchronous logic simply waits for the two copies to agree before continuing execution.
• the prior art of Jiang and Martin as described above discloses a scheme that uses two series transistors for each original transistor in the circuit, as well as two C- elements on the output.
• the proposed approach differs because: (i) We do not replicate series transistors in combinational logic; (ii) The decomposition in some embodiments eliminates the two series transistor construction for state-holding logic; (iii) The construction shown in some embodiments does not use two C-elements to drive the primary output — instead, C-elements are only used to implement the keeper circuit; and (iv) The robust C-element keepers shown are a novel construction, and the modification improves the SEE immunity of the logic.

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