JP5158607B2 - 耐故障性非同期回路 - Google Patents

耐故障性非同期回路 Download PDF

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Publication number
JP5158607B2
JP5158607B2 JP2009507984A JP2009507984A JP5158607B2 JP 5158607 B2 JP5158607 B2 JP 5158607B2 JP 2009507984 A JP2009507984 A JP 2009507984A JP 2009507984 A JP2009507984 A JP 2009507984A JP 5158607 B2 JP5158607 B2 JP 5158607B2
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Japan
Prior art keywords
circuit
output
elements
logic
outputs
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JP2009507984A
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English (en)
Japanese (ja)
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JP2009538549A (ja
JP2009538549A5 (enExample
Inventor
マノハー，ラジット
ダブリュ． ケリー，クリントン
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Achronix Semiconductor Corp
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Achronix Semiconductor Corp
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Priority claimed from US11/740,180 external-priority patent/US7504851B2/en
Priority claimed from US11/740,168 external-priority patent/US7505304B2/en
Application filed by Achronix Semiconductor Corp filed Critical Achronix Semiconductor Corp
Publication of JP2009538549A publication Critical patent/JP2009538549A/ja
Publication of JP2009538549A5 publication Critical patent/JP2009538549A5/ja
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Publication of JP5158607B2 publication Critical patent/JP5158607B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2009507984A 2006-04-27 2007-04-27 耐故障性非同期回路 Active JP5158607B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US79612506P 2006-04-27 2006-04-27
US60/796,125 2006-04-27
US81733506P 2006-06-28 2006-06-28
US81750806P 2006-06-28 2006-06-28
US60/817,508 2006-06-28
US60/817,335 2006-06-28
US11/740,168 2007-04-25
US11/740,180 2007-04-25
US11/740,180 US7504851B2 (en) 2006-04-27 2007-04-25 Fault tolerant asynchronous circuits
US11/740,168 US7505304B2 (en) 2006-04-27 2007-04-25 Fault tolerant asynchronous circuits
PCT/US2007/067622 WO2007127917A2 (en) 2006-04-27 2007-04-27 Fault tolerant asynchronous circuits

Publications (3)

Publication Number Publication Date
JP2009538549A JP2009538549A (ja) 2009-11-05
JP2009538549A5 JP2009538549A5 (enExample) 2010-06-17
JP5158607B2 true JP5158607B2 (ja) 2013-03-06

Family

ID=38656414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009507984A Active JP5158607B2 (ja) 2006-04-27 2007-04-27 耐故障性非同期回路

Country Status (4)

Country Link
EP (1) EP2020085B1 (enExample)
JP (1) JP5158607B2 (enExample)
KR (1) KR101060270B1 (enExample)
WO (1) WO2007127917A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7505304B2 (en) 2006-04-27 2009-03-17 Achronix Semiconductor Corporation Fault tolerant asynchronous circuits
US7504851B2 (en) 2006-04-27 2009-03-17 Achronix Semiconductor Corporation Fault tolerant asynchronous circuits
WO2011155532A1 (ja) * 2010-06-11 2011-12-15 国立大学法人京都工芸繊維大学 フリップフロップ回路、半導体装置および電子機器
FR2998688B1 (fr) * 2012-11-29 2014-12-26 Electricite De France Procede de durcissement logique par partitionnement d'un circuit electronique
JP6310933B2 (ja) * 2013-10-16 2018-04-11 株式会社日立製作所 半導体装置
CN109991531B (zh) * 2019-03-28 2021-12-24 西北核技术研究所 低概率条件下大气中子单粒子效应截面测量方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4785204A (en) * 1985-06-21 1988-11-15 Mitsubishi Denki Kabushiki Kaisha Coincidence element and a data transmission path
JP4904154B2 (ja) * 2003-07-14 2012-03-28 フルクラム・マイクロシステムズ・インコーポレーテッド 非同期スタティックランダムアクセスメモリ
US7157934B2 (en) * 2003-08-19 2007-01-02 Cornell Research Foundation, Inc. Programmable asynchronous pipeline arrays
WO2006026676A2 (en) * 2004-08-30 2006-03-09 California Institute Of Technology Seu-tolerant qdi circuits
US7301362B2 (en) * 2005-03-14 2007-11-27 California Institute Of Technology Duplicated double checking production rule set for fault-tolerant electronics

Also Published As

Publication number Publication date
EP2020085B1 (en) 2017-11-08
EP2020085A2 (en) 2009-02-04
WO2007127917A3 (en) 2008-07-24
KR101060270B1 (ko) 2011-08-29
WO2007127917A2 (en) 2007-11-08
EP2020085A4 (en) 2011-04-27
JP2009538549A (ja) 2009-11-05
KR20090003367A (ko) 2009-01-09

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