WO2007094295A1 - プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置 - Google Patents
プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置 Download PDFInfo
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- WO2007094295A1 WO2007094295A1 PCT/JP2007/052474 JP2007052474W WO2007094295A1 WO 2007094295 A1 WO2007094295 A1 WO 2007094295A1 JP 2007052474 W JP2007052474 W JP 2007052474W WO 2007094295 A1 WO2007094295 A1 WO 2007094295A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
- G09G3/2946—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge by introducing variations of the frequency of sustain pulses within a frame or non-proportional variations of the number of sustain pulses in each subfield
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/10—AC-PDPs with at least one main electrode being out of contact with the plasma
- H01J11/12—AC-PDPs with at least one main electrode being out of contact with the plasma with main electrodes provided on both sides of the discharge space
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
- G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
Definitions
- the present invention relates to a method of driving a plasma display panel used in a wall-mounted television or a large monitor, and a plasma display device.
- a typical AC surface discharge type panel as a plasma display panel (hereinafter referred to as "panel"), a large number of discharge cells are formed between a front plate and a back plate disposed opposite to each other.
- a front plate a plurality of display electrode pairs consisting of a pair of scan electrodes and sustain electrodes are formed in parallel to each other on the front glass substrate, and a dielectric layer and a protective layer are formed to cover the display electrode pairs.
- the back plate includes a plurality of parallel data electrodes on the back glass substrate, a dielectric layer covering them, and a plurality of partitions on top of the back electrodes, which are parallel to the data electrodes.
- a phosphor layer is formed on the surface and the side of the partition wall.
- the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode intersect each other, and sealed.
- a discharge gas containing, for example, 5% of xenon in a partial pressure ratio is enclosed in the discharge space inside. It is done!
- a discharge cell is formed in the portion where the display electrode pair and the data electrode face each other.
- ultraviolet light is generated by gas discharge in each discharge cell, and the ultraviolet light excites and emits phosphors of each color of red (R), green (G) and blue (B). Color display.
- a sub-field method that is, a method in which one field period is divided into a plurality of sub-fields and gray scale display is performed by a combination of sub-fields to be illuminated It is.
- Each subfield has an initialization period, an address period and a sustain period, and generates an initialization discharge in the initialization period to form wall charges necessary for the subsequent address operation on each electrode.
- address discharge is selectively generated in the discharge cells to be displayed to form wall charges.
- sustain pulses are alternately applied to the display electrode pair consisting of the sustain electrode and the sustain electrode, sustain discharge is generated in the discharge cell in which the address discharge has occurred, and the phosphor layer of the corresponding discharge cell is illuminated.
- the image is displayed by
- each of the display electrode pairs is a capacitive load having an inter-electrode capacitance of the display electrode pair as one of techniques for reducing power consumption in the sustain period, and a resonant circuit including an inductor as a component
- the LC resonance between the inductor and the inter-electrode capacitance is used, the charge stored in the inter-electrode capacitance is recovered to the capacitor for power recovery, and the recovered charge is reused for driving the display electrode pair.
- a recovery circuit has been proposed (see, for example, Patent Document 1).
- the setup discharge is performed using a slowly changing voltage waveform, and the setup discharge is selectively performed on the discharge cell which has performed the sustain discharge.
- a novel driving method has been proposed in which light emission unrelated to display is minimized to improve the contrast ratio (see, for example, Patent Document 2).
- Patent Document 1 Japanese Patent Publication No. 7-109542
- Patent Document 2 Japanese Patent Application Laid-Open No. 2000-242224
- the panel drive method and plasma display apparatus of the present invention provide a panel drive method and plasma display apparatus capable of achieving high panel brightness and reduction of power consumption.
- the present invention is a method of driving a panel provided with a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode.
- an address period for generating address discharge selectively in the discharge cell and a sustain period for generating a sustain discharge in the discharge cell in which the address discharge is generated by marking the sustain pulse the number of times corresponding to the luminance weight.
- the plasma display apparatus according to the present invention sets the repetition cycle of the sustain pulse based on the average luminance level of the image signal. This makes it possible to further reduce the power consumption.
- the repetition period of the sustaining pulse in the subfield having the largest luminance weight be shortened stepwise as the average luminance level decreases.
- an overlapping period is provided in which the rising time of the sustaining pulse applied to one of the display electrode pair and the rising time of the sustaining pulse applied to the other of the display electrode pair overlap.
- the duration is the time during which the voltage of the sustain pulse is clamped to a predetermined voltage.
- a panel provided with a plurality of discharge cells having a display electrode pair consisting of scan electrodes and sustain electrodes, an average luminance level detection circuit for detecting an average luminance level of an image signal, And a sustain pulse generation circuit that applies a sustain pulse to each of the display electrode pairs to generate a sustain discharge.
- the sustain pulse generation circuit resonates the capacitance between the display electrode pair and the inductor to cause the sustain pulse to rise and fall, and a clamp for clamping the voltage of the sustain pulse to a predetermined voltage. And setting the repetition cycle of the sustain pulse based on the average luminance level of the image signal.
- FIG. 1 is an exploded perspective view showing a structure of a panel to which the embodiment of the present invention is applied.
- FIG. 2 is an electrode array diagram of a panel to which the embodiment of the present invention is applied.
- FIG. 3 is a circuit block diagram of a plasma display device according to an embodiment of the present invention.
- FIG. 4 is a drive voltage waveform diagram applied to each electrode of the panel to which the embodiment of the present invention is applied.
- FIG. 5 is a view showing a sub-field configuration which is a feature of the embodiment of the present invention.
- FIG. 6 is a circuit diagram of a sustain pulse generating circuit according to an embodiment of the present invention.
- FIG. 7 is a timing chart showing the operation of the sustain pulse generating circuit according to the embodiment of the present invention.
- FIG. 8A is a view showing the relationship between the rise time of the sustain pulse and the reactive power of the sustain pulse generation circuit according to the embodiment of the present invention.
- FIG. 8B is a view showing the relationship between the rise time of the sustain pulse and the luminous efficiency according to the embodiment of the present invention.
- FIG. 9 is a view showing the relationship between the voltage applied to the sustain electrode, the erase phase difference, and the rise time of the last sustain pulse in the initialization period according to the embodiment of the present invention.
- FIG. 10 is a view showing the relationship between the rise time S of the penultimate sustain pulse according to the embodiment of the present invention and the voltage applied to the sustain electrode in the initialization period.
- FIG. 11 is a diagram showing the relationship between the lighting rate and the lighting voltage according to the embodiment of the present invention, using the maintenance cycle as a parameter.
- FIG. 12 is a view showing the relationship between the APL of the plasma display device according to the embodiment of the present invention and the shape of the sustain pulse.
- FIG. 13 is a diagram showing the relationship between the sustain period and duration and the write voltage of the present invention.
- FIG. 14 is a drive voltage waveform diagram applied to each electrode of the panel to which another embodiment of the present invention is applied.
- FIG. 1 is an exploded perspective view showing the structure of a panel 10 according to an embodiment of the present invention.
- a plurality of display electrode pairs 28 composed of scan electrodes 22 and sustain electrodes 23 are formed on the front plate 21 made of glass.
- the dielectric layer 24 covers the scanning electrode 22 and the sustaining electrode 23.
- the protective layer 25 is formed on the dielectric layer 24.
- a plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and further, parallel-bar-like partitions 34 are formed thereon.
- a phosphor layer 35 emitting light of red (R), green (G) and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.
- the front plate 21 and the back plate 31 are disposed opposite to each other so that the display electrode pair 28 and the data electrode 32 intersect with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is a sealing material such as glass frit. It is sealed.
- a mixed gas of neon and xenon is enclosed as a discharge gas.
- a discharge gas with a xenon partial pressure of 10% is used to improve the luminance.
- the discharge space is divided into a plurality of sections by the barrier ribs 34, and discharge cells are formed at the intersections of the display electrode pairs 28 and the data electrodes 32. An image is displayed as the discharge cells discharge and emit light.
- the structure of the panel is not limited to that described above, and may be provided with, for example, stripe-shaped barrier ribs.
- FIG. 2 is an electrode array diagram of panel 10 in accordance with an embodiment of the present invention.
- m long data electrodes D1 to Dm (data electrodes 32 in FIG. 1) are arranged in the column direction.
- scan electrode SCi and sustain electrode SUi are formed in parallel to each other, and therefore, between scan electrodes SCl to SCn and sustain electrodes SUl to SUn.
- FIG. 3 is a circuit block diagram of plasma display device 1 according to the embodiment of the present invention.
- the plasma display device 1 is necessary for the panel 10, the image signal processing circuit 51, the data electrode drive circuit 52, the scan electrode drive circuit 53, the sustain electrode drive circuit 54, the timing generation circuit 55, the APL detection circuit 58 and each circuit block. It has a power supply circuit (not shown) that supplies power.
- the image signal processing circuit 51 converts the input image signal Sig into image data indicating light emission / no light emission in each subfield.
- Data electrode drive circuit 52 converts the image data for each subfield into signals corresponding to each of data electrodes D1 to Dm, and drives each of data electrodes D1 to Dm.
- the APL detection circuit 58 detects an average luminance level (hereinafter abbreviated as “APL”) of the image signal Sig. Specifically, the APL is detected by using a generally known method such as accumulating luminance values of an image signal over one field period or one frame period, for example.
- APL average luminance level
- Timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on APL detected by horizontal synchronization signal H, vertical synchronization signal V and APL detection circuit 58, and Supply to the circuit block of Scan electrode drive circuit 53 has a sustain pulse generation circuit 100 for generating a sustain pulse to be applied to scan electrodes SCl to SCn in the sustain period, and each scan electrode SC1 to SCn is generated based on the timing signal. Drive SCn respectively.
- Sustain electrode drive circuit 54 includes a circuit for applying voltage Vel to sustain electrodes SUl to SUn in the initializing period, and a sustain pulse generating circuit for generating sustain pulses to be applied to sustain electrodes SUl to SUn in the sustain period. And 200, and drive sustaining electrodes SU 1 to SUn based on the timing signal.
- the plasma display apparatus 1 performs gradation display by the sub-field method, that is, one field period is divided into a plurality of sub-fields, and emission / non-emission of each discharge cell is controlled for each sub-field.
- Each sub-field has an initialization period, a write period and a sustain period.
- a setup discharge is generated in the setup period, and wall charges necessary for the subsequent address discharge are formed on each electrode.
- the initialization operation at this time includes an initialization operation for generating an initialization discharge in all discharge cells (hereinafter abbreviated as “all cell initialization operation”) and an initialization discharge in a discharge cell which has undergone a sustain discharge.
- selection initialization operation In the address period, address discharge is selectively generated in the discharge cells to be lit to form wall charges. Then, in the sustaining period, sustaining pulses of a number proportional to the luminance weight are alternately applied to the display electrode pair to generate the address discharge. A sustain discharge is generated in the power cell to emit light. The proportional constant at this time is called the luminance magnification.
- FIG. 4 is a drive voltage waveform diagram applied to each electrode of the panel 10 according to the embodiment of the present invention.
- FIG. 4 shows subfields in which the all-cell initializing operation is performed and subfields in which the selective initializing operation is performed.
- OV is applied to data electrodes Dl to Dm and sustain electrodes SUl to SUn, and to scan electrodes SCl to SCn, voltages lower than the discharge start voltage with respect to sustain electrodes SUl to SUn.
- ramp voltage a ramp waveform voltage that gradually rises toward voltage Vi2 that exceeds the discharge start voltage.
- weak setup discharges occur between the scan electrodes SCl to SCn, the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm.
- Negative wall voltage is accumulated on scan electrodes SCl to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.
- the wall voltage at the upper part of the electrode means the voltage generated by the wall charge accumulated on the dielectric layer covering the electrode, on the protective layer, on the phosphor layer or the like.
- voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SCl to SCn.
- the data electrode The voltage difference at the intersection of Dk and scan electrode SCI is the difference between the externally applied voltage (Vd-Va) and the difference between the wall voltage on data electrode Dk and the wall voltage on scan electrode SC1. The discharge start voltage is exceeded.
- an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1, and a negative voltage is generated on sustain electrode SU1.
- the wall voltage is accumulated, and the negative wall voltage is also accumulated on the data electrode Dk.
- an address operation is performed to cause address discharge in the discharge cells to be lit in the first row and to accumulate wall voltage on each electrode.
- the jamming discharge does not occur.
- the above address operation is performed up to the discharge cell of the nth row, and the address period is completed.
- a sustain discharge occurs between the scan electrode SCi and the sustain electrode SUi, and the phosphor layer 35 emits light due to the ultraviolet light generated at this time. Then, negative wall voltage is accumulated on scan electrode SCi, and positive wall voltage is accumulated on sustain electrode SUi. Furthermore, positive wall voltage is also accumulated on data electrode Dk. In a discharge cell in which no address discharge occurs in the write period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.
- the number of sustainings obtained by alternately multiplying the luminance weight by the luminance magnification for scan electrodes SC1 to SCn and sustain electrodes SU 1 to SUn By applying a pulse and applying a potential difference between the electrodes of the display electrode pair, a sustain discharge is continuously performed in the discharge cell in which the address discharge has occurred in the address period.
- a so-called narrow pulse-like voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, leaving a positive wall voltage on data electrode Dk.
- the sustain pulse voltage Vs is applied to the scan electrodes SCl to SCn. Then, a sustain discharge occurs between the sustain electrode SUi and the scan electrode SCi of the discharge cell which has caused the sustain discharge.
- a predetermined time interval (hereinafter referred to as “erase phase difference Thl” is referred to).
- erase phase difference Thl a voltage Vel is applied to the sustaining electrodes SU1 to SUn in order to reduce the potential difference between the display electrode pair.
- voltage Vel is applied to sustain electrodes SU1 to SUn
- OV is applied to data electrodes D1 to Dm
- voltage Vi3 'force voltage on scan electrodes SCl to SCn Apply a ramp voltage that gradually drops.
- a weak setup discharge is generated in the discharge cell in which the sustain discharge is caused in the sustain period of the previous subfield, and the wall voltage on the scan electrode SCi and the sustain electrode SUi is weakened.
- a sufficient positive wall voltage is accumulated on data electrode Dk by the previous sustain discharge, so an excessive portion of this wall voltage is discharged, and the wall suitable for the writing operation. Adjusted to the voltage.
- the selective initializing operation is an operation to selectively perform the initializing discharge with respect to the discharge cell which has performed the sustaining operation in the sustain period of the immediately preceding sub-field.
- the operation of the subsequent write period is the same as the operation of the write period of the subfield in which all the cells are to be initialized.
- the operation of the subsequent sustain period is the same except for the number of sustain pulses.
- FIG. 5 is a diagram showing a sub-field configuration which is a feature of the embodiment of the present invention.
- one field is divided into ten subfields (first SF, second SF, ⁇ , 10S F).
- Each subfield has a luminance weight of, for example, (1, 2, 3, 6, 11, 18, 30, 44, 60, 80).
- the all-cell initialization operation is performed in the initialization period of the first SF
- the selection initialization operation is performed in the initialization period of the second to tenth SFs.
- sustain pulses of the number obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification are applied to each of the display electrode pairs.
- the number of subfields and the luminance weight of each subfield are not limited to the above values.
- the sub-field configuration may be switched based on an image signal or the like.
- FIG. 6 is a circuit diagram of sustain pulse generating circuits 100 and 200 according to the embodiment of the present invention.
- the interelectrode capacitance of panel 10 is shown as Cp, and the circuit for generating the scanning pulse and the initializing voltage waveform is omitted.
- Sustain pulse generation circuit 100 includes a power recovery unit 110 and a clamp unit 120.
- the power recovery unit 110 includes a capacitor C10 for power recovery, switching elements Q11 and Q12, diodes D11 and D12 for reverse current prevention, and inductors LI1 and L12 for resonance.
- the clamp unit 120 also has switching elements Q13 and Q14.
- the power recovery unit 110 and the clamp unit 120 are connected to a scan electrode 22 which is one end of the interelectrode capacitance Cp via a scan pulse generation circuit (not shown because it is short-circuited during the sustain period).
- the inductances of the inductors Ll l and L12 are set so that the resonance period with the interelectrode capacitance Cp is longer than the sustain pulse duration.
- the resonance period is a period due to LC resonance.
- the inductance of the inductor L the capacitance of the capacitor When C is set, the resonance period can be obtained by the calculation formula “2 ⁇ (LC)”.
- the inductance L here is the inductance of the inductor LI 1 or the inductor L 12
- the capacitance C is the capacitance Cp between the electrodes of the panel 10.
- Power recovery unit 110 performs LC resonance of inter-electrode capacitance Cp and inductor L 11 or inductor L 12 to perform the rise and fall of the sustain pulse.
- the charge stored in the capacitor C10 for power recovery is transferred to the interelectrode capacitance Cp via the switching element Q11, the diode D11 and the inductor L11.
- the charge stored in the interelectrode capacitance Cp is returned to the power recovery capacitor C10 through the inductor L12, the diode D12 and the switching element Q12.
- the sustain pulse is applied to the scan electrode 22.
- the power recovery unit 110 drives the scanning electrode 22 by LC resonance without supplying power, the power consumption is ideally zero.
- the capacitor C10 for power recovery has a sufficiently larger capacity than the interelectrode capacitance Cp, and is charged to about VsZ2 which is half the voltage value Vs of the power supply VS so as to serve as a power source for the power recovery unit 110. ing. Since the power recovery unit 110 has a large impedance, if a strong discharge occurs while the scan electrode 22 is being driven by the power recovery unit 110, the voltage applied to the scan electrode 22 due to the discharge current is It will drop significantly.
- the discharge current is applied to the scan electrode 22.
- the voltage value of the power supply VS is set to a low value, so that the sustaining discharge to a certain extent does not decrease significantly.
- Voltage clamp unit 120 connects scan electrode 22 to power supply VS via switching element Q 13 and clamps scan electrode 22 to voltage Vs. Further, the scanning electrode 22 is grounded via the switching element Q14 and clamped at OV. Thus, the voltage clamp unit 120 drives the scanning electrode 22. Therefore, when the voltage is applied by the voltage clamp unit 120, a large discharge current due to a strong sustain discharge can be stably supplied.
- sustain pulse generation circuit 100 controls scan elements Q11, Q12, Q13 and Q14 to use scan line using power recovery unit 110 and voltage clamp unit 120. 22. Apply a sustain pulse.
- these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.
- Sustain pulse generation circuit 200 includes a power recovery unit 210 including a capacitor C20 for power recovery, switching elements Q21 and Q22, diodes D21 and D22 for backflow prevention, an inductor L21 for resonance, and an inductor L22.
- the clamp unit 220 having the elements Q23 and Q24 is connected to the sustain electrode 23 which is one end of the inter-electrode capacitance Cp of the panel 10.
- the operation of sustain pulse generating circuit 200 is similar to that of sustain pulse generating circuit 100. Also in this case, the inductances of the inductors L21 and L22 are set so that the resonance period with the interelectrode capacitance Cp is longer than the sustaining pulse duration.
- FIG. 6 also includes a power source VE generating a voltage Vel for reducing the potential difference between the display electrode pair and a switching element Q28 and Q29 for applying the voltage Vel to the sustain electrode 23. These actions will be described later.
- FIG. 7 is a timing chart showing the operation of sustain pulse generating circuits 100 and 200 according to the embodiment of the present invention.
- One cycle of the sustain pulse repetition cycle (hereinafter, referred to as "maintenance cycle") is divided into six periods indicated by T1 to T6, and each period will be described.
- the operation to turn on the switching element is referred to as “off” and the operation to turn off the operation is referred to as “off”.
- the repetition cycle is an interval of sustain pulses repeatedly applied to the display electrode pair in the sustain period, and represents, for example, a cycle repeated by the periods T1 to T6.
- FIG. 7 although the description is given using the waveform of the positive electrode, the present invention is not limited to this.
- the embodiment in the waveform of the negative electrode is omitted. Forces which are expressed as “rising” in the waveform of the positive electrode in the following description are read as “falling” in the waveform of the negative electrode. Even if it is a waveform, the same effect can be obtained.
- inductor L1 Since the resonance period of 2 and the interelectrode capacitance Cp is set to 2000 nsec, the voltage of the scan electrode 22 decreases to almost OV after 10 10 Onsec from time tl.
- the period T1 from time tl to time t2b that is, the fall time of the sustain pulse using the power recovery unit 110, is set based on the APL in the range of 650 nsec to 850 nsec, which is shorter than lOOOnsec.
- the voltage of the scanning electrode 22 does not fall to 0 V at time t. Then, at time t2b, the switching element Q14 is turned ON. Then, since the scan electrode 22 is directly grounded through the switching element Q 14, the voltage of the scan electrode 22 is clamped at 0V.
- Switching element Q24 is turned on, and sustain electrode 23 is clamped at 0V. Then, just before time t2a, the sustaining electrode 23 is clamped at 0 V, and the switching element Q24 is turned off.
- the switching element Q21 is turned on. Then, current starts flowing from the capacitor C20 for power recovery through the switching element Q21, the diode D21, and the inductor L21 to the sustaining electrode 23, and the voltage of the sustaining electrode 23 starts to rise. Since the resonance period of the inductor L21 and the interelectrode capacitance Cp is also set to 2000 nsec, the voltage of the sustain electrode 23 rises almost to the voltage Vs after lOOOnsec from time t2a. However, the period T2 from time t2a to time t3, that is, the rise time of the sustaining pulse using the power recovery unit 210 is set to 90 Onsec !, so at time t3! The voltage does not rise to Vs. Then, at time t3, the switching element Q23 is turned ON. Then, the sustaining electrode 23 is directly connected to the power source VS through the switching element Q23, so that the sustaining electrode 23 is clamped with the voltage Vss.
- this period that is, the period from time t2a to time t2b is referred to as an “overlap period”.
- the time of the overlapping period is set based on APL in the range of 250 nsec to 450 nsec.
- the maintenance period is shortened by providing this overlapping period.
- sustain electrode 23 When sustain electrode 23 is clamped at voltage Vs, the voltage difference between scan electrode 22 and sustain electrode 23 exceeds the discharge start voltage and sustain discharge occurs in the discharge cell in which the address discharge occurred. Ru. Then, the sustaining electrode 23 is clamped to the voltage Vs, and the switching element Q23 is turned off just before time t4.
- the voltage of sustain electrode 23 is maintained at sustain pulse voltage Vs
- the period T3 is the pulse duration of the sustain pulse applied to sustain electrode 23.
- the pulse duration means the time during which the voltage of the sustaining pulse raised by resonance is clamped to the voltage Vs and the voltage Vs is maintained for a predetermined time.
- the period T3 is set based on the APL in the range of 850 nsec to 1250 nsec.
- Switching element Q12 may be turned off after time t2b and before time t5a, and switching element Q21 may be turned off after time t3 and before time t4.
- switching element Q22 is turned on. Then, current starts flowing from the sustaining electrode 23 to the capacitor C20 through the inductor L22, the diode D22, and the switching element Q22, and the voltage of the sustaining electrode 23 starts to decrease.
- the resonance period between inductor L22 and interelectrode capacitance Cp is also set to 2000 nsec, while the period T4 from time t4 to time t5 b, that is, the rise time of the sustain pulse using power recovery unit 210 is 650 nsec to It is set based on APL in the range of 850 nsec. Therefore, at time t5b, the voltage of sustain electrode 23 does not fall to 0V! /.
- the switching element Q24 is turned on. Then, since sustain electrode 23 is directly grounded through switching element Q24, sustain electrode 23 is clamped at 0V.
- the switching element Q14 clamping the scanning electrode 22 to 0 V is turned off immediately before time t5a.
- the switching element Q11 is turned on. Then, current starts flowing from the capacitor C10 for power recovery through the switching element Q11, the diode D11, and the inductor L11 to the scan electrode 22, and the voltage of the scan electrode 22 starts to rise.
- the resonance period of the inductor L11 and the interelectrode capacitance Cp is set to 2000 nsec, while the fall time of the sustain pulse using the power recovery unit 110 is set to 900 nsec. Therefore, at time t6 The voltage of the scan electrode 22 does not rise to the voltage Vs. Then, at time t6, the switching element Q13 is turned ON. Then, the scan electrode 22 is clamped to the voltage Vs.
- a period is provided in which period T4 and period T5 overlap, and this period, ie, the period from time t5a to time t5b is also referred to as an “overlap period”. And the time of this overlapping period is also set based on the APL in the range of 250 nsec to 450 nsec.
- the voltage of scan electrode 22 is maintained at sustain pulse voltage Vs in period T6, and the duration of period T6 is the pulse duration of the sustain pulse applied to scan electrode 22.
- the period T6 is also set based on the APL in the range of 850 nsec to 1250 nsec.
- Switching element Q22 may be turned off after time t5b by time t2a of the next sustaining cycle, and switching element Q11 may be turned off after time t6 before time tl of the next sustaining cycle.
- switching element Q24 should be turned off just before time t2a of the next sustain cycle and switching element Q13 should be turned off just before time tl of the next sustain cycle. Is desirable.
- sustain pulse generating circuits 100 and 200 in the present embodiment apply a necessary number of sustain pulses to scan electrode 22 and sustain electrode 23.
- the resonance period of inductors L11, L21 and interelectrode capacitance Cp is the sustain pulse duration, ie, the period It is set to be longer than T3 and ⁇ 6.
- the times obtained by doubling the times 2 and 5 which are the rise times of the sustaining pulse using the power recovery units 110 and 210 are set to be longer than the times 3 and 6.
- the present inventors have examined the relationship between the resonance period of the power recovery units 110 and 210 and the reactive power and the light emission efficiency by changing the resonance period of the power recovery units 110 and 210, and changing the reactive power and the light emission. The efficiency was measured.
- the present inventors conducted experiments by setting the rise time of the sustain pulse to one half of the resonance period in the power recovery units 110 and 210. Therefore, for example, when the resonance period of the power recovery units 110 and 210 is 1200 nsec, the rise time is 600 nsec, and when the resonance period is 1600 nsec, the rise time is 800 nsec.
- FIG. 8A is a diagram showing the relationship between the rise time of the sustain pulse and the reactive power of the sustain pulse generation circuit according to the present embodiment.
- FIG. 8B is a view showing the relationship between the rise time and the luminous efficiency.
- 8A and 8B show values calculated by percentage assuming that the reactive power and the luminous efficiency are 100 when the rise time is 600 nsec, and the vertical axis in FIG. 8A indicates the reactive power ratio in FIG. 8B.
- the vertical axis of represents the luminous efficiency ratio, and the horizontal axis represents the rise time.
- the reactive power of sustain pulse generating circuits 100 and 200 is reduced by prolonging the rise time.
- the reactive power is reduced by about 10%, and the reactive power is reduced by about 15% by 900 nsec.
- increasing the rise time improves the light emission efficiency.
- the luminous efficiency is improved by about 5%, and by setting it to 900 nsec, the luminous efficiency is improved by about 13%.
- the rising of the sustain pulse is made gentle so as to be 750 nsec or more, more preferably 900 nsec or more, the luminous efficiency of the sustain discharge can be reduced by reducing the reactive power of the sustain pulse generation circuits 100 and 200 only. It has also been experimentally confirmed that it improves.
- the sustain pulse duration is too short, the wall voltage formed due to the sustain discharge will be insufficient, and the sustain discharge can be generated continuously. It will be lost.
- the sustain pulse duration is too long, the repetition cycle of the sustain pulse becomes long, and it is not possible to apply the required number of sustain pulses to the display electrode pair. Therefore, it is desirable to set the sustain pulse duration to about 800 nsec to 1500 nsec for practical use. And, in the present embodiment, sufficient wall voltage can be accumulated for periods T3 and T6 corresponding to the sustain pulse duration, and the time for which the required number of sustain pulses can be secured is 850 nsec to 1250 nsec. I will speak.
- period T2 which is the rise time of the sustain pulse using power recovery units 110, 210, and the time obtained by doubling ⁇ 5
- period ⁇ 3 which is the duration of the sustain pulse.
- the rise time of the sustain pulse may be set to be longer than the period ⁇ 3 and ⁇ 6.
- the resonance period of the inductors Ll l, L21 and the interelectrode capacitance C p to be twice or more of the period T2 which is the rise time of the sustain pulse, or more than twice ⁇ 5, the sustain pulse rise time period ⁇ 2, 5
- the voltage applied to the display electrode pair can be prevented from decreasing in Therefore, by setting the resonance period to be longer than the period ⁇ 3 and ⁇ 6 that is the sustain pulse duration, the effects of reducing reactive power and improving the light emission efficiency can be obtained. More preferably, the time obtained by multiplying the resonance period by 0.5 to 0.75 may be set to be longer than the periods ⁇ 3 and ⁇ 6.
- the maintenance cycle is one cycle from period T1 to period 6.
- the overlapping period from period t2a to time t2b and period T4 from period t1 to period t2 overlap with each other.
- the maintenance period is shortened by the overlapping period. Therefore, although the driving time of one field is shortened, the number of sustain pulses is increased by raising the luminance magnification using the shortened driving time, and the peak luminance of the display image is raised.
- inductors L11 and L21 that determine the resonance cycle of rising of the sustain pulse, and the resonance cycle of falling force S of the sustain pulse are determined.
- Inductors L12 and L22 are provided independently. Therefore, when changing the rise time and fall time of the sustain pulse, the inductors Ll l, L2
- inductors L12 and L22 By changing the values of inductors L12 and L22, various specifications of the panel can be met. In particular, in the case where the rise time is extended to make the rise of the sustain pulse gentler as described above, it is desirable that the resonance cycle of the rise of the sustain pulse and the resonance cycle of the fall force S can be set independently. Furthermore, the power recovery unit 11 By independently arranging the inductors Ll l and L21 of the 0 and 210 and the inductors L12 and L22, the amount of heat generation per inductor can be halved, and the effect of reducing the thermal resistance of the inductor is also obtained. Be
- the resonance period of rising power S of the sustaining pulse in power recovery units 110 and 210 and the resonance period of falling are set to the same value, and inductors Ll l and L21 and inductors L12 and L22 have the same inductance. There is.
- the periods T7, T8, T9 and T10 in FIG. 7 are the same as T1, T2, T3 and T4 described above, respectively, so the description is omitted.
- the period T11 to the period T13 will be described using FIG. 7 again.
- the switching element Q11 is turned ON at time 12 before the voltage of the scanning electrode 22 rises to near Vs. Then, the scanning electrode 22 is directly connected to the power source VS through the switching element Q13 and is clamped to the voltage Vs.
- the phase difference is the narrow pulse shape until the voltage Vs for generating the final sustain discharge is applied to the scan electrode 22 and the voltage Vel is applied to the sustain electrode 23, and the pulse width is the erase position It is a difference Thl. Therefore, the sustaining discharge that occurs last is a discharge that can be called erasing discharge.
- data electrode 32 is held at 0 V at this time, and charged particles by discharge are used to reduce the wall charge so as to reduce the potential difference between the voltage applied to data electrode 32 and the voltage applied to scan electrode 22. As it is formed, a positive wall voltage is accumulated on the data electrode 32.
- the time period T12 during which the erasing phase difference Th1 is set is set to 350 nsec. Furthermore, the period T11, which is the rise time of the last sustain pulse of the sustain period, is set to 650 nsec, and is shorter than the 900 nsec of the period T2, period T5, which is the rise time of other sustain pulses.
- the erase phase difference Thl is set to 350 nsec, and the rise time of the last sustain pulse in the sustain period is higher than the rise time of the other sustain pulses.
- the reasons for setting the short 650 nsec will be explained.
- the present inventors have found that the rise time at the erase phase difference Thl and the last sustain pulse is An experiment was conducted to investigate the relationship between the voltage V.sub.el applied to the sustain electrode 23 and the sustain electrode 23 in the initialization period. If the voltage Ve 1 applied to the sustain electrode 23 is set too high, a write pulse is applied to cause a write pulse! If a write discharge occurs even in the discharge cell, a malfunction may occur. Is desirable to widen the driving margin.
- FIG. 9 is a diagram showing the relationship between the voltage Vel required to perform a normal selective initializing operation in the initializing period, the erase phase difference Thl, and the rise time of the last sustain pulse.
- the abscissa represents the erasing phase difference Th
- the ordinate represents the voltage Vel.
- the present inventors set the normal selective initializing operation by shortening the rise time of the penultimate maintenance pulse, ie, the period T8 in FIG. 7, to be shorter than 900 nse C. It has been found experimentally that the voltage Vel necessary to perform can be further lowered.
- FIG. 10 is a diagram showing the relationship between the rise time of the second last sustain pulse and the voltage Vel.
- the horizontal axis shows the rise time of the second last sustain pulse, and the vertical axis shows the voltage Vel.
- the rise time of the second last maintenance pulse is set to 750 nsec in consideration of the utilization efficiency of the recovered power and the like.
- the sustain electrode application voltage Ve1 required to generate a normal setup discharge is further lowered to realize a further increase in drive margin.
- lighting rate a ratio (hereinafter abbreviated as “lighting rate”) to a number of discharge cells in which the number of discharge cells in which a sustain discharge occurs is given and a sustain period, and a sustain discharge.
- lighting voltage the required sustaining pulse applied voltage
- FIG. 11 is a diagram showing the relationship between the lighting rate and the lighting voltage in the present embodiment, with the maintenance cycle as a parameter.
- the vertical axis represents the lighting voltage
- the horizontal axis represents the lighting rate.
- the maintenance period is 3.8 ⁇ s and 4.8 ⁇ s. From this experiment, it was found that the lighting voltage decreased when the lighting rate was low, and the lighting voltage increased when the lighting rate was high. In addition, it was also found that the lighting voltage rises when the maintenance cycle becomes short and the lighting voltage falls when the maintenance cycle becomes long.
- the lighting voltage increases as the lighting rate becomes higher, for example, when the lighting rate becomes higher, the discharge current increases, and the voltage drop due to the resistance component of the display electrode pair becomes larger, and the distance between the display electrodes of the discharge cell increases. Since the voltage applied to the light source is reduced, it can be considered that the lighting voltage is apparently increased.
- the sustaining pulse duration is shortened when the sustaining period is shortened, and the wall voltage stored along with the sustaining discharge is reduced. It is considered that the sustaining pulse voltage to be applied to is increased.
- the APL is low, the luminance weight is large when displaying an image, and the lighting rate of the sub-field is low. Therefore, as described above, the lighting voltage also decreases. This indicates that when displaying a low-light image of APL, it is possible to reduce the size of the luminance weight and the sustain period of the sub-field.
- the present embodiment when APL is low, driving is performed in which the sustain pulse duration time of the luminance weight is large! / ⁇ subfield when the image is displayed is shortened. Power!
- the overlap period between the rise and fall of the sustain pulse is lengthened and the fall time of the sustain pulse is shortened to further maintain the image.
- the cycle has been shortened.
- the reactive power tends to increase if the overlap period of the sustain pulse is made too long or if the fall time of the sustain pulse is too short, in the present embodiment, the discharge characteristics of the panel, its variation, etc.
- the overlap period of the sustain pulse is set to 250 nsec to 450 nsec, and the fall time of the sustain pulse is set to 650 nsec to 850 nsec.
- the shortened driving time Increase the brightness ratio to increase the number of sustain pulses and increase the peak brightness of the displayed image.
- FIG. 12 is a diagram showing the relationship between the APL of the plasma display device in the present embodiment and the shape of the sustain pulse.
- the overlap period of the sustain pulse of the eighth SF to the tenth SF is 450 nsec
- the fall time of the sustain pulse is 650 nsec
- the sustain period is 3900 nsec.
- the overlap period of the 9th SF and 10th SF sustain pulses is 400 nsec
- the fall period of the sustain pulses is 700 nsec
- the sustain period is 4300 nsec. .
- the overlap period of the 9th SF and 10th SF sustain pulse is 350 nsec
- the fall period of the sustain pulse is 750 nsec
- the sustain period is 4700 nsec.
- the overlap period of the sustain pulse of the 10th SF is 300 nsec
- the fall time of the sustain pulse is 800 nsec
- the sustain cycle is 5100 sec sec.
- the overlap period of the sustain pulse in the 10th SF is 250 nsec
- the fall time of the sustain pulse is 850 nsec
- the sustain cycle is 5500 nsec. This makes it possible to increase the luminance magnification up to 4.3 times.
- the sustain period of the subfield having a large luminance weight is shortened.
- the peak magnification of the display image is increased by increasing the number of sustain pulses by raising the luminance magnification using the shortened driving time.
- the reduced driving time may be used to increase the number of display gradations to improve the display quality of the image, or to increase the all-cell initializing operation to further stabilize the discharge.
- the address pulse voltage Vd must be set high to ensure that the address discharge occurs. It was strong. This is considered to be due to the fact that the wall voltage accumulated on the data electrode is insufficient due to the erase discharge in period T12 of FIG. 7, and the write pulse voltage Vd needs to be increased to compensate for the shortage in the address period. Therefore, the inventors made the write voltage V As a result of studying to lower d, it is possible to restore the address pulse voltage by extending the duration of the sustain pulse generating the sustain discharge immediately before the erase discharge, ie, the period T8 in FIG. I found out.
- FIG. 13 is a diagram showing experimental results in which the relationship between the sustain period and duration and the write voltage Vd required to reliably generate the write discharge is investigated.
- the sustain period is reduced from 5 ⁇ sec to 4 ⁇ sec, the write voltage rises from 62 V to 66.5 V. Even if the power sustain period is 4 sec, the sustain pulse duration just before the erase discharge is maintained.
- the write voltage can be returned to 62 V by extending the maintenance period to 5 seconds or more.
- the sustain pulse immediately before the erase discharge is added to the sustain pulse, and the duration of the two or three previous sustain pulses is extended, and the write voltage does not decrease further.
- the duration of the sustain pulse just before the erase discharge may be extended, but if there is enough drive time, the duration of the last two or three sustain pulses is extended. It does not matter.
- the sustain pulse voltage Vs must of course be high enough to ensure that the sustain discharge occurs, but as described in FIG. 6, the operation of the power recovery units 110 and 210 is described.
- the sustain pulse voltage Vs is set low enough to disperse the discharge current. If the voltage Vs is too high, a sustaining pulse is applied to the scanning electrode 22 or the sustaining electrode 23 using the power recovery units 110 and 210, and a strong, sustaining discharge is generated between the periods T2 and T5. As a result, a large discharge current flows. Since the impedance in the power recovery units 110 and 210 is high, a voltage drop occurs when a large discharge current flows, and the voltage marked on the scanning electrode 22 or the sustaining electrode 23 drops significantly and the sustaining discharge becomes unstable. As a result, there is a risk that the image display quality may be degraded such that the light emission luminance is not uniform in the display area.
- sustain pulse voltage Vs is set to 190V. This voltage value itself is particularly low V, not a value compared to the sustaining pulse voltage of a general plasma display device, but the panel 10 used in the present embodiment has a xenon partial pressure of 10%. To increase the luminous efficiency, and hence the discharge start voltage between the display electrode pair is also increased. Therefore, the voltage value of sustain pulse voltage Vs is relatively smaller than the discharge start voltage. That is, the power recovery units 110 and 210 are used to In the periods T2 and ⁇ 5 in which pressure is applied, no sustain discharge occurs, or even if sustain discharge occurs, the voltage applied to the display electrode pair is reduced due to the voltage drop due to the discharge current, and the sustain discharge is not performed. Strong enough to be stable, and not a sustain discharge.
- the light emission efficiency is high, and driving becomes possible.
- the voltage value of the sustain pulse voltage relative to the discharge start voltage is set low. ing. Therefore, if the wall voltage is not reliably accumulated by the sustaining discharge, the wall voltage may be insufficient and the sustaining discharge may not occur continuously. In particular, if the discharge characteristics of the discharge cells constituting the display screen are uneven, the possibility of occurrence of such a problem tends to be high. Therefore, the rise time of the first sustain pulse may be set shorter than the rise time of the other sustain pulses so that sufficient wall voltage is surely accumulated in the first sustain discharge of the sustain period.
- FIG. 14 is an example of a drive voltage waveform diagram applied to each electrode of panel 10.
- the period T5f which is the rise time of the first sustain pulse
- the period T5 which is the rise time of the normal sustain pulse
- a strong sustain discharge is generated to ensure the accumulation of the wall voltage.
- the panel has a certain degree of variation in discharge characteristics of the discharge cell, stable sustain discharge can be generated continuously.
- the period T2 which is the rise time of the sustain pulse and the power period T2 and ⁇ 5 described with 9005 being 900 nsec are two minutes of the resonance period. It may be less than 1 and longer than the periods 3, 2 of the maintenance pulse duration for which the periods 2, 2 are doubled.
- the present invention is not limited to this configuration, and the same configuration can be used for power supply and for power recovery. Also as a configuration using an inductor of.
- the voltage waveform of the last sustain pulse in the sustain period is not limited to the above-described voltage waveform. Further, in the present embodiment, even if the xenon partial pressure of the discharge gas is 10%, the xenon partial pressure may be set to a driving voltage according to the panel.
- the specific numerical values used in the present embodiment are merely an example, and the optimum values may be appropriately selected according to the characteristics of the panel, the specification of the plasma display device, and the like. It is desirable to set to.
- the method of driving a panel and the plasma display device of the present invention can further reduce power consumption while increasing the brightness of the panel, and is useful as a method of driving a panel and a plasma display device.
Description
Claims
Priority Applications (4)
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KR1020087007763A KR100930776B1 (ko) | 2006-02-14 | 2007-02-13 | 플라즈마 디스플레이 패널의 구동 방법 및 플라즈마디스플레이 장치 |
JP2008500496A JP5045665B2 (ja) | 2006-02-14 | 2007-02-13 | プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置 |
US12/088,784 US20090278863A1 (en) | 2006-02-14 | 2007-02-13 | Plasma display panel drive method and plasma display device |
CN2007800010834A CN101351832B (zh) | 2006-02-14 | 2007-02-13 | 等离子体显示面板的驱动方法和等离子体显示装置 |
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JP2006-036325 | 2006-02-14 | ||
JP2006036325 | 2006-02-14 |
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US (1) | US20090278863A1 (ja) |
JP (1) | JP5045665B2 (ja) |
KR (1) | KR100930776B1 (ja) |
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WO2009098771A1 (ja) * | 2008-02-07 | 2009-08-13 | Hitachi, Ltd. | プラズマディスプレイ装置及びプラズマディスプレイパネルの駆動方法 |
CN102074185A (zh) * | 2009-12-31 | 2011-05-25 | 四川虹欧显示器件有限公司 | 等离子显示器的图像信号的处理方法及装置 |
CN103903552A (zh) * | 2014-03-14 | 2014-07-02 | 四川虹欧显示器件有限公司 | 一种等离子显示器驱动方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000322025A (ja) * | 1999-05-14 | 2000-11-24 | Nec Corp | プラズマディスプレイ装置 |
JP2003076321A (ja) * | 2001-06-20 | 2003-03-14 | Matsushita Electric Ind Co Ltd | プラズマディスプレイパネル表示装置とその駆動方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4866349A (en) * | 1986-09-25 | 1989-09-12 | The Board Of Trustees Of The University Of Illinois | Power efficient sustain drivers and address drivers for plasma panel |
JP2004177980A (ja) * | 1997-07-16 | 2004-06-24 | Mitsubishi Electric Corp | プラズマディスプレイ装置 |
TW518555B (en) * | 2000-04-21 | 2003-01-21 | Matsushita Electric Ind Co Ltd | Gray-scale image display device that can reduce power consumption when writing data |
JP2002108280A (ja) * | 2000-10-04 | 2002-04-10 | Nec Corp | Ac型プラズマディスプレイパネルの駆動方法 |
TWI256031B (en) * | 2001-06-20 | 2006-06-01 | Matsushita Electric Ind Co Ltd | Plasma display panel display device and related drive method |
JP2004061863A (ja) * | 2002-07-29 | 2004-02-26 | Sanyo Electric Co Ltd | プラズマディスプレイ表示装置 |
US7463218B2 (en) * | 2002-10-02 | 2008-12-09 | Lg Electronics Inc. | Method and apparatus for driving plasma display panel |
EP1437705A1 (en) * | 2003-01-10 | 2004-07-14 | Deutsche Thomson-Brandt Gmbh | Method for optimizing brightness in a display device and apparatus for implementing the method |
US20050078062A1 (en) * | 2003-09-27 | 2005-04-14 | Lg Electronics Inc. | Method and apparatus of driving a plasma display panel |
KR20050049668A (ko) * | 2003-11-22 | 2005-05-27 | 삼성에스디아이 주식회사 | 플라즈마 디스플레이 패널 구동방법 |
-
2007
- 2007-02-13 US US12/088,784 patent/US20090278863A1/en not_active Abandoned
- 2007-02-13 KR KR1020087007763A patent/KR100930776B1/ko not_active IP Right Cessation
- 2007-02-13 CN CN2007800010834A patent/CN101351832B/zh not_active Expired - Fee Related
- 2007-02-13 JP JP2008500496A patent/JP5045665B2/ja not_active Expired - Fee Related
- 2007-02-13 WO PCT/JP2007/052474 patent/WO2007094295A1/ja active Application Filing
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JP2000322025A (ja) * | 1999-05-14 | 2000-11-24 | Nec Corp | プラズマディスプレイ装置 |
JP2003076321A (ja) * | 2001-06-20 | 2003-03-14 | Matsushita Electric Ind Co Ltd | プラズマディスプレイパネル表示装置とその駆動方法 |
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KR20080042913A (ko) | 2008-05-15 |
KR100930776B1 (ko) | 2009-12-09 |
US20090278863A1 (en) | 2009-11-12 |
CN101351832A (zh) | 2009-01-21 |
CN101351832B (zh) | 2011-11-16 |
JPWO2007094295A1 (ja) | 2009-07-09 |
JP5045665B2 (ja) | 2012-10-10 |
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