WO2007058014A1 - 液晶表示装置およびその駆動方法 - Google Patents
液晶表示装置およびその駆動方法 Download PDFInfo
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- WO2007058014A1 WO2007058014A1 PCT/JP2006/318121 JP2006318121W WO2007058014A1 WO 2007058014 A1 WO2007058014 A1 WO 2007058014A1 JP 2006318121 W JP2006318121 W JP 2006318121W WO 2007058014 A1 WO2007058014 A1 WO 2007058014A1
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- data signal
- signal line
- liquid crystal
- switches
- crystal display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
Definitions
- Liquid crystal display device and driving method thereof Liquid crystal display device and driving method thereof
- the present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device that performs display based on a phase expanded video signal and a driving method thereof.
- FIG. 14 is a diagram showing a configuration of a liquid crystal display device that performs display based on a four-phase developed video signal.
- the pixel array 1 includes (m X n) display elements P, n scanning signal lines Gl to Gn, and m data signal lines Sl to Sm. Yes.
- the scanning signal line driving circuit 2 selectively activates the scanning signal lines Gl to Gn in order based on the gate clock GCK and the gate start pulse GSP.
- the data signal line driving circuit 81 drives the data signal lines Sl to Sm based on the source clock SCK and its inverted signal, the source start pulse SSP, and the four-phase expanded video signals V1 to V4.
- the mZ4 flip-flops 82 are connected in series to form an mZ4 stage shift register.
- the switch control signals C1 to Cq output from the shift register are selectively activated in order (for example, high level).
- the data signal lines Sl to Sm are grouped by four.
- the j-th data signal line included in the i-th group (where i is an integer from 1 to mZ4 and j is an integer from 1 to 4) is given by the switch control signal Ci to the control terminal. It is connected to the signal line that propagates the video signal Vj through the switch 83.
- the four switches 83 controlled by the switch control signal Ci become conductive when the switch control signal Ci is at a high level.
- each of the four data signal lines included in the i-th group has a video signal. Numbers V1 to V4 are applied.
- the switch control signal Ci changes to the low level, the voltages of the four data signal lines included in the i-th group reach the voltage levels of the video signals V1 to V4, respectively.
- the switch control signals Cl to Cq sequentially become high level one by one (see FIG. 15). For this reason, for example, the timing at which the switch control signal C2 changes to high level is almost simultaneously with the timing at which the switch control signal C1 changes to low level. After the switch control signal C1 changes to the low level, the data signal lines S1 to S4 enter the high impedance state.
- a parasitic capacitance 84 is generated between the adjacent data signal lines Sl to Sm. For this reason, when the video signal VI starts to be applied to the data signal line S5 after the data signal line S4 enters the high impedance state, the effect also reaches the data signal line S4 via the parasitic capacitance 84. As a result, as shown in FIG. 18, the voltage of the data signal line S4 fluctuates (increases or decreases) by ⁇ from the originally desired level.
- the voltage held in the last data signal line (for example, S4 or S8) in the group is Fluctuates under the influence of the voltage applied to the first data signal line in the next group (for example, S5 and S9). Since this phenomenon occurs every predetermined number of data signal lines (four in the above example), it is visually recognized as vertical stripes (hereinafter referred to as vertical stripes) on the screen.
- the period during which the switch control signals Cl to Cq are at the high level overlaps by one cycle (see FIG. 16). For this reason, for example, even when the switch control signal C2 changes to high level and the video signal VI starts to be applied to the data signal line S5, the data signal line S4 is not in a high impedance state. S4 power The pressure does not fluctuate. Therefore, according to the second method, the problem of vertical stripes can be solved.
- the levels of the video signals V1 to V4 at the time when the switch control signal C1 changes to the low level are affected by the data of the previous and subsequent cycles, and the data signal lines S1 to S4 May not match the voltage level to be applied. This phenomenon occurs in the vicinity of the place where the voltage level of the video signal changes, with a predetermined number or less of data signal lines (4 or less in the above example). It is visually recognized as a ghost.
- Patent Document 1 discloses a liquid crystal display device shown in FIG.
- mZ Two flip-flops 92 are connected in series to form an mZ2-stage shift register.
- a sampling pulse that does not overlap is generated for the switch 93 connected to the same video signal line, and the switch 93 adjacent to the switch 93 is generated.
- overlapping sampling pulses are generated.
- Patent Document 1 Japanese Unexamined Patent Publication No. 2000-267616
- the flip-flop 92 that is twice as large as the liquid crystal display device 80 shown in FIG. 14 is arranged along one side in the row direction of the pixel array 1. It has a configuration. Further, the source clock SCK having a frequency twice that of the liquid crystal display device 80 is supplied to the liquid crystal display device 90, and the flip-flop 92 of the liquid crystal display device 90 is compared with the flip-flop 82 of the liquid crystal display device 80. Operates at twice the speed (see Figure 15, Figure 16 and Figure 20). For this reason, the size of each flip-flop 92 is also larger than that of the flip-flop 82.
- the liquid crystal display device 90 has a configuration in which the flip-flop 92 having a large size is arranged along one side in the row direction of the pixel array 1.
- the width of one side (below, called the picture frame) is thicker than the other sides. Further, in the liquid crystal display device 90, the power consumption increases as the flip-flop 92 operates at high speed.
- an object of the present invention is to provide a liquid crystal display device in which a vertical stripe is not generated on a screen and a frame is narrow.
- a first aspect of the present invention is a liquid crystal display device that performs display based on a phase-expanded video signal
- a plurality of scanning signal lines connected in common to the display elements arranged in the same row, and a display element arranged in the same column
- a scanning signal line driving circuit for selectively activating the scanning signal lines
- the pixel array is arranged along one side in the row direction of the pixel array and is a part of the video signal.
- a first data signal line driving circuit that drives a first data signal line that is a part of the data signal line based on the video signal of 1;
- the pixel array is arranged along the other side of the pixel array in the row direction, and is the remaining part of the video signal.
- a second data signal line driving circuit for driving a second data signal line, which is the remaining part of the data signal line, based on the video signal of 2.
- the first data signal line driving circuit controls a plurality of first switches for switching whether or not to apply the first video signal to the first data signal lines, and the first switch.
- a first switch control circuit
- the second data signal line driving circuit controls a plurality of second switches for switching whether or not to apply the second video signal to the second data signal lines, and the second switch.
- a second switch control circuit
- the conduction period does not overlap between the switches to which the same video signal is supplied, and at least a part of the conduction period overlaps between the switches corresponding to the adjacent data signal lines. As described above, the first and second switches are controlled.
- a second aspect of the present invention is the first aspect of the present invention,
- the data signal lines included in each group belong to different categories with the group boundary adjacent to each other.
- the first data signal line and the second data signal line are divided into
- the first switch control circuit controls the switches corresponding to the first data signal lines included in the same group among the first switches to be sequentially turned on in sequence, and the second switch control.
- the circuit controls the switches corresponding to the second data signal lines included in the same group among the second switches to be sequentially turned on at a timing different from that of the first switch control circuit. It is characterized by doing.
- a third aspect of the present invention is the second aspect of the present invention.
- the first switch control circuit includes a first shift register having stages equal to the number of groups of the data signal lines,
- the second switch control circuit includes a second shift register having the same number of stages as the number of groups of the data signal lines,
- the first and second shift registers operate at different timings.
- a fourth aspect of the present invention is the third aspect of the present invention.
- the first and second shift registers operate at a timing shifted by a half cycle of a cycle in which the video signal changes.
- a fifth aspect of the present invention is the first aspect of the present invention.
- the conduction periods of the first and second switches are shifted by a half cycle of the cycle in which the video signal changes, and both have the same length as the cycle.
- a sixth aspect of the present invention is the fifth aspect of the present invention.
- the first and second video signals change at a timing shifted by a half period of the period.
- a seventh aspect of the present invention is the first aspect of the present invention.
- An eighth aspect of the present invention is the first aspect of the present invention.
- the pixel array, the scanning signal line driving circuit, and the first and second data signal line driving circuits are formed monolithically on a single insulating substrate.
- a ninth aspect of the present invention is the first aspect of the present invention.
- the length of the signal line for transmitting the first video signal to the first data signal line driving circuit is substantially equal to the length of the signal line for transmitting the second video signal to the second data signal line driving circuit. It is characterized by that.
- the tenth aspect of the present invention is the same as the plurality of display elements arranged in the row direction and the column direction, and the plurality of scanning signal lines commonly connected to the display elements arranged in the same row.
- the first video signal which is a part of the video signal is a part of the data signal line. Controlling a plurality of first switches for switching whether or not to apply to the first data signal line;
- the second video signal which is the remaining part of the video signal is the remaining part of the data signal line.
- a plurality of second switches for switching whether or not a force is applied to the second data signal line, and
- the conduction period does not overlap between switches to which the same video signal is supplied, and at least the conduction period is between switches corresponding to adjacent data signal lines.
- the first and second switches are controlled so as to partially overlap each other.
- the first and second switches are controlled so that the conduction periods do not overlap between the switches to which the same video signal is supplied. Gatsutsu Thus, it is possible to prevent a ghost that occurs when switches supplied with the same video signal are conducted simultaneously.
- the first and second switches are controlled so that at least a part of the conduction period overlaps between the switches corresponding to the adjacent data signal lines. Therefore, it is possible to prevent vertical streaks caused by the parasitic capacitance generated between adjacent data signal lines. Furthermore, by dividing the data signal line driver circuit along two opposing sides of the pixel array, it is possible to prevent one side of the frame from becoming thicker than the other side.
- the group boundaries are defined. Adjacent data signal lines are driven at different timings.
- the conduction periods do not overlap between switches to which the same video signal is supplied, and the conduction periods coincide between switches corresponding to adjacent data signal lines, or some conduction periods overlap.
- the first and second switches can be controlled.
- the first and second switch control circuits operate at a timing shifted by a half cycle of the cycle in which the video signal changes. Between the corresponding switches, the conduction periods coincide or overlap by the half period of the period when the video signal changes.
- the switch corresponding to the adjacent data signal line is provided. Between switches, the conduction periods are the same, or they overlap by the half period of the period in which the video signal changes.
- the seventh aspect of the present invention since the circuit amount of the first data signal line driving circuit and the circuit amount of the second data signal line driving circuit are substantially equal, the first data Signal line drive times
- the width of the side of the frame where the path is arranged can be made equal to the width of the side of the frame where the second data signal line driving circuit is arranged.
- the capacitive loads and resistance values of the two signal lines are substantially equal. Therefore, the charging effect of the first data signal line by the first data signal line driving circuit is substantially the same as the charging effect of the data signal line by the second data signal line driving circuit. Therefore, it is possible to suppress variations in charging associated with driving data signal lines from both sides of the pixel array.
- FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.
- FIG. 2 is a timing chart of the liquid crystal display device shown in FIG.
- FIG. 3 is a diagram showing an example of mounting the liquid crystal display device shown in FIG.
- FIG. 4 is a diagram showing another example of mounting the liquid crystal display device shown in FIG.
- FIG. 5 is a timing chart of a liquid crystal display device according to a modification of the first embodiment of the present invention.
- FIG. 6 is a diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.
- FIG. 7 is a timing chart of the liquid crystal display device shown in FIG.
- FIG. 8 is a diagram showing a configuration of a liquid crystal display device according to a third embodiment of the present invention.
- FIG. 9 is a timing chart of the liquid crystal display device shown in FIG.
- FIG. 10 is a diagram showing a configuration of a liquid crystal display device according to a fourth embodiment of the present invention.
- FIG. 11 is a timing chart of the liquid crystal display device shown in FIG.
- FIG. 12 is a diagram showing a configuration of a liquid crystal display device according to a fifth embodiment of the present invention.
- FIG. 13 is a timing chart of the liquid crystal display device shown in FIG.
- FIG. 14 is a diagram showing a first configuration of a conventional liquid crystal display device.
- FIG. 15 is a first timing chart of the liquid crystal display device shown in FIG.
- FIG. 16 is a second timing chart of the liquid crystal display device shown in FIG.
- FIG. 17 is a diagram showing parasitic capacitance generated between data signal lines of a liquid crystal display device.
- FIG. 18 is a diagram showing how the voltage of the data signal line fluctuates in the liquid crystal display device shown in FIG.
- FIG. 19 is a diagram showing a second configuration of a conventional liquid crystal display device.
- FIG. 20 is a timing chart of the liquid crystal display device shown in FIG.
- ⁇ is an integer of 1 or more
- m is a multiple of 8
- i is an integer of 1 to mZ4
- j is an integer of 1 to mZ8.
- mZ4 may be described as q and mZ8 as r.
- FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to the first embodiment of the present invention.
- a liquid crystal display device 10 shown in FIG. 1 includes a pixel array 1, a scanning signal line driving circuit 2, a first data signal line driving circuit 11, and a second data signal line driving circuit 12.
- the liquid crystal display device 10 performs monochrome multi-gradation display based on the video signals V1 to V4 expanded in four phases.
- the pixel array 1 includes (!!!!) display elements! 3 , n scanning signal lines Gl to Gn, and m data signal lines Sl to Sm. There are m elements P arranged in the row direction and n elements in the column direction, and the display elements arranged in the same row are the scanning signal lines Gl to Gn. Commonly connected to either. The display elements arranged in the same column are connected in common to the data signal lines Sl to Sm.
- the scanning signal line driving circuit 2 selectively activates the scanning signal lines Gl to Gn in order based on the gate clock GCK and the gate start pulse GSP. More specifically, the scanning signal line drive circuit 2 has an n-stage shift register. The serial data input terminal of this shift register is supplied with a gate start pulse GSP that is activated (for example, high level) once per frame time. The clock terminal is supplied with a gate clock GCK that changes (for example, rises) in a predetermined direction every line time. The scanning signal lines Gl to Gn are activated or deactivated according to the output signal of each stage of the shift register. If the gate clock GCK rises while the gate start pulse GSP is active, the scanning signal line G1 becomes active for one line time immediately after that. After that, the scanning signal lines that are activated are switched in the order of G2, G3,..., Gn every line time.
- the data signal lines Sl to Sm are driven by the first data signal line drive circuit 11 and the second data signal line drive circuit 12.
- the first data signal line driving circuit 11 is arranged along one side of the pixel array 1 in the row direction (the upper side of the pixel array 1 in FIG. 1).
- the second data signal line driving circuit 12 is arranged along the other side of the pixel array 1 in the row direction (the lower side of the pixel array 1 in FIG. 1). In this way, the data signal lines Sl to Sm are driven by two circuits provided on opposite sides across the pixel array 1.
- the first data signal line driving circuit 11 is supplied with a source start pulse SSPA, a source clock SCKA and its inverted signal, and video signals VI and V2 which are part of the video signals V1 to V4.
- the second data signal line driving circuit 12 is supplied with the source start pulse SSPB, the source clock SCKB and its inverted signal, and the video signals V3 and V4 which are the remainder of the video signals V1 to V4.
- the mZ4 flip-flops 13 are connected in series to form an mZ4 stage shift register (hereinafter referred to as a first shift register).
- a source start pulse SSPA is applied to the serial data input terminal of the first shift register, and a source clock SCKA and its inverted signal are applied to the clock terminal.
- the source start pulse SSPA is activated (for example, a noise level) once per line time, and the source clock SCKA and its inverted signal change in the same cycle as the video signals VI and V2 change ( That is, it rises or falls once per cycle).
- the i-th stage output signal of the first shift register is referred to as a switch control signal CAi.
- the switch control signal CA1 goes high in the next cycle. After that, the switch control signal that goes high switches in the order of CA2, CA3, ..., CAq every cycle.
- the first shift register functions as a control circuit for the switch 15.
- the mZ4 flip-flops 14 are connected in series to form an mZ4 stage shift register (hereinafter referred to as a second shift register).
- a source start pulse SSPB is applied to the serial data input terminal of the second shift register, and a source clock SCKB and its inverted signal are applied to the clock terminal.
- the source start pulse SSPB is a signal delayed by a half cycle from the source start pulse SSPA, and the source clock SCKB and its inverted signal are signals delayed by a half cycle from the source clock SCKA and its inverted signal, respectively.
- the i-th stage output signal of the second shift register is referred to as a switch control signal CBi. If the source clock SCKB rises while the source start pulse SSPB is active, the switch control signal CB1 goes high in the next cycle. After that, the switch control signal that goes high switches in the order of CB2, CB3, ..., CBq every cycle.
- the second shift register functions as a control circuit for the switch 16.
- the video signals V 1 to V 4 the data signal lines Sl to Sm, the flip-flops 13 and 14, and the switches 15 and 16 are associated as follows.
- Data signal line Sl to Sm are grouped by 4 (the number of video signals) according to the arrangement order, thereby forming mZ4 groups.
- the four data signal lines included in each group are two, one driven by the first data signal line drive circuit 11 and the other driven by the second data signal line drive circuit 12. Divided.
- the number of data signal lines driven by the first data signal line driving circuit 11 is the same as the number of data signal lines driven by the second data signal line driving circuit 12.
- the four data signal lines included in the i-th group are referred to as Sil, Si2, Si3, and Si4 in the arrangement order.
- the first data signal line driving circuit 11 is provided with two switches 15 (hereinafter referred to as first and second switches), and the second data signal
- the line drive circuit 12 is also provided with two switches 16 (hereinafter referred to as third and fourth switches).
- the first switch is provided between the signal line propagating the video signal VI and the data signal line Sil. That is, a signal line for propagating the video signal VI is connected to one end of the first switch, and a data signal line Sil is connected to the other end.
- the second switch is provided between the signal line for transmitting the video signal V2 and the data signal line Si2.
- the switch control signal CAi output from the i-th stage of the first shift register is given to the control terminals of the first and second switches.
- the first and second switches switch whether to apply the video signals VI and V2 to the data signal lines Sil and Si2 according to the switch control signal CAi.
- the third switch is provided between the signal line propagating the video signal V3 and the data signal line Si3.
- the fourth switch is provided between the signal line that propagates the video signal V4 and the data signal line Si4.
- the switch control signal CBi output from the i-th stage of the second shift register is given to the control terminals of the third and fourth switches.
- the third and fourth switches switch whether to apply the video signals V3 and V4 to the data signal lines Si3 and Si4 according to the switch control signal CBi.
- the switch control signal CAi when the switch control signal CAi is at the high level, the video signals VI and V2 are applied to the data signal lines Sil and Si2 via the switch 15, respectively.
- the switch control signal CBi When the switch control signal CBi is at high level, the data signal lines Si3 and Si4 Video signals V3 and V4 are applied via H16.
- the period during which the switch control signal CAi is high and the period during which the switch control signal CBi is high are shifted by a half cycle.
- the first data signal line drive circuit 11 controls the switches 15 corresponding to the data signal lines included in the same group to be in a conductive state in order, and the second data signal line drive circuit 12 Then, the switches 16 corresponding to the data signal lines included in the same group are controlled to be sequentially turned on collectively at a timing different from that of the first data signal line driving circuit 11.
- the conduction period of switch 15 and the conduction period of switch 16 are both shifted by one half cycle, which is one cycle.
- FIG. 2 is a timing chart of the liquid crystal display device 10.
- the switch control signals C Al, CA2,..., CAq become high level one by one in one cycle.
- the switch control signals CB1, CB2,..., CBq go to the high level one by one in one cycle. Become.
- the source start pulse SSPB, the source clock SCKB, and the inverted signal thereof are signals delayed by a half cycle from the source start pulse SSPA, the source clock SCKA, and the inverted signal, respectively. Therefore, the switch control signals CB1, CB2,..., CBq are signals delayed by half a cycle from the switch control signals CA1, CA2,. As a result, the switch control signals CAl to CAq, CBl to CBq go to CA1, CB1, CA2, CB2, CA3, CB3,... ⁇ CAq, CBq in order of half cycle, and become high level by cycle. .
- the voltages of the data signal lines Sil and Si2 reach the levels of the video signals VI and V2 while the switch control signal CAi is at the high level, and do not change after the switch control signal CAi changes to the low level. Therefore, the voltages of the data signal lines Sil and Si2 are determined by the levels of the video signals VI and V2 at the time when the switch control signal CAi changes to the same level. Similarly, the voltages of the data signal lines Si3 and Si4 are determined by the levels of the video signals V3 and V4 at the time when the switch control signal CBi changes to the low level.
- the video signal VI is generated every cycle from the cycle immediately after the source start pulse SSPA is activated. It changes in the order of Dl, D5, D9,.
- the video signal V2 changes in the order of D2, D6, D10, ... at the same timing as the video signal VI.
- the video signal V3 changes in the order of D3, D7, Dl,... Every cycle from the cycle immediately after the source start pulse SSPB becomes active.
- the video signal V4 changes in the order of D4, D8, D12,... At the same timing as the video signal V3.
- the video signals V3 and V4 change at a timing delayed by half a cycle from the video signals VI and V2.
- the first data signal line driving circuit 11 applies the level Dl to the data signal lines Sl, S2, S5, S6,. Apply video signals D2, D5, D6,.
- the second data signal line driving circuit 12 applies video signals of levels D3, D4, D7, D8,... To the data signal lines S3, S4, S7, S8,.
- the first data signal line drive circuit 11 correctly drives a part of the data signal line (Sl, S2, S5, S6, etc.), and the second data signal line drive circuit 12 is connected to the data signal line. Drive the rest (S3, S4, S7, S8, etc.) correctly. Therefore, according to the liquid crystal display device 10 including the scanning signal line driving circuit 2, the first data signal line driving circuit 11, and the second data signal line driving circuit 12, the display elements included in the pixel array 1 are included. Child P can be driven correctly and the desired screen can be displayed.
- FIG. 3 is a diagram showing a mounting example of the liquid crystal display device 10.
- the liquid crystal panel 3 shown in FIG. 3 includes a pixel array 1, a scanning signal line driving circuit 2, a first data signal line driving circuit 11, and a second data signal line driving circuit on a single insulating substrate 4. It can be obtained by forming 12 monolithically.
- the liquid crystal panel 3 is equipped with a control IC 5.
- a control signal (dot clock CLK, horizontal synchronization signal HSYNC, vertical synchronization signal VSYNC, etc.) and a video signal VIN that is not phase-expanded are supplied.
- the control IC5 Based on these control signals, the control IC5 generates the gate start pulse GSP, gate clock GCK, source start pulse SSPA, SSPB, source clocks SCKA, SCKB and their inverted signals, and drives the scanning signal line Supply to circuit 2 etc.
- the control IC5 is a phase expansion circuit (Fig. (Not shown).
- the video signals VI and V2 are supplied to the first data signal line driving circuit 11, and the video signals V3 and V4 are supplied to the second data signal line driving circuit 12. Supplied.
- the force for mounting the liquid crystal panel 3 control IC 5 may be provided outside the liquid crystal panel 7 as shown in FIG.
- the lengths of the signal lines that transmit the video signals VI and V 2 to the first data signal line driving circuit 11 and the video signals V 3 and V 4 to the second data signal line driving circuit 12 are transmitted. It is preferable that the length of the signal line is substantially equal.
- the length of the wiring for transmitting the video signals VI and V2 from the control IC 5 to the first data signal line drive circuit 11 and the video signals V3 and V4 from the control IC 5 to the second is preferable that the length of the wiring transmitted to the data signal line driving circuit 12 is substantially equal.
- the length of the wiring for transmitting the video signals VI and V2 to the first data signal line driving circuit 11 from the external terminal force of the liquid crystal panel 7 and the video signals V3 and V4 are displayed. It is preferable that the length of the wiring transmitted to the second data signal line drive circuit 12 from the external terminal force of 7 is substantially equal.
- the liquid crystal display device 10 has the effect that no vertical stripes are generated, and the frame is narrow and the power consumption is small.
- a ghost may occur on a screen when conduction periods overlap between switches to which the same video signal is supplied.
- the first data signal line driving circuit 11 when the four data signal lines Sl to Sm are grouped in accordance with the arrangement order, the first data signal line driving circuit 11 includes the data signal lines included in the same group. Since two of them are controlled to be in a conductive state in sequence, switch 15 (for example, switch 15 corresponding to data signal line S1 and switch corresponding to data signal line S5 is supplied with the same video signal. 15) will not conduct at the same time.
- the second data signal line driving circuit 12 collectively controls two of the data signal lines included in the same group to be sequentially turned on, so that the switch 16 (for example, the same video signal is supplied) Therefore, the switch 16 corresponding to the data signal line S3 and the switch 16) corresponding to the data signal line S7 do not conduct at the same time.
- the switch 16 for example, the same video signal is supplied
- the switch 16 corresponding to the data signal line S3 and the switch 16 corresponding to the data signal line S7 do not conduct at the same time.
- the liquid crystal display device may display on the screen due to parasitic capacitance generated between adjacent data signal lines. Vertical streaks may occur.
- the adjacent data signal lines for example, S4 and S5 or S8 and S9 across the group boundary are They are divided so that they belong to different categories (that is, one is driven by the first data signal line driving circuit 11 and the other is driven by the second data signal line driving circuit 12).
- the switch control signals CAl to CAq and CB1 to CBq are overlapped by half cycle in the order of CA1, CB1, CA2, CB2, CA3, CB3, ..., CAq, CBq.
- Each cycle goes high. Therefore, in the liquid crystal display device 10, between the switches corresponding to the adjacent data signal lines, either the conduction periods coincide or the conduction periods overlap by a half cycle. Therefore, according to the liquid crystal display device 10, it is possible to prevent vertical stripes generated on the screen.
- the first data signal line driving circuit 11 is arranged along one side in the row direction of the pixel array 1, and the second data signal line driving circuit 12 is arranged in the row of the pixel array 1. Arranged along the other side of the direction. Therefore, even when the same number of flip-flops and switches as in the conventional liquid crystal display device 90 (FIG. 19) are provided, the data signal line driving circuit is divided and arranged on two opposite sides of the frame, so that one side of the frame is It can be prevented from becoming thicker than other sides.
- the flip-flop 92 of the data signal line driving circuit 91 operates once every half cycle.
- a liquid crystal display device 10 the flip-flop 13 of the first data signal line driving circuit 11 and the flip-flop 14 of the second data signal line driving circuit 12 operate at a rate of once per cycle. Therefore, according to the liquid crystal display device 10, the power consumption can be reduced by the amount that the operating frequency of the flip-flop is low. Further, the size of the transistors included in the flip-flops 13 and 14 can be reduced, and the frame can be narrowed.
- the length of the signal line for transmitting the video signals VI and V2 to the first data signal line driving circuit 11, and the length of the signal line for transmitting the video signals V3 and V4 to the second data signal line driving circuit 12. are almost equal, the capacitive load and resistance of these signal lines are almost equal in terms of the circuit power to output video signals V1 to V4. Therefore, the charging effect of the data signal lines Sil and Si2 by the first data signal line driving circuit 11 and the charging effect of the data signal lines Si3 and Si4 by the second data signal line driving circuit 12 are almost the same. Be the same. Therefore, it is possible to suppress variations in charging associated with driving data signal lines from both sides of the pixel array 1.
- the source start pulses SSPA and SSPB and the source clocks SCKA and SCKB supplied to the liquid crystal display device 10 change at different timings.
- the source start pulses SSPA and SSPB The source clocks SCKA and SCKB may change at the same timing as shown in FIG.
- the flip-flop 13 of the first data signal line drive circuit 11 changes the switch control signals CAl to CAq at the rising edge of the source clock
- the flip-flop 14 of the second data signal line drive circuit 12 The switch control signals CBl to CBq may be changed at the falling edge of the clock.
- the liquid crystal display devices according to the second to fifth embodiments have the same configuration and similar characteristics as the liquid crystal display device 10 according to the first embodiment, and perform the same operations. Therefore, hereinafter, differences from the first embodiment will be mainly described, and description of the same points as in the first embodiment will be omitted.
- FIG. 6 is a diagram showing a configuration of a liquid crystal display device according to the second embodiment of the present invention.
- the liquid crystal display device 20 shown in FIG. 6 includes a pixel array 1, a scanning signal line driving circuit 2, a first data signal line driving circuit 21, and a second data signal line driving circuit 22, and is developed in four phases. Based on video signals V1 to V4, monochrome multi-gradation display is performed.
- the second data signal line driving circuit 22 includes mZ4 flip-flops. Includes Lop 24 and mZ 2 switches 26.
- the connection form and operation of the flip-flops 23 and 24 are the same as those in the first embodiment.
- the data signal lines Sl to Sm are grouped by four (the number of video signals) according to the arrangement order, thereby forming mZ4 groups.
- the signal lines and data signal lines that propagate the video signals VI and V3 One switch 25 is provided between Sil and Si 3 respectively. These two switches 25 switch whether to apply the video signals VI and V3 to the data signal lines Sil and Si3 according to the switch control signal CAi.
- One switch 26 is provided between each of the signal lines propagating the video signals V2 and V4 and the data signal lines Si2 and Si4. These two switches 26 switch whether or not to apply the video signals V2 and V4 to the data signal lines Si2 and Si4 according to the switch control signal CBi.
- FIG. 7 is a timing chart of the liquid crystal display device 20.
- the video signals VI and V3 change at the same timing, and the video signals V2 and V4 change at a timing delayed by a half cycle.
- FIG. 8 is a diagram showing a configuration of a liquid crystal display device according to the third embodiment of the present invention.
- the liquid crystal display device 30 shown in FIG. 8 includes a pixel array 1, a scanning signal line driving circuit 2, a first data signal line driving circuit 31, and a second data signal line driving circuit 32, and is expanded into eight phases. Performs monochrome multi-tone display based on video signals V1 to V8.
- the second data signal line driving circuit 32 includes mZ8 flip-flops. It includes a lop 34 and m / 2 switches 36.
- a first shift register formed by connecting mZ8 flip-flops 33 in series.
- the star outputs switch control signals CAl to CAr.
- a second shift register formed by connecting mZ8 flip-flops 34 in series outputs switch control signals CB1 to CBr.
- the data signal lines Sl to Sm are grouped by 8 (the number of video signals) according to the arrangement order, thereby forming mZ8 groups.
- the first data signal line driving circuit 31 and the second data signal line driving circuit 32 are each provided with four switches corresponding to each group.
- the video signals VI to V4 One switch 35 is provided between each of the signal line propagating through the signal line and the data signal lines Sj1 to Sj4. These four switches 35 switch whether to apply the video signals V1 to V4 to the data signal lines 3 ⁇ 41 to 3 ⁇ 44 according to the switch control signal CAj.
- One switch 36 is provided between each of the signal lines propagating the video signals V5 to V8 and the data signal lines 3 ⁇ 45 to 3 ⁇ 48. These four switches 36 switch whether to apply the video signals V5 to V8 to the data signal lines Sj5 to Sj8 according to the switch control signal CBj.
- FIG. 9 is a timing chart of the liquid crystal display device 30.
- the video signals V1 to V4 change at the same timing, and the video signals V5 to V8 change at a timing delayed by a half cycle.
- FIG. 10 is a diagram showing a configuration of a liquid crystal display device according to the fourth embodiment of the present invention.
- the liquid crystal display device 40 shown in FIG. 10 includes a pixel array 1, a scanning signal line driving circuit 2, a first data signal line driving circuit 41, and a second data signal line driving circuit 42, and is expanded into eight phases. Performs monochrome multi-tone display based on video signals V1 to V8.
- the connection form and operation of the flip-flops 43 and 44 are the same as those of the third embodiment.
- the data signal lines Sl to Sm are grouped by 8 (the number of video signals) according to the arrangement order, thereby forming mZ8 groups.
- First data signal line driving circuit 41 and the second data signal line driving circuit 42 are provided with four switches corresponding to each group.
- the video signals VI, V3 A switch 45 is provided between each of the signal line propagating through V5 and V7 and the data signal line 3 ⁇ 4 1, 3 ⁇ 43, 3 ⁇ 45, and 3 ⁇ 47. These four switches 45 switch whether to apply the video signals VI, V3, V5, V7 to the data signal lines Sjl, Sj3, Sj5, Sj7 according to the switch control signal CAj. Further, one switch 46 is provided between each of the signal lines propagating the video signals V2, V4, V6, and V8 and the data signal lines Sj2, 3 ⁇ 44, Sj6, and Sj8. These four switches 46 switch whether to apply the video signals V2, V4, V6, V8 to the data signal lines Sj2, Sj4, Sj6, Sj8 according to the switch control signal CBj.
- FIG. 11 is a timing chart of the liquid crystal display device 40.
- the video signals VI, V3, V5, and V7 change at the same timing, and the video signals V2, V4, V6, and V8 are delayed by half a cycle. Change.
- FIG. 12 is a diagram showing a configuration of a liquid crystal display device according to the fifth embodiment of the present invention.
- a liquid crystal display device 50 shown in FIG. 12 includes a pixel array 6, a scanning signal line driving circuit 2, a first data signal line driving circuit 51, and a second data signal line driving circuit 52, and is developed in four phases.
- the pixel array 6 includes (3m X n) display elements P, n scanning signal lines Gl to Gm, and 3m data signal lines Rl to Rm, gl to gm, and B1 to Bm. Contains.
- the display elements P are arranged 3m in the row direction and n in the column direction. Display elements arranged in the same row are commonly connected to any one of the scanning signal lines Gl to Gn.
- the display elements arranged in the same column are connected in common to any of the data signal lines Rl to Rm, gl to gm, B1 to Bm.
- Three display elements arranged side by side in the row direction correspond to red, green and blue, respectively.
- the connection form and operation of the flip-flops 53 and 54 are the same as those in the first embodiment.
- the data signal lines Rl to Rm, gl to gm, and Bl to Bm are grouped by 12 (the number of video signals) according to the arrangement order, thereby forming a group of mZ4.
- the first data signal line driving circuit 51 and the second data signal line driving circuit 52 are provided with six switches corresponding to each group.
- the twelve data signal lines included in the i-th group are Ril, gil, Bil, Ri2, gi2, Bi2, Ri3, gi3, Bi3, Ri4, gi4, Bi4 in the arrangement order.
- the video signal VR1, VG1, VB1, VR2, VG2, VB2 and the data signal line Ril, gil, Bil, Ri2, gi2, Bi2 are each one switch 55 Provided. These six switches 55 switch whether to apply the video signals VR1, VG1, VB1, VR2, VG2, VB2 to the data signal lines Ril, gil, Bil, Ri2, gi2, Bi2 according to the switch control signal CAi. Replace.
- one switch 56 is provided between the signal line that propagates the video signals VR3, VG3, VB3, VR4, VG4, and VB4 and the data signal line Ri3, gi3, Bi3, Ri4, gi4, Bi4. It is done. These six switches 56 indicate whether to apply the video signals VR3, VG3, VB3, VR4, VG4, VB4 to the data signal lines Ri3, gi3, Bi3, Ri4, gi4, Bi4 according to the switch control signal CBi. Switch.
- FIG. 13 is a timing chart of the liquid crystal display device 50.
- video signals VR1, VG1, VB1, VR2, VG2, VB2 change at the same timing
- video signals VR3, VG3, VB3, VR4, VG4, VB4 Also changes at a timing delayed by half a cycle.
- the liquid crystal display devices 20, 30, 40, 50 according to the second to fifth embodiments have the same characteristics as the liquid crystal display device 10 according to the first embodiment. . That is, in the liquid crystal display devices 20, 30, 40, and 50, (1) there is no overlap of conduction periods between switches to which the same video signal is supplied. (2) Switches corresponding to adjacent data signal lines. (3) The data signal line drive circuit is divided and arranged so as to have the same circuit amount on the two opposite sides of the frame, and (4) is divided and arranged. The flip-flops included in the data signal line drive circuit operate once per cycle. did Therefore, in the liquid crystal display devices 20, 30, 40, and 50 according to the second to fifth embodiments, a vertical stripe ghost is generated as in the liquid crystal display device 10 according to the first embodiment. The effect is that the frame is narrow and the power consumption is small.
- a liquid crystal display device having a similar structure and similar characteristics and performing the same operation can be formed.
- the number of display elements included in the pixel array is arbitrary in both the row direction and the column direction, and the number of phase expansions of the video signal is arbitrary.
- the video signal may be a black and white video signal or a color video signal.
- the data signal lines adjacent to each other across the boundary of the group belong to another category.
- the way of dividing may be arbitrary. For example, in a liquid crystal display device that performs display based on an 8-phase expanded video signal, group eight data signal lines Sl to Sm according to the arrangement order, and then the first data signal line in the group Is driven by the first data signal line drive circuit, and the eighth data signal line in the group is driven by the second data signal line drive circuit, the second to seventh data signal lines in the group are It may be driven by either the first data signal line driving circuit or the second data signal line driving circuit.
- the width of the side of the frame on which the first data signal line driving circuit is arranged and the width of the side of the frame on which the second data signal line driving circuit is arranged do not have to be aligned
- the data signal lines included in each group may be divided into different numbers (for example, eight data signal lines are divided into five and three).
- the division method in one group and the division method in another group may be different.
- the source start pulses SSPA and S SPB that change at the same timing and the source clocks SCKA and SCKB are also supplied to the liquid crystal display devices other than the first embodiment. May be.
- liquid crystal display devices also have the effect that vertical stripes do not occur and the frame is narrow and power consumption is small, as in the liquid crystal display devices according to the first to fifth embodiments.
- the liquid crystal display device of the present invention has no vertical stripes on the screen and a narrow frame. Therefore, it can be used for display devices of various devices such as mobile phones, information processing terminals and personal computers.
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- Crystallography & Structural Chemistry (AREA)
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- Liquid Crystal Display Device Control (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US12/084,766 US20090115771A1 (en) | 2005-11-15 | 2006-09-13 | Liquid Crystal Display Device and Method for Driving Same |
JP2007545169A JPWO2007058014A1 (ja) | 2005-11-15 | 2006-09-13 | 液晶表示装置およびその駆動方法 |
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JP2005-330108 | 2005-11-15 | ||
JP2005330108 | 2005-11-15 |
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WO2007058014A1 true WO2007058014A1 (ja) | 2007-05-24 |
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PCT/JP2006/318121 WO2007058014A1 (ja) | 2005-11-15 | 2006-09-13 | 液晶表示装置およびその駆動方法 |
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US (1) | US20090115771A1 (ja) |
JP (1) | JPWO2007058014A1 (ja) |
CN (1) | CN101305413A (ja) |
WO (1) | WO2007058014A1 (ja) |
Cited By (4)
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JP2009229819A (ja) * | 2008-03-24 | 2009-10-08 | Epson Imaging Devices Corp | 表示装置 |
CN103761954A (zh) * | 2014-02-17 | 2014-04-30 | 友达光电(厦门)有限公司 | 显示面板与栅极驱动器 |
CN108538241A (zh) * | 2018-06-29 | 2018-09-14 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示装置 |
JP7505296B2 (ja) | 2020-06-30 | 2024-06-25 | セイコーエプソン株式会社 | 電気光学装置及び電子機器 |
Families Citing this family (5)
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JP5378592B2 (ja) * | 2010-03-19 | 2013-12-25 | シャープ株式会社 | 表示装置および表示駆動方法 |
JP5526976B2 (ja) * | 2010-04-23 | 2014-06-18 | セイコーエプソン株式会社 | 記憶性表示装置の駆動方法、記憶性表示装置、および電子機器 |
KR102250844B1 (ko) | 2014-06-09 | 2021-05-13 | 삼성디스플레이 주식회사 | 유기전계발광 표시장치 |
CN105204250B (zh) * | 2015-10-29 | 2019-03-01 | 京东方科技集团股份有限公司 | 阵列基板、显示装置及阵列基板的制作方法 |
KR102664716B1 (ko) | 2019-03-19 | 2024-05-09 | 삼성전자 주식회사 | 변형가능한 디스플레이 패널 내의 화면의 표시를 위한 전자 장치, 방법, 및 컴퓨터 판독가능 매체 |
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Also Published As
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CN101305413A (zh) | 2008-11-12 |
US20090115771A1 (en) | 2009-05-07 |
JPWO2007058014A1 (ja) | 2009-04-30 |
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