WO2007056950A1 - Dispositif de detection de phase pour alimentation electrique urbaine - Google Patents

Dispositif de detection de phase pour alimentation electrique urbaine Download PDF

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Publication number
WO2007056950A1
WO2007056950A1 PCT/CN2006/003082 CN2006003082W WO2007056950A1 WO 2007056950 A1 WO2007056950 A1 WO 2007056950A1 CN 2006003082 W CN2006003082 W CN 2006003082W WO 2007056950 A1 WO2007056950 A1 WO 2007056950A1
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WO
WIPO (PCT)
Prior art keywords
phase
output
accumulator
digital
detector
Prior art date
Application number
PCT/CN2006/003082
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English (en)
French (fr)
Inventor
Chaosheng Song
Gang Gou
Original Assignee
Miartech, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Miartech, Inc. filed Critical Miartech, Inc.
Priority to EP06817830A priority Critical patent/EP1953917A4/en
Priority to US12/093,532 priority patent/US7646225B2/en
Publication of WO2007056950A1 publication Critical patent/WO2007056950A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Definitions

  • the present invention relates to a phase detecting device, and more particularly to a commercial power phase detecting device. Background technique
  • phase/frequency of the power line needs to be detected.
  • the usual mains phase/frequency detection uses the zero-crossing detection method, that is, the zero-crossing point of the mains is detected by a comparator, and then the period and frequency of the mains are obtained by calculating the time interval between the zero-crossing points.
  • This method has the advantages of fast detection speed, simple and reliable. However, due to the large amount of noise and interference on the power line, it will have a certain impact on the time of zero crossing, which makes this simple zero-crossing detection method not obtain high-precision detection results. Summary of the invention
  • the present invention provides a commercial power phase detecting device which can effectively improve the detection accuracy of the commercial power phase.
  • phase measuring device of the present invention a high-precision all-digital phase-locked loop is added after the zero-crossing detector to provide extremely high-accuracy detection performance.
  • the invention provides a commercial power phase detecting device, comprising a zero-crossing detector and an all-digital phase-locked loop, wherein the all-digital phase-locked loop comprises a digital phase detector connected in sequence, a digital loop filter and a numerical control oscillation
  • the digitally controlled oscillator output and the zero crossing detector output are coupled to the digital phase detector input.
  • the digital phase detector includes an exclusive OR gate.
  • the digital loop filter includes: an accumulator, a proportional adjuster, an integrator, a first adder, and a second adder, the accumulator input end and the number
  • the phase detector output is connected, the proportional regulator and the input of the integrator are connected to the accumulator output; the two inputs of the first adder are respectively associated with the proportional regulator and the integral
  • the output of the device is connected, the second adder has two inputs, wherein one input is connected to the first adder
  • the initial frequency word corresponds to a frequency between 53 and 57 Hz.
  • the initial frequency word corresponds to a frequency of 55 Hz.
  • a rising edge detector that generates a detection pulse triggered by a rising edge of an output signal of the zero-crossing detector, the rising edge detector outputs a detection pulse to the An accumulator of the loop filter, the accumulator resetting in response to the detection pulse, and accumulating an output signal of the phase detector between the two detection pulses.
  • the numerically controlled oscillator includes a phase accumulator, and an input end of the phase accumulator is connected to an output end of the digital loop filter, and the highest of the phase accumulator The bit acts as an output signal to the digital phase detector.
  • FIG. 1 is a block diagram showing the structure of a commercial power phase detecting device of the present invention
  • FIG. 2 is a structural block diagram of a preferred embodiment of a commercial power phase detecting device of the present invention
  • FIG. 3 is a block diagram showing a loop filter structure of the commercial phase detecting device shown in FIG. 2;
  • Figure 4 is a block diagram showing the structure of an integrator of the commercial phase detecting device shown in Figure 2;
  • Figure 5 is a block diagram showing the structure of a phase accumulator of the mains phase detecting device shown in Figure 2;
  • FIG. 6 is a schematic diagram showing waveforms of respective points of the commercial phase detecting device shown in FIG. 2;
  • FIG. 7 is a schematic diagram showing waveforms of respective points of the loop filter shown in FIG. 3;
  • Fig. 8 is a schematic diagram showing waveforms of respective points of the phase accumulator shown in Fig. 5.
  • the commercial phase detecting device of the present invention includes a zero crossing detector 110 and an all-digital phase locked loop composed of a digital phase detector 111, a digital loop filter 112 and a numerically controlled oscillator 113.
  • the zero-crossing detector (comparator) 110 shapes the analog signal obtained by the mains sampling, converts the mains signal from a distorted sine wave into a square wave signal, and samples the clock signal to obtain a 1-bit digital signal. .
  • the digital phase detector 111 of the phase locked loop completes the external input digital signal and the numerical control vibration
  • the phase comparison of the output signal of the sigmoid 113 (generally implemented by a component having a multiplicative characteristic), the digital loop filter 1 12 implements low-pass filtering, and generates an error control signal to adjust the frequency of the output signal of the numerically controlled oscillator 1 13 to The input signals differ by zero. Because the all-digital phase-locked loop has accurate phase tracking, it can be used in commercial phase detection to provide extremely accurate detection performance.
  • zero crossing detector 110 can be implemented using conventional techniques. Therefore, the internal structure will not be further described herein, and those skilled in the art can implement the conventional technology or the prior art according to the above description.
  • FIG. 2 is a structural block diagram of a preferred embodiment of the commercial power phase detecting device of the present invention
  • FIG. 6 is a waveform diagram of each point of the commercial power phase detecting device shown in FIG.
  • the zero-crossing detector 121 similarly shapes the analog signal obtained by the commercial power sampling, converts the commercial power signal into a square wave signal from a distorted sine wave, and obtains 1 bit through the clock signal. 50Hz digital signal a.
  • the all digital phase locked loop includes a rising edge detector 122, an exclusive OR phase detector 123, a loop filter 124, and a phase accumulator 125 for use as a numerically controlled oscillator.
  • the phase detector 123 performs phase discrimination on the input signal a to be tracked and the output signal b of the phase accumulator 125 (ie, the numerically controlled oscillator). Since the input signal a is a 1-bit digital signal, the output b of the phase accumulator 125 is also a square wave ( It can also be represented by a 1-bit signal. Therefore, the multiplication operation required by the phase detector 123 only requires 1 bit multiplied by 1 bit, so that the phase detector here can be simplified to an exclusive OR gate.
  • the rising edge detector 122 detects the rising edge of the output signal a and thereby generates a detection pulse signal d for controlling the operation of the loop filter 124 and the phase accumulator 125, the process of which will be described below.
  • FIG. 3 is a block diagram of the loop filter 124 of FIG. 2, and FIG. 7 is a waveform diagram of each point of the loop filter shown in FIG.
  • the loop filter 124 is composed of a first-order loop including an accumulator 130, a proportional adjuster 131, an integrator 132, a first adder 133, and a second adder 134.
  • the input end of the accumulator 130 is connected to the output end of the phase detector 123 for accumulating the output signal a of the phase detector 123 to complete the conversion of the lbit data to the specific phase data.
  • the specific accumulating process is: At the rising edge of the output signal a of 121, the accumulator 130 receives the detection pulse of the rising edge detector 122 and performs an initial value (ie, reset, the reset value is zero) between the two rising edges of the signal a ( That is, between the two detection pulses of the rising edge detector 122), the output signal c of the phase detector 123 is accumulated, and the output signal is e0.
  • the inputs of the proportional regulator 131 and the integrator 132 are both connected to the output of the accumulator 130, wherein the proportional regulator 131 is used to accumulate the accumulator 130.
  • FIG. 4 shows a block diagram of the structure of one embodiment of the integrator 132.
  • the integrator 132 is composed of a 19-bit adder 141 and a 19-bit unit delay unit 142.
  • One input of the adder 141 is the output signal e0 of the accumulator 130, and the other input is the output of the delay unit 142, at the output signal a.
  • the rising edge of the adder 141 is stored by the unit delay unit 142.
  • the outputs of the integrator 132 and the proportional adjuster 131 are added in the first adder, the operation result e2 and an initial frequency word are input to the second adder 133, and the output signal e of the second adder 134 is a loop filter The output of 124.
  • the initial frequency word corresponds to an initial output frequency
  • the phase-locked loop can finally achieve phase-locking with the input signal a to be tracked by using the initial output frequency. Since the world uses 50 Hz and 60 Hz two-frequency alternating current, it is better to set By setting an initial frequency word corresponding to an initial output frequency between 53 Hz and 57 Hz, it is possible to more easily realize the phase lock function of 50 Hz or 60 Hz mains, without separately configuring the initial frequency words of 50 Hz and 60 Hz, and more preferably, The initial frequency word corresponds to an initial output frequency of 55 Hz. Assume that the clock frequency in the system is 921.6kHz, and the number of bits in the phase accumulator is 31 bits, by the formula
  • this initial frequency word is 128159.
  • the phase-locked loop of this structure has a long initial lock-up time, and the specific value is determined by the accuracy of the system clock and the phase accumulator. This structure can be employed because there is no particularly high requirement for the initial lock time in the actual use of the system.
  • FIG. 5 is a structural block diagram of the phase accumulator
  • FIG. 8 is a waveform diagram of each point of the phase accumulator shown in FIG.
  • the phase accumulator 125 is a DDS (Digital Direct Frequency Synthesis) architecture with a system clock frequency of 921.6 kHz. It uses a 31-bit accumulator.
  • the structure of the accumulator is similar to that of the integrator 132 in the loop filter 124. The difference is that the adder 151 is 31 bits wide and the delay unit 152 is 31 bits wide.
  • the phase accumulator is accumulated every clock cycle, and when the adder 151 overflows, a cycle is completed, and the highest bit periodically changes, that is, the output signal b of the entire digital phase-locked loop, its phase and the input signal to be tracked. a orthogonal (90 degrees difference).
  • FIG. 6 is a schematic diagram showing waveforms of respective points of the commercial phase detecting device shown in FIG. 2. From FIG. 6, the phase locking operation process of the commercial phase detecting device can be seen, wherein the output signal a of the zero-crossing detector 121 is 50 Hz. The square wave; the signal b is the output signal of the digital phase-locked loop.
  • Figure 7 further illustrates the waveform output of each point during operation of loop filter 124.
  • the signal e0 is the output signal of the accumulator 130, and the accumulator 130 accumulates the output signal c of the phase detector 123. It can be seen that when the loop starts to work, the output of the accumulator 130 changes significantly, and when the loop reaches After the steady state, the output of the accumulator 130 remains unchanged, and the amplitude is stabilized at 0; the signal el is the output signal of the integrator 132. Since the integrator 132 itself has a hysteresis effect, it can be seen that the integrator 132 outputs the relative first adder.
  • the 133 output (including the output of the proportional regulator 131) has a delay.
  • the output of the integrator 132 changes significantly.
  • the output of the integrator 132 remains unchanged and stabilizes at - The amplitude of 48584; the signal e2 is the output of the first adder 133.
  • the output of the first adder 133 changes significantly, and when the loop reaches the steady state, the first adder 133 outputs It remains unchanged and stabilizes at an amplitude of -11651;
  • the signal e is the output of the second adder 134, that is, the output of the loop filter 124, and when the loop is just starting to operate, the second adder 134 outputs an explicit The change occurs, and when the loop reaches the steady state, the output of the second adder 134 remains unchanged and stabilizes at the amplitude of 116508. It can be seen that the output of the second adder 134 relative to the first adder 133 differs only by the initial frequency. The difference between the words 128159.
  • Figure 8 shows the waveform output of each point when the numerically controlled oscillator is operating.
  • the signal bl is the 31-bit accumulator output signal, which changes periodically.
  • the signal b is the highest-order output signal of the accumulator, that is, the final output of the entire digital phase-locked loop, which is a square wave output.
  • the accuracy of the all digital phase locked loop of the present invention is determined by the bit width of the phase accumulator 125 and the system clock.
  • the clock frequency is 921.6 kHz
  • the commercial power phase detecting device of the invention adopts an all-digital loop structure and a high sampling clock, and the recovered signal is orthogonal to the commercial power phase, has the same frequency, and has jitter of less than lOus, and can realize zero in a wide range.
  • Frequency error and zero-phase signal tracking can effectively provide excellent detection results for power line carrier communication and mains frequency detection. Thanks to the all-digital approach, design and debug can be implemented in software, which greatly reduces the cost and avoids the device consistency problem caused by the analog phase-locked loop.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Phase Differences (AREA)

Description

一种市由,相位检测装置 技术领域
本发明涉及一种相位检测装置， 尤其涉及一种市电相位检测装置。 背景技术
在多种应用领域 （例如市电频率监测、 相控整流、 以及电力线载波通信中的 市电相位检测） ， 需要对电力线的相位 /频率进行检测。
通常的市电相位 /频率检测均采用过零点检测法， 即通过一个比较器检测出市 电的过零点，然后通过计算过零点之间的时间间隔得到市电的周期和频率。这种方 法具有检测速度快， 简单可靠的优点。 但由于电力线上存在着大量的噪声和干扰， 会对过零点出现的时间造成一定的影响，从而造成这种简单的过零点检测方法并不 能得到高精度的检测结果。 发明内容
为了克服现有技术存在的缺点， 本发明在于提供一种市电相位检测装置， 该 检测装置能有效地提高市电相位的检测精度。
在本发明的市电相位捡测装置中， 在过零点检测器之后加入一个高精度的全 数字锁相环路， 以提供精确度极高的检测性能。
本发明提供一种市电相位检测装置， 包括一过零点检测器和一全数字锁相 环， 所述全数字锁相环包括依次序连接的数字鉴相器、 数字环路滤波器和数控 振荡器， 其中所述数控振荡器输出端与所述过零点检测器输出端连接到所述数 字鉴相器输入端。
在所述的市电相位检测装置中， 所述数字鉴相器包括一异或门。
在所述的市电相位检测装置中， 所述数字环路滤波器包括： 累加器、 比例 调节器、 积分器、 第一加法器和第二加法器， 所述累加器输入端与所述数字鉴 相器输出端连接， 所述比例调节器和所述积分器的输入端与所述累加器输出端 连接； 所述第一加法器的两输入端分别与所述比例调节器和所述积分器的输出 端连接， 所述第二加法器具有两输入端， 其中一输入端与所述第一加法器的输
1
确认本 出端连接， 另一输入端被置一初始频率字。
在所述的市电相位检测装置中，所述初始频率字对应一介于 53~57Hz之间 的频率。
在所述的市电相位检测装置中， 所述初始频率字对应一 55Hz的频率。 在所述的市电相位检测装置中， 还包括一受所述过零点检测器的输出信号 的上升沿触发而产生检测脉冲的上升沿检测器， 所述上升沿检测器输出检测脉 冲至所述环路滤波器的累加器， 所述累加器响应所述检测脉冲而进行重置， 且 在两个所述检测脉冲之间对所述鉴相器的输出信号进行累加。
在所述的市电相位检测装置中， 所述数控振荡器包括一相位累加器， 所述 相位累加器的输入端与所述数字环路滤波器的输出端连接， 所述相位累加器的 最高位作为输出到所述数字鉴相器的输出信号。 附图概述
本发明的特征、 性能将通过以下的实施例并配合附图来进一步描述。
图 1为本发明的市电相位检测装置的结构框图；
图 2为本发明的市电相位检测装置一个较佳实施例的结构框图；
图 3为图 2所示的市电相位检测装置的环路滤波器结构框图；
图 4为图 2所示的市电相位检测装置的积分器结构框图；
图 5为图 2所示的市电相位检测装置的相位累加器结构框图；
图 6为图 2所示的市电相位检测装置的各点波形示意图；
图 7为图 3所示的环路滤波器的各点波形示意图；
图 8为图 5所示的相位累加器的各点波形示意图。 本发明的最佳实施方式
请参阅图 1所示， 本发明的市电相位检测装置包括一过零点检测器 110以及 一个由数字鉴相器 111、数字环路滤波器 112和数控振荡器 113组成的全数字锁相 环。 首先由过零点检测器 （比较器） 110对市电取样得到的模拟信号进行整形， 将市电信号由一个有失真的正弦波转化成方波信号， 并经过时钟信号采样得到 1 比特的数字信号。 锁相环的数字鉴相器 111完成外部输入数字信号和数控振 荡器 113输出信号的相位比较 （一般为具有乘法特性的部件实现） ， 数字环路 滤波器 1 12实现低通滤波， 产生误差控制信号来调整数控振荡器 1 13输出信号 的频率， 使其与输入信号相差为零。 由于全数字锁相环路具有精确的相位追踪功 能， 因此将其用于市电相位检测中， 能够提供精确度极高的检测性能。
在图 1的实施例中， 过零点检测器 110可以采用常规技术实现。 因此， 在此 不再对其内部结构作进一步的描述，本领域技术人员可以根据上述的描述利用常规 技术或现有技术加以实现。
请结合图 6同时参阅图 2所示， 图 2为本发明的市电相位检测装置一个较佳 实施例的结构框图， 图 6是图 2所示市电相位检测装置的各点波形示意图。在本实 施例中， 过零点检测器 121 同样对市电取样得到的模拟信号进行整形， 将市电 信号由一个有失真的正弦波转化成方波信号， 并经过时钟信号釆样得到 1比特 的 50Hz数字信号 a。全数字锁相环包括上升沿检测器 122、异或门鉴相器 123、 环路滤波器 124和用作数控振荡器的相位累加器 125。 鉴相器 123对需要跟踪 的输入信号 a和相位累加器 125 (即数控振荡器） 的输出信号 b进行鉴相， 由 于输入信号 a为 lbit数字信号， 相位累加器 125的输出 b也是方波 （也可用 1 比特信号表示） ， 故鉴相器 123 所需要实现的乘法操作仅仅需要 lbite乘以 1 比特， 从而这里的鉴相器可简化为一个异或门。 上升沿检测器 122检测输出信 号 a的上升沿， 并由此产生检测脉冲信号 d， 该信号用于控制环路滤波器 124 和相位累加器 125的工作， 其过程将在以下描述。
请结合图 7同时参阅图 3所示， 图 3是图 2中的环路滤波器 124的结构框 图， 图 7为图 3所示的环路滤波器的各点波形示意图。 环路滤波器 124由一个 1 阶环路构成， 包括累加器 130、 比例调节器 131、 积分器 132、 第一加法器 133 和第二加法器 134。 累加器 130的输入端与鉴相器 123的输出端连接， 用以对 鉴相器 123输出信号 a累加计数， 完成 lbit数据到具体相位数据的转换， 具体 的累加过程是： 在过零点检测器 121的输出信号 a的上升沿， 累加器 130接收 到上升沿检测器 122的检测脉冲而进行赋初值 （即重置， 重置值是零） ， 在信 号 a的两个上升沿之间 （亦即上升沿检测器 122的两个检测脉冲之间） 对鉴相 器 123的输出信号 c进行累加， 输出信号为 e0。 比例调节器 131和积分器 132 的输入端均与累加器 130的输出端连接，其中比例调节器 131用以对累加器 130 输出信号 e0进行加权， 积分器 132对累加器 130输出信号 eO进行累加， 输出 信号 el， 具体的累加过程是： 在输出信号 a的上升沿， 积分器 132接收到上升 沿检测器 122的检测脉冲而进行累加。 图 4示出积分器 132的一个实施例的结 构框图。积分器 132由一个 19bit加法器 141和一个 19bit单位延时单元 142构 成， 加法器 141的一个输入为累加器 130的输出信号 e0， 而另一个输入为延时 单元 142的输出， 在输出信号 a的上升沿， 加法器 141输出经过单位延时单元 142储存。 积分器 132和比例调节器 131的输出在第一加法器进行加法运算， 运算结果 e2和一初始频率字输入到第二加法器 133，第二加法器 134的输出信 号 e即为环路滤波器 124的输出。
上述初始频率字对应于一个初始输出频率， 锁相环利用该初始输出频率可 最终与需要跟踪的输入信号 a实现锁相，由于目前世界上使用 50Hz和 60Hz两 种频率交流电，因此较佳地设定一个对应一介于 53Hz~57Hz之间的初始输出频 率的初始频率字， 可以更简单的实现 50Hz或者 60Hz市电的锁相功能， 不需要 分别配置 50Hz和 60Hz初始频率字， 更佳地， 所述初始频率字对应 55Hz的初 始输出频率。 假定系统中时钟频率为 921.6kHz, 相位累加器的位数是 31位， 由公式
55 X 231/921.6/1000=128159
可知这个初始频率字取 128159。这种结构的锁相环初始锁定时间较长， 具 体数值由系统时钟以及相位累加器的精度确定。 因为在系统实际使用中对初始 锁定时间并没有特别高的要求， 故可以采用这种结构。
请结合图 8并参阅图 5所示， 图 5是相位累加器的结构框图， 图 8是图 5 所示的相位累加器的各点波形示意图。相位累加器 125为 DDS (数字直接频率 合成） 结构， 釆用系统时钟频率为 921.6kHz。 它使用一个 31 比特的累加器， 累加器的结构与环路滤波器 124中的积分器 132结构类似，不同的是加法器 151 位宽为 31bit， 延时单元 152位宽为 31bit。 相位累加器在每个时钟周期进行累 加， 当加法器 151溢出时完成一个循环周期， 其最高位周期性变化， 即为整个 数字锁相环路的输出信号 b，其相位与需要追踪的输入信号 a正交（相差 90度）。
图 6为图 2所示的市电相位检测装置的各点波形示意图， 从图 6中可以看出 市电相位检测装置的锁相工作过程，其中过零点检测器 121的输出信号 a是 50Hz 方波； 信号 b是数字锁相环路的输出信号， 可以看到初始时输出信号 b的频率 与输入信号 a并不一致； 信号 c为鉴相器 123的输出信号， 可以看到当环路刚 开始工作时， 鉴相器 123输出有明显的变化， 反映了输入信号 a和锁相环输出 信号 b之间的相位差， 而当环路输出信号 a和输入信号 b频率一致后， 鉴相器 123输出保持不变； 信号 d为上升沿检测器 122的输出信号， 随过零点检测器 的输出信号 a的上升沿变化； 信号 e为环路滤波器的输出信号， 可以看到当环 路开始工作时， 环路滤波器 124的输出并不是保持为一个近似常数， 而是明显 变化， 反映了环路处于捕获期，而当环路输出信号 b和输入信号 a频率一致后， 环路滤波器的输出近似保持为一个固定的常数 116508， 该值对应输出频率 50Hz, 说明环路已经与 50Hz输入信号实现锁相。 因此数字锁相环路的输出信 号 b最终稳定输出和输入信号 a频率一样， 而相位相差 90度。
图 7进一步示出环路滤波器 124工作过程中的各点波形输出。其中信号 e0 为累加器 130的输出信号， 累加器 130对鉴相器 123的输出信号 c进行累加， 可以看出当环路刚开始工作时， 累加器 130输出有明显变化， 而当环路达到稳 定状态后， 累加器 130输出保持不变， 稳定在 0的幅值； 信号 el为积分器 132 的输出信号， 由于积分器 132本身有迟滞效果， 可以看出积分器 132输出相对 第一加法器 133输出 （包含比例调节器 131输出） 有延时， 当环路刚开始工作 时， 积分器 132输出有明显变化， 而当环路达到稳定态后， 积分器 132输出保 持不变， 稳定在 -48584的幅值； 信号 e2为第一加法器 133的输出， 当环路刚 开始工作时， 第一加法器 133的输出有明显变化， 而当环路达到稳定态后， 第 一加法器 133输出保持不变， 稳定在 -11651的幅值； 信号 e为第二加法器 134 的输出， 即环路滤波器 124的输出， 当环路刚开始工作时， 第二加法器 134输 出有明显变化， 而当环路达到稳定态后， 第二加法器 134输出保持不变， 稳定 在 116508的幅值， 可以看出第二加法器 134相对第一加法器 133的输出， 仅 仅相差初始频率字 128159的差异。
图 8为数控振荡器工作时的各点波形输出。其中信号 bl为 31bit累加器输 出信号， 周期性变化， 信号 b为累加器最高位输出信号， 也就是整个数字锁相 环路的最终输出， 为方波输出。
本发明的全数字锁相环的精度由相位累加器 125的位宽和系统时钟决定， 实际系统中时钟频率为 921.6kHz， 相位累加器 125为 31位， 故系统的频率分 辨率为 921.6k/231 = 0.43 X l(T3 Hz， 可以满足系统设计要求。 工业应用性
本发明的市电相位检测装置采用了全数字的环路结构以及高的采样时钟， 恢复出来的信号与市电相位正交， 频率相同， 且具有小于 lOus的抖动， 可以在 大范围内实现零频率误差和零相位的信号跟踪， 能有效地为电力线载波通信、 市电频率检测等提供性能优良的检测结果。 由于采用全数字的方式， 设计调试 均可以通过软件实现， 故极大的降低了成本， 同时可以避免采用模拟锁相环所 带来的器件一致性问题。

Claims

1 . 一种市电相位检测装置， 包括一过零点检测器， 其特征在于， 所述市 电相位检测装置还包括一全数字锁相环， 所述全数字锁相环包括依次序连接的 数字鉴相器、 数字环路滤波器和数控振荡器， 其中所述数控振荡器输出端与所 述过零点检测器输出端连接到所述数字鉴相器输入端。
2. 如权利要求 1 所述的市电相位检测装置， 其特征在于， 所述数字鉴相 器包括一异或门。
3. 如权利要求 1 所述的市电相位检测装置， 其特征在于， 所述数字环路 滤波器包括： 累加器、 比例调节器、 积分器、 第一加法器和第二加法器， 所述 累加器输入端与所述数字鉴相器输出端连接， 所述比例调节器和所述积分器的 输入端与所述累加器输出端连接； 所述第一加法器的两输入端分别与所述比例 调节器和所述积分器的输出端连接， 所述第二加法器具有两输入端， 其中一输 入端与所述第一加法器的输出端连接， 另一输入端被置一初始频率字。
4. 如权利要求 3所述的市电相位检测装置， 其特征在于， 所述初始频率 字对应一介于 53~57Hz之间的频率。
5. 如权利要求 3或 4所述的市电相位检测装置， 其特征在于， 所述初始 频率字对应一 55Hz的频率。
6. 如权利要求 3 所述的市电相位检测装置， 其特征在于， 还包括一受所 述过零点检测器的输出信号的上升沿触发而产生检测脉冲的上升沿检测器， 所 述上升沿检测器输出检测脉冲至所述累加器， 所述累加器响应所述检测脉冲而 进行重置， 且在两个所述检测脉冲之间对所述鉴相器的输出信号进行累加。
7. 如权利要求 1或 3所述的市电相位检测装置， 其特征在于， 所述数控 振荡器包括一相位累加器， 所述相位累加器的输入端与所述数字环路滤波器的 输出端连接， 所述相位累加器的最高位作为输出到所述数字鉴相器的输出信 号。
PCT/CN2006/003082 2005-11-16 2006-11-16 Dispositif de detection de phase pour alimentation electrique urbaine WO2007056950A1 (fr)

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8116714B2 (en) * 2007-03-14 2012-02-14 Northern Microdesign, Inc. Use of powerlines for transmission of high frequency signals
JP5290589B2 (ja) * 2008-02-06 2013-09-18 ルネサスエレクトロニクス株式会社 半導体集積回路
CN101594147B (zh) * 2008-05-29 2011-08-24 中芯国际集成电路制造(北京)有限公司 锁相环电路
US8031025B2 (en) * 2009-03-16 2011-10-04 Mediatek Inc. Mixed-mode PLL
US8102195B2 (en) * 2009-05-13 2012-01-24 Mediatek Inc. Digital phase-locked loop circuit including a phase delay quantizer and method of use
US8938291B1 (en) * 2009-10-16 2015-01-20 Blackrock Microsystems, LLC Methods and systems for signal processing of neural data
US8907655B2 (en) 2011-04-29 2014-12-09 Analog Devices, Inc. System and method for detecting a fundamental frequency of an electric power system
US8868364B2 (en) * 2011-04-29 2014-10-21 Analog Devices, Inc. Apparatus and method for real time harmonic spectral analyzer
TWI451700B (zh) * 2011-12-05 2014-09-01 Global Unichip Corp 時脈資料回復電路
US8922253B2 (en) 2013-05-24 2014-12-30 Intel IP Corporation Hybrid phase-locked loops
US8872558B1 (en) * 2013-05-24 2014-10-28 Intel IP Corporation Hybrid phase-locked loops
CN105262480A (zh) * 2015-10-22 2016-01-20 江苏绿扬电子仪器集团有限公司 一种从高速串行信号中恢复时钟信号的系统
PL3579376T3 (pl) 2018-06-08 2020-08-10 Ovh Sposoby i systemy do rozpoznawania toru połączeniowego między źródłem zasilania a obciążeniem
US10236897B1 (en) * 2018-07-26 2019-03-19 Texas Instruments Incorporated Loss of lock detector
CN110995257B (zh) * 2019-12-28 2023-06-02 芯动微电子科技(珠海)有限公司 一种环路滤波电路
US11157057B1 (en) 2020-05-28 2021-10-26 Ovh Systems and methods for electric systems monitoring and/or failure detection
US11489553B1 (en) 2021-04-13 2022-11-01 Ovh System and method for identifying a connection between a power distribution unit and an electric device
CN113702693A (zh) * 2021-07-21 2021-11-26 青岛鼎信通讯股份有限公司 一种基于交流电压采样的电网过零检测方法及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5590157A (en) * 1993-05-19 1996-12-31 U.S. Philips Corporation Data terminal comprising a demodulator for a FSK phase-coherent modulated signal
CN1396710A (zh) * 2001-07-09 2003-02-12 三星电子株式会社 用输入信号的零交叉特性检测相差的装置及其锁相环电路
EP1422827A1 (en) * 2002-11-21 2004-05-26 STMicroelectronics Belgium N.V. Low frequency self-calibration of a PLL with multiphase clocks

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3883817A (en) * 1973-08-20 1975-05-13 Nasa Digital phase-locked loop
US5485484A (en) * 1993-12-21 1996-01-16 Unisys Corporation Digitally implemented phase and lock indicators for a bit synchronizer
JP2806239B2 (ja) * 1993-12-28 1998-09-30 三菱電機株式会社 周波数シンセサイザ
US6711227B1 (en) * 1999-02-05 2004-03-23 Broadcom Corporation Synchronizing method and apparatus
US6429707B1 (en) * 2001-04-27 2002-08-06 Semtech Corporation Reference signal switchover clock output controller
US6956924B2 (en) * 2001-08-14 2005-10-18 Northrop Grumman Corporation Efficient implementation of a decision directed phase locked loop (DD-PLL) for use with short block code in digital communication systems
DE10247996A1 (de) * 2002-10-15 2004-04-29 Robert Bosch Gmbh Schaltung zur Erzeugung eines hochfrequenten Takts aus einem analogen NF-Signal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5590157A (en) * 1993-05-19 1996-12-31 U.S. Philips Corporation Data terminal comprising a demodulator for a FSK phase-coherent modulated signal
CN1396710A (zh) * 2001-07-09 2003-02-12 三星电子株式会社 用输入信号的零交叉特性检测相差的装置及其锁相环电路
EP1422827A1 (en) * 2002-11-21 2004-05-26 STMicroelectronics Belgium N.V. Low frequency self-calibration of a PLL with multiphase clocks

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