US20080309376A1 - Mains Phase Detection Apparatus - Google Patents
Mains Phase Detection Apparatus Download PDFInfo
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- US20080309376A1 US20080309376A1 US12/093,532 US9353206A US2008309376A1 US 20080309376 A1 US20080309376 A1 US 20080309376A1 US 9353206 A US9353206 A US 9353206A US 2008309376 A1 US2008309376 A1 US 2008309376A1
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- 238000001514 detection method Methods 0.000 title claims abstract description 45
- 230000000630 rising effect Effects 0.000 claims description 16
- 238000001914 filtration Methods 0.000 claims description 2
- 230000001960 triggered effect Effects 0.000 claims description 2
- 238000005070 sampling Methods 0.000 abstract description 4
- 238000004891 communication Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
Definitions
- the present invention relates to a phase detection apparatus, more particularly to a mains phase detection apparatus.
- phase/frequency monitoring it is required to detect the phase/frequency of a power line in various application fields, such as mains frequency monitoring, phase-controlled rectification, and mains phase detection in a power line carrier communication.
- a zero-crossing detection method is employed by conventional mains phase/frequency detection, i.e., a zero-crossing point is detected by a comparator, and a cycle and a frequency of the mains are then obtained by calculating the time interval between zero-crossing points.
- Such method has the advantage of a high detecting speed, simplicity and reliability.
- the appearing time of the zero-crossing points will be affected, which thus causes it is impossible to obtain a detecting result with a high precision from such a simple zero-crossing detection method.
- the present invention provides a mains phase detection apparatus to overcome the deficiencies existing in the prior art.
- the detection apparatus is capable of effectively improving the detection precision for the mains phase.
- an all-digital phase-locked loop with a high precision is added after a zero-crossing detector to provide a detection performance with an extremely high precision.
- the present invention provides a mains phase detection apparatus including a zero-crossing detector and an all-digital phase-locked loop.
- the all-digital phase-locked loop includes a digital phase detector, a digital loop filter and a digital controlled oscillator which are sequentially coupled. An output terminal of the digital controlled oscillator and an output terminal of the zero-crossing detector are connected to an input terminal of the digital phase detector.
- the digital phase detector includes an exclusive-OR gate.
- the digital loop filter includes: an accumulator, a proportion regulator, an integrator, a first adder, and a second adder.
- An input terminal of the accumulator is connected to an output terminal of the digital phase detector.
- Input terminals of the proportion regulator and the integrator are connected to an output terminal of the accumulator.
- Two input terminals of the first adder are connected to output terminals of the proportion regulator and the integrator, respectively.
- the second adder has two input terminals, one input terminal thereof is connected to an output terminal of the first adder, and the other input terminal thereof is set with an initial frequency word.
- the initial frequency word corresponds to a frequency between 53 ⁇ 57 Hz.
- the initial frequency word corresponds to a frequency of 55 Hz.
- the mains phase detection apparatus further includes a rising edge detector that is triggered by a rising edge of an output signal of the zero-crossing detector to generate a detecting pulse.
- the rising edge detector outputs the detecting pulse to the accumulator of the loop filter.
- the accumulator is reset responsive to the detecting pulse, and accumulates an output signal of the phase detector between two of the detecting pulses.
- the digital controlled oscillator includes a phase accumulator.
- An input terminal of the phase accumulator is connected to an output terminal of the digital loop filter.
- the MSB (Most Significant Bit) of the phase accumulator is an output signal output to the digital phase detector.
- FIG. 1 is a block diagram of a mains phase detection apparatus of the present invention.
- FIG. 2 is a block diagram of a preferred embodiment of the mains phase detection apparatus of the present invention.
- FIG. 3 is a block diagram of a loop filter of the mains phase detection apparatus illustrated in FIG. 2 .
- FIG. 4 is a block diagram of an integrator of the mains phase detection apparatus illustrated in FIG. 2 .
- FIG. 5 is a block diagram of a phase accumulator of the mains detection apparatus illustrated in FIG. 2 .
- FIG. 6 is an illustrative diagram of waveforms at various points of the mains phase detection apparatus illustrated in FIG. 2 .
- FIG. 7 is an illustrative diagram of waveforms at various points of the loop filter illustrated in FIG. 3 .
- FIG. 8 is an illustrative diagram of waveforms at various points of the phase accumulator illustrated in FIG. 5 .
- a mains phase detection apparatus of the present invention includes a zero-crossing detector 110 , and an all-digital phase-locked loop constructed with a digital phase detector 111 , a digital loop filter 112 and a digital controlled oscillator 113 .
- an analog signal obtained by sampling the mains is shaped by the zero-crossing detector (comparator) 110 .
- the mains signal is converted from a sinusoidal wave with distortion to a square signal, which is sampled then by a clock signal to generate a 1 bit digital signal.
- the digital phase detector 111 of the phase-locked loop implement a phase comparison between an external input digital signal and an output signal of the digital controlled oscillator 113 (typically performed by a component with multiplication characteristics).
- the digital loop filter 112 implements low-pass filtering to generate an error control signal for adjusting the frequency of the output signal of the digital controlled oscillator 113 , thus to make it have a zero phase difference with the input signal. Since the all-digital phase-locked loop has an accurate phase tracking functionality, a detection performance with an extremely high precision can be achieved by applying it in the mains phase detection.
- the zero-crossing detector 110 may be implemented using a conventional technique.
- the internal architecture thereof is thus not further described herein. People skilled in the art may implement it utilizing a conventional technique or prior art according to the previous description.
- FIG. 2 is a block diagram of a preferred embodiment of the mains phase detection apparatus of the present invention.
- FIG. 6 is an illustrative diagram of waveforms at various points of the mains phase detection apparatus illustrated in FIG. 2 .
- a zero-crossing detector 121 also shapes the analog signal obtained by sampling the mains, and converts the mains signal from a sinusoidal wave with distortion to a square signal, which is then sampled by a clock signal to generate a 1 bit 50 Hz digital signal a.
- the all-digital phase-locked loop includes a rising edge detector 122 , an exclusive-OR (XOR) phase detector 123 , a loop filter 124 and a phase accumulator 125 used as a digital controlled oscillator.
- the phase detector 123 perform phase detection upon the input signal a required to be tracked and an output signal b of the phase accumulator 125 (i.e., the digital controlled oscillator). Since the input signal a is a 1 bit digital signal and the output signal b of the phase accumulator 125 is also a square signal (can also be represented by a 1 bit signal), the multiplication operation required to be implemented by the phase detector 123 merely requires 1 bit multiplying 1-bit. Therefore, the phase detector herein may be simplified as an exclusive-OR gate.
- the rising edge detector 122 detects a rising edge of the output signal a, and therefore generates a detecting pulse signal d, which is used to control the operations of the loop filter 124 and the phase accumulator 125 , the process of which will be described below.
- FIG. 3 is a block diagram of the loop filter 124 in FIG. 2
- FIG. 7 is an illustrative diagram of waveforms at various points of the loop filter illustrated in FIG. 3
- the loop filter 124 is constructed with a first order loop, including an accumulator 130 , a proportion regulator 131 , an integrator 132 , a first adder 133 and a second adder 134 .
- An input terminal of the accumulator 130 is connected to an output terminal of the phase detector 123 .
- the accumulator 130 is used to accumulatively account the output signal a of the phase detector 123 , thus to perform the conversion from 1 bit data to data with a specific phase.
- the detailed accumulating process includes: at a rising edge of the output signal a of the zero-crossing detector 121 , the accumulator 130 receives a detecting pulse of the rising edge detector 122 and thus is assigned an initial value (i.e., reset, the reset value is zero); the accumulator 130 then accumulates an output signal c of the phase detector 123 between two rising edges of the signal a (i.e., two detecting pulses of the rising edge detector 122 ), and the output signal thereof is e 0 .
- FIG. 4 illustrates a block diagram of an embodiment of the integrator 132 .
- the integrator 132 consists of a 19-bit adder 141 and a 19-bit delay unit 142 .
- An input of the adder 141 is the output signal e 0 of the accumulator 130 , and another input is an output of the delay unit 142 .
- an output of the adder 141 is stored by the delay unit 142 .
- the outputs of the integrator 132 and the proportion regulator 131 are performed an addition operation at the first adder.
- An operation result e 2 thereof and an initial frequency word are then input into the second adder 134 .
- An output signal e of the second adder 134 is an output of the loop filter 124 .
- the aforementioned initial frequency word corresponds to an initial output frequency.
- the phase-locked loop can utilize the initial output frequency to ultimately implement phase-locking with the input signal a required to be tracked. Since alternative currents of two frequencies including 50 Hz and 60 Hz are employed currently in the world, preferably setting an initial frequency word corresponding to an initial output frequency between 53 Hz ⁇ 57 Hz can implement the phase-locking functionality for a 50 Hz or 60 Hz mains signal more simply, without configuring 50 Hz and 60 Hz initial frequency words respectively. More preferably, the initial frequency word corresponds to an initial output frequency of 55 Hz. Assume that the clock frequency in the system is 921.6 kHz and the bit-width of the phase accumulator is 31-bit, according to the formula:
- the initial frequency is 128159.
- the phase-locked loop with such a structure has a longer initial locking time, the specific number of which is determined by the system clock and the precision of the phase accumulator. Since there is not a very high requirement for the initial locking time in a practical system, the present structure may be employed.
- FIG. 5 is a block diagram of a phase accumulator
- FIG. 8 is an illustrative diagram of waveforms at various points of the phase accumulator illustrated in FIG. 5 .
- the phase accumulator 125 is a DDS (direct digital synthesized) structure and employs a system clock frequency being 921.6 kHz. It employs a 31-bit accumulator that has a structure similar to the structure of the integrator 132 in the loop filter 124 . The differences are that an adder 151 has a bit-width of 31-bit, and a delay unit 152 has a bit-width of 31-bit.
- the phase accumulator performs accumulation at each clock cycle.
- a circular cycle completes when the adder 151 overflows.
- the MSB of the adder 151 varies periodically, i.e., being the output signal b of the overall digital phase-locked loop.
- the phase of the output signal b is orthogonal with the input signal a required to be tracked (with a 90-degree difference).
- FIG. 6 is an illustrative diagram of waveforms at various points of the mains phase detection apparatus illustrated in FIG. 2 .
- the phase-locking process of the mains phase detection apparatus can be seen from FIG. 6 .
- the output signal a of the zero-crossing detector 121 is a 50 Hz square signal
- the signal b is the output signal of the digital phase-locked loop. It can be seen that the frequency of the output signal b initially is not consistent with the input signal a.
- the signal c is the output signal of the phase detector 123 .
- the output of the phase detector 123 has an apparent variation, which reflects the phase difference between the input signal a and the output signal b of the phase-locked loop, and when the output signal b of the loop has a frequency consistent with the frequency of the input signal a, the output of the phase detector 123 keeps unchanged.
- the signal d is the output signal of the rising edge detector 122 , and varies following the rising edges of the output signal a of the zero-crossing detector 123 .
- the signal e is the output signal of the loop filter.
- the output of the loop filter 124 varies apparently, rather than being maintained as an approximate constant, which reflects that the loop is in a capturing period, and when the output signal b of the loop has a frequency consistent with the frequency of the input signal a, the output signal of the loop filter is approximately maintained at a fixed constant 116508 that corresponds to the input frequency 50 Hz, which illustrates that the loop has been phased-locked with the 50 Hz input signal. Accordingly, the output signal b of the digital phase-locked loop is ultimately stably output and has the same frequency as the input signal a, with a phase difference of 90-degree.
- FIG. 7 further illustrates waveform outputs at various points in the operation process of the loop filter 124 .
- the signal e 0 is the output signal of the accumulator 130 .
- the accumulator 130 accumulates the output signal c of the phase detector 123 . It can be seen that when the loop just begins to operate, the output of the accumulator 130 has an apparent variation, and when the loop comes to a stable state, the output of the accumulator 130 keeps unchanged, and stabilizes at the amplitude of zero.
- the signal e 1 is the output signal of the integrator 132 , since the integrator 132 itself has a hysteresis effect, it can be seen that the output of the integrator 132 has a delay with respect to the output of the first adder 133 (including the output of the proportion regulator 131 ).
- the output of the integrator 132 has an apparent variation, and when the loop comes to a stable state, the output of the integrator 132 maintains unchanged, and stabilizes at the amplitude of ⁇ 48584.
- the signal e 2 is the output signal of the first adder 133 .
- the output of the first adder 133 When the loop just begins to operate, the output of the first adder 133 has an apparent variation, and when the loop comes to a stable state, the output of the first adder 133 maintains unchanged, and stabilizes at the amplitude of ⁇ 11651.
- the signal e is the output signal of the second adder 134 , i.e., the output of the loop filter 124 .
- the output of the second adder 134 has an apparent variation, and when the loop comes to a stable state, the output of the second adder 134 maintains unchanged, and stabilizes at the amplitude of 116508. It can be seen that with respect to the output of the first adder 133 , the second adder 134 only has a difference of the initial frequency word 128159.
- FIG. 8 illustrates waveform outputs at various points when the digital controlled oscillator is in operation.
- a signal b 1 is the output signal of the 31-bit accumulator and varies periodically.
- a signal b is the MSB output signal of the accumulator, i.e., the ultimate output of the overall digital phase-locked loop, and is a square wave output.
- the precision of the all-digital phase-locked loop of the present invention is determined by the bit-width of the phase accumulator 125 and the system clock.
- the mains phase detection apparatus of the present invention employs an all-digital loop architecture and a high frequency sampling clock to recover a signal with a phase orthogonal with that of the mains signal and a frequency the same as the mains signal. And jitters in the recovered signal are less than 10 us. Therefore, the present phase detection apparatus is capable of implementing signal tracking with a zero frequency error and a zero phase in a large range. It can provide a detection result of excellent performance for the power line carrier communication, mains frequency detection, etc. Since an all-digital manner is employed, both of the design and debug can be implemented by software. Therefore the cost is extremely decreased, and also the device consistency problem brought by employing an analog phase-locked loop can be avoided.
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Abstract
Description
- The present invention relates to a phase detection apparatus, more particularly to a mains phase detection apparatus.
- It is required to detect the phase/frequency of a power line in various application fields, such as mains frequency monitoring, phase-controlled rectification, and mains phase detection in a power line carrier communication.
- A zero-crossing detection method is employed by conventional mains phase/frequency detection, i.e., a zero-crossing point is detected by a comparator, and a cycle and a frequency of the mains are then obtained by calculating the time interval between zero-crossing points. Such method has the advantage of a high detecting speed, simplicity and reliability. However, since there is a large amount of noise and interference on the power line, the appearing time of the zero-crossing points will be affected, which thus causes it is impossible to obtain a detecting result with a high precision from such a simple zero-crossing detection method.
- The present invention provides a mains phase detection apparatus to overcome the deficiencies existing in the prior art. The detection apparatus is capable of effectively improving the detection precision for the mains phase.
- In the mains phase detection apparatus of the present invention, an all-digital phase-locked loop with a high precision is added after a zero-crossing detector to provide a detection performance with an extremely high precision.
- The present invention provides a mains phase detection apparatus including a zero-crossing detector and an all-digital phase-locked loop. The all-digital phase-locked loop includes a digital phase detector, a digital loop filter and a digital controlled oscillator which are sequentially coupled. An output terminal of the digital controlled oscillator and an output terminal of the zero-crossing detector are connected to an input terminal of the digital phase detector.
- In the mains phase detection apparatus, the digital phase detector includes an exclusive-OR gate.
- In the mains phase detection apparatus, the digital loop filter includes: an accumulator, a proportion regulator, an integrator, a first adder, and a second adder. An input terminal of the accumulator is connected to an output terminal of the digital phase detector. Input terminals of the proportion regulator and the integrator are connected to an output terminal of the accumulator. Two input terminals of the first adder are connected to output terminals of the proportion regulator and the integrator, respectively. The second adder has two input terminals, one input terminal thereof is connected to an output terminal of the first adder, and the other input terminal thereof is set with an initial frequency word.
- In the mains phase detection apparatus, the initial frequency word corresponds to a frequency between 53˜57 Hz.
- In the mains phase detection apparatus, the initial frequency word corresponds to a frequency of 55 Hz.
- The mains phase detection apparatus further includes a rising edge detector that is triggered by a rising edge of an output signal of the zero-crossing detector to generate a detecting pulse. The rising edge detector outputs the detecting pulse to the accumulator of the loop filter. The accumulator is reset responsive to the detecting pulse, and accumulates an output signal of the phase detector between two of the detecting pulses.
- In the mains phase detection apparatus, the digital controlled oscillator includes a phase accumulator. An input terminal of the phase accumulator is connected to an output terminal of the digital loop filter. The MSB (Most Significant Bit) of the phase accumulator is an output signal output to the digital phase detector.
- The features and performances of the present invention will be further described through the following embodiments and in conjunction with the accompany drawings, in which:
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FIG. 1 is a block diagram of a mains phase detection apparatus of the present invention. -
FIG. 2 is a block diagram of a preferred embodiment of the mains phase detection apparatus of the present invention. -
FIG. 3 is a block diagram of a loop filter of the mains phase detection apparatus illustrated inFIG. 2 . -
FIG. 4 is a block diagram of an integrator of the mains phase detection apparatus illustrated inFIG. 2 . -
FIG. 5 is a block diagram of a phase accumulator of the mains detection apparatus illustrated inFIG. 2 . -
FIG. 6 is an illustrative diagram of waveforms at various points of the mains phase detection apparatus illustrated inFIG. 2 . -
FIG. 7 is an illustrative diagram of waveforms at various points of the loop filter illustrated inFIG. 3 . -
FIG. 8 is an illustrative diagram of waveforms at various points of the phase accumulator illustrated inFIG. 5 . - Please refer to
FIG. 1 , a mains phase detection apparatus of the present invention includes a zero-crossing detector 110, and an all-digital phase-locked loop constructed with adigital phase detector 111, adigital loop filter 112 and a digital controlled oscillator 113. Firstly, an analog signal obtained by sampling the mains is shaped by the zero-crossing detector (comparator) 110. Thus, the mains signal is converted from a sinusoidal wave with distortion to a square signal, which is sampled then by a clock signal to generate a 1 bit digital signal. Thedigital phase detector 111 of the phase-locked loop implement a phase comparison between an external input digital signal and an output signal of the digital controlled oscillator 113 (typically performed by a component with multiplication characteristics). Thedigital loop filter 112 implements low-pass filtering to generate an error control signal for adjusting the frequency of the output signal of the digital controlled oscillator 113, thus to make it have a zero phase difference with the input signal. Since the all-digital phase-locked loop has an accurate phase tracking functionality, a detection performance with an extremely high precision can be achieved by applying it in the mains phase detection. - In an embodiment of
FIG. 1 , the zero-crossing detector 110 may be implemented using a conventional technique. The internal architecture thereof is thus not further described herein. People skilled in the art may implement it utilizing a conventional technique or prior art according to the previous description. - Please refer to
FIG. 6 while referring toFIG. 2 .FIG. 2 is a block diagram of a preferred embodiment of the mains phase detection apparatus of the present invention.FIG. 6 is an illustrative diagram of waveforms at various points of the mains phase detection apparatus illustrated inFIG. 2 . In the present embodiment, a zero-crossing detector 121 also shapes the analog signal obtained by sampling the mains, and converts the mains signal from a sinusoidal wave with distortion to a square signal, which is then sampled by a clock signal to generate a 1 bit 50 Hz digital signal a. The all-digital phase-locked loop includes a risingedge detector 122, an exclusive-OR (XOR)phase detector 123, aloop filter 124 and aphase accumulator 125 used as a digital controlled oscillator. Thephase detector 123 perform phase detection upon the input signal a required to be tracked and an output signal b of the phase accumulator 125 (i.e., the digital controlled oscillator). Since the input signal a is a 1 bit digital signal and the output signal b of thephase accumulator 125 is also a square signal (can also be represented by a 1 bit signal), the multiplication operation required to be implemented by thephase detector 123 merely requires 1 bit multiplying 1-bit. Therefore, the phase detector herein may be simplified as an exclusive-OR gate. The risingedge detector 122 detects a rising edge of the output signal a, and therefore generates a detecting pulse signal d, which is used to control the operations of theloop filter 124 and thephase accumulator 125, the process of which will be described below. - Please refer to
FIG. 7 while referring toFIG. 3 .FIG. 3 is a block diagram of theloop filter 124 inFIG. 2 , andFIG. 7 is an illustrative diagram of waveforms at various points of the loop filter illustrated inFIG. 3 . Theloop filter 124 is constructed with a first order loop, including anaccumulator 130, aproportion regulator 131, anintegrator 132, afirst adder 133 and asecond adder 134. An input terminal of theaccumulator 130 is connected to an output terminal of thephase detector 123. Theaccumulator 130 is used to accumulatively account the output signal a of thephase detector 123, thus to perform the conversion from 1 bit data to data with a specific phase. The detailed accumulating process includes: at a rising edge of the output signal a of the zero-crossing detector 121, theaccumulator 130 receives a detecting pulse of the risingedge detector 122 and thus is assigned an initial value (i.e., reset, the reset value is zero); theaccumulator 130 then accumulates an output signal c of thephase detector 123 between two rising edges of the signal a (i.e., two detecting pulses of the rising edge detector 122), and the output signal thereof is e0. Input terminals of theproportion regulator 131 and theintegrator 132 are both connected to an output terminal of theaccumulator 130, wherein theproportion regulator 131 is used to weight the output signal e0 of theaccumulator 130, and theintegrator 132 accumulates the output signal e0 of theaccumulator 130 and outputs a signal e1. The detailed accumulating process includes: at a rising edge of the output signal a, theintegrator 132 receives the detecting pulse from the risingedge detector 122 and perform accumulation upon the pulse.FIG. 4 illustrates a block diagram of an embodiment of theintegrator 132. Theintegrator 132 consists of a 19-bit adder 141 and a 19-bit delay unit 142. An input of theadder 141 is the output signal e0 of theaccumulator 130, and another input is an output of thedelay unit 142. At a rising edge of the output signal a, an output of theadder 141 is stored by thedelay unit 142. The outputs of theintegrator 132 and theproportion regulator 131 are performed an addition operation at the first adder. An operation result e2 thereof and an initial frequency word are then input into thesecond adder 134. An output signal e of thesecond adder 134 is an output of theloop filter 124. - The aforementioned initial frequency word corresponds to an initial output frequency. The phase-locked loop can utilize the initial output frequency to ultimately implement phase-locking with the input signal a required to be tracked. Since alternative currents of two frequencies including 50 Hz and 60 Hz are employed currently in the world, preferably setting an initial frequency word corresponding to an initial output frequency between 53 Hz˜57 Hz can implement the phase-locking functionality for a 50 Hz or 60 Hz mains signal more simply, without configuring 50 Hz and 60 Hz initial frequency words respectively. More preferably, the initial frequency word corresponds to an initial output frequency of 55 Hz. Assume that the clock frequency in the system is 921.6 kHz and the bit-width of the phase accumulator is 31-bit, according to the formula:
-
55×231/921.6/1000□128159□ - it is known that the initial frequency is 128159. The phase-locked loop with such a structure has a longer initial locking time, the specific number of which is determined by the system clock and the precision of the phase accumulator. Since there is not a very high requirement for the initial locking time in a practical system, the present structure may be employed.
- Please refer to
FIG. 8 while referring toFIG. 5 .FIG. 5 is a block diagram of a phase accumulator, andFIG. 8 is an illustrative diagram of waveforms at various points of the phase accumulator illustrated inFIG. 5 . Thephase accumulator 125 is a DDS (direct digital synthesized) structure and employs a system clock frequency being 921.6 kHz. It employs a 31-bit accumulator that has a structure similar to the structure of theintegrator 132 in theloop filter 124. The differences are that anadder 151 has a bit-width of 31-bit, and adelay unit 152 has a bit-width of 31-bit. The phase accumulator performs accumulation at each clock cycle. A circular cycle completes when theadder 151 overflows. The MSB of theadder 151 varies periodically, i.e., being the output signal b of the overall digital phase-locked loop. The phase of the output signal b is orthogonal with the input signal a required to be tracked (with a 90-degree difference). -
FIG. 6 is an illustrative diagram of waveforms at various points of the mains phase detection apparatus illustrated inFIG. 2 . The phase-locking process of the mains phase detection apparatus can be seen fromFIG. 6 . The output signal a of the zero-crossingdetector 121 is a 50 Hz square signal, and the signal b is the output signal of the digital phase-locked loop. It can be seen that the frequency of the output signal b initially is not consistent with the input signal a. The signal c is the output signal of thephase detector 123. It can be seen that when the loop just begins to operate, the output of thephase detector 123 has an apparent variation, which reflects the phase difference between the input signal a and the output signal b of the phase-locked loop, and when the output signal b of the loop has a frequency consistent with the frequency of the input signal a, the output of thephase detector 123 keeps unchanged. The signal d is the output signal of the risingedge detector 122, and varies following the rising edges of the output signal a of the zero-crossingdetector 123. The signal e is the output signal of the loop filter. It can be seen that when the loop begins to operate, the output of theloop filter 124 varies apparently, rather than being maintained as an approximate constant, which reflects that the loop is in a capturing period, and when the output signal b of the loop has a frequency consistent with the frequency of the input signal a, the output signal of the loop filter is approximately maintained at a fixed constant 116508 that corresponds to the input frequency 50 Hz, which illustrates that the loop has been phased-locked with the 50 Hz input signal. Accordingly, the output signal b of the digital phase-locked loop is ultimately stably output and has the same frequency as the input signal a, with a phase difference of 90-degree. -
FIG. 7 further illustrates waveform outputs at various points in the operation process of theloop filter 124. The signal e0 is the output signal of theaccumulator 130. Theaccumulator 130 accumulates the output signal c of thephase detector 123. It can be seen that when the loop just begins to operate, the output of theaccumulator 130 has an apparent variation, and when the loop comes to a stable state, the output of theaccumulator 130 keeps unchanged, and stabilizes at the amplitude of zero. The signal e1 is the output signal of theintegrator 132, since theintegrator 132 itself has a hysteresis effect, it can be seen that the output of theintegrator 132 has a delay with respect to the output of the first adder 133 (including the output of the proportion regulator 131). When the loop just begins to operate, the output of theintegrator 132 has an apparent variation, and when the loop comes to a stable state, the output of theintegrator 132 maintains unchanged, and stabilizes at the amplitude of −48584. The signal e2 is the output signal of thefirst adder 133. When the loop just begins to operate, the output of thefirst adder 133 has an apparent variation, and when the loop comes to a stable state, the output of thefirst adder 133 maintains unchanged, and stabilizes at the amplitude of −11651. The signal e is the output signal of thesecond adder 134, i.e., the output of theloop filter 124. When the loop just begins to operate, the output of thesecond adder 134 has an apparent variation, and when the loop comes to a stable state, the output of thesecond adder 134 maintains unchanged, and stabilizes at the amplitude of 116508. It can be seen that with respect to the output of thefirst adder 133, thesecond adder 134 only has a difference of theinitial frequency word 128159. -
FIG. 8 illustrates waveform outputs at various points when the digital controlled oscillator is in operation. A signal b1 is the output signal of the 31-bit accumulator and varies periodically. A signal b is the MSB output signal of the accumulator, i.e., the ultimate output of the overall digital phase-locked loop, and is a square wave output. - The precision of the all-digital phase-locked loop of the present invention is determined by the bit-width of the
phase accumulator 125 and the system clock. In an practical system, the clock frequency is 921.6 kHz and thephase accumulator 125 is 31-bit, thus the frequency resolution of the system is 921.6 k/231=0.43×10−3 Hz, which can satisfy the requirement of system design. - The mains phase detection apparatus of the present invention employs an all-digital loop architecture and a high frequency sampling clock to recover a signal with a phase orthogonal with that of the mains signal and a frequency the same as the mains signal. And jitters in the recovered signal are less than 10 us. Therefore, the present phase detection apparatus is capable of implementing signal tracking with a zero frequency error and a zero phase in a large range. It can provide a detection result of excellent performance for the power line carrier communication, mains frequency detection, etc. Since an all-digital manner is employed, both of the design and debug can be implemented by software. Therefore the cost is extremely decreased, and also the device consistency problem brought by employing an analog phase-locked loop can be avoided.
Claims (7)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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CN200510110391 | 2005-11-16 | ||
CNA2005101103913A CN1968019A (en) | 2005-11-16 | 2005-11-16 | All-digital phase-lock loop used for precision testing of city electricity |
CN200510110391.3 | 2005-11-16 | ||
PCT/CN2006/003082 WO2007056950A1 (en) | 2005-11-16 | 2006-11-16 | Phase detecting device for city power |
Publications (2)
Publication Number | Publication Date |
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US20080309376A1 true US20080309376A1 (en) | 2008-12-18 |
US7646225B2 US7646225B2 (en) | 2010-01-12 |
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US12/093,532 Expired - Fee Related US7646225B2 (en) | 2005-11-16 | 2006-11-16 | Mains phase detection apparatus |
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US (1) | US7646225B2 (en) |
EP (1) | EP1953917A4 (en) |
CN (1) | CN1968019A (en) |
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US20100150215A1 (en) * | 2007-03-14 | 2010-06-17 | Northern Microdesign, Inc. | Use of powerlines for transmission of high frequency signals |
US8872558B1 (en) * | 2013-05-24 | 2014-10-28 | Intel IP Corporation | Hybrid phase-locked loops |
US8922253B2 (en) | 2013-05-24 | 2014-12-30 | Intel IP Corporation | Hybrid phase-locked loops |
US8938291B1 (en) * | 2009-10-16 | 2015-01-20 | Blackrock Microsystems, LLC | Methods and systems for signal processing of neural data |
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CN101594147B (en) * | 2008-05-29 | 2011-08-24 | 中芯国际集成电路制造(北京)有限公司 | Phase-locked loop circuit |
US8031025B2 (en) * | 2009-03-16 | 2011-10-04 | Mediatek Inc. | Mixed-mode PLL |
US8102195B2 (en) * | 2009-05-13 | 2012-01-24 | Mediatek Inc. | Digital phase-locked loop circuit including a phase delay quantizer and method of use |
US8868364B2 (en) * | 2011-04-29 | 2014-10-21 | Analog Devices, Inc. | Apparatus and method for real time harmonic spectral analyzer |
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US10236897B1 (en) * | 2018-07-26 | 2019-03-19 | Texas Instruments Incorporated | Loss of lock detector |
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US11157057B1 (en) | 2020-05-28 | 2021-10-26 | Ovh | Systems and methods for electric systems monitoring and/or failure detection |
US11489553B1 (en) | 2021-04-13 | 2022-11-01 | Ovh | System and method for identifying a connection between a power distribution unit and an electric device |
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Also Published As
Publication number | Publication date |
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WO2007056950A1 (en) | 2007-05-24 |
CN1968019A (en) | 2007-05-23 |
US7646225B2 (en) | 2010-01-12 |
EP1953917A1 (en) | 2008-08-06 |
EP1953917A4 (en) | 2012-07-25 |
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