CN101594147B - Phase-locked loop circuit - Google Patents

Abstract

A phase-locked loop circuit comprises a time detector, a divider, a digital loop filter with the transfer function of (alpha (z-1)+rho/(z-1)) and a digitally controlled oscillator with the transfer function of (z<-1>)/(1-z<-1>); wherein, the time detector is used for outputting a first digital signal; the first digital signal is used for representing the difference between a periodic accumulated value of a reference clock signal and the periodic accumulated value of a feedback clock signal in a time domain; the periodic accumulated value of the feedback clock signal represents the product of the periodic accumulated value and the frequency of a synthesizer clock signal in the time domain; the divider is used for dividing the first digital signal by the frequency and outputting a second digital signal; the digital loop filter is used for accumulating the second digital signal and outputting digital control signals; the digitally controlled oscillator is used for generating the synthesizer clock signal according to the digital control signals. The phase-locked loop circuit has the characteristics of simple structure, low power consumption and stable property.

Description

Phase-locked loop circuit

Technical field

The present invention relates to phase-locked loop circuit, particularly relate to a kind of all-digital phase-locked loop circuit.

Background technology

Phase-locked loop (PLL, Phase Locked Loop) typically refers to a kind of circuit that is applied in the communication control processor, and its effect is that the signal that comprises clock that receives is handled, and therefrom extracts the phase information of certain clock.In other words, for the signal that receives, imitated clock signal makes that the signal that receives is synchronous or relevant with imitated clock signal from certain viewpoint of measures.Because imitated clock signal has certain differing with respect to the clock signal in the received signal, therefore be also referred to as phase locking unit.Phase-locked loop has many types, can be digital, simulation or the digital-to-analogue mixing.

Mentioned a kind of all-digital phase-locked loop (ADPLL, All Digital Phase Locked Loop) among the U.S. Patent Application Publication specification US6809598.With reference to shown in Figure 1, described all-digital phase-locked loop is used for the differing of feedback clock signal Rv (k) of input reference clock signal CHANNEL that comparison receives and self output signal, and according to described differing the synthetic clock signal fv of back output is adjusted in the output of self.

Described all-digital phase-locked loop comprises: be used for phase detectors (Phase Detector) P13 that differing of described input reference clock signal CHANNEL and feedback clock signal Rv (k) calculated, be used for the output of phase detectors P13 is carried out loop gain multiplier (Loop Gain ALPHAMultiplier) P14 and the adder P15 of filtering, be used for producing digital controlled oscillator gain adjustment (DCO Gain Normalization) the unit P16 that adjusts signal OTW according to the output result of adder P15, and digital controlled oscillator (DCO, the Digitally Controlled Oscillator) P17 that is used for the output of self being adjusted and being exported synthetic clock signal fv according to the adjustment signal OTW of digital controlled oscillator gain adjusting unit P16 output.Wherein, the end input of phase detectors P13 comes from the output of fixed phase accumulator (ReferencePhase Accumulator) P11, and described fixed phase accumulator P11 comes the computes integer periodic phase in conjunction with the reference clock signal CHANNEL and the frequency control signal FCW of input; The other end input of described phase detectors P13 comes from the output feedback of phase-locked loop self, be the feedback of the synthetic clock signal of digital controlled oscillator P17 output, described synthetic clock signal is transported to phase detectors P13 after oscillation phase accumulator (OscillatorPhase Accumulator) P12 carries out accumulating operation.The end input of adder P15 comes from loop gain multiplier P14, and other end input comes from direct adjustment (DirectModulation) unit P18, is used for the slight error adjustment is carried out in the output of loop gain multiplier P14.

What the phase detectors P13 of phase-locked loop shown in Figure 1 exported is phase difference signal, and phase-locked loop is based on the framework of phase field (Phase Domain).For all-digital phase-locked loop, above-mentioned differing can be passed through time-to-digit converter (TDC, Time to Digital Converter, not shown) and be converted to digital signal, the effect of described time-to-digit converter is that the time is converted to digital signal, and normally obtain digital signal input time by mating the time of delay of delay chain, because the mode of this delay chain, can't well set up the corresponding relation of frequency interval of the controlled minimum of the delay of delay cell and digital controlled oscillator, can bring like this is that the gain of whole loop is no longer constant, causes the stability of a system relatively poor.So must through the multiplier (not shown) change into phase signal (1 cycle time correspondence phase place be 2 π), increase extra hardware circuit like this, and needed the extra direct adjustment unit P18 of increase that the slight error adjustment is carried out in the output of loop gain multiplier P14.

And the effect of digital controlled oscillator P17 is the clock signal of synthesizing certain frequency according to digital controlled signal, the control of its frequency is to realize by the mode that changes electric capacity, in this control procedure, the linearity of electric capacity changes, the change of frequency is not linear, but be inversely proportional to the condenser paper root, so non-linear meeting makes the gain of whole loop no longer constant, causes the stability of a system relatively poor.So just need to increase the linearity that extra digital controlled oscillator gain adjusting unit P16 adjusts digital controlled oscillator P17.

Above-mentioned these can increase the complexity of phase-locked loop circuit structure undoubtedly for improving the extra multiplier that increases of the stability of a system, direct adjustment unit and digital controlled oscillator gain adjusting unit, thereby make the area of phase-locked loop increase, and power consumption also increases.

Summary of the invention

The problem that the present invention solves is to provide a kind of stable phase-locked loop circuit, to simplify circuit structure, reduction area and power consumption.

For addressing the above problem, embodiment of the present invention provides a kind of phase-locked loop circuit, comprising:

Time detector, be used to export first digital signal, described first digital signal is used to represent periodic accumulation value poor of the periodic accumulation value of reference clock signal and feedback clock signal on time-domain, the periodic accumulation value of described feedback clock signal is expressed as the periodic accumulation value of synthetic clock signal and the product of divider ratio on time-domain;

Divider, first digital signal that is used for described time detector is exported is exported second digital signal divided by divider ratio;

Digital loop filters, second digital signal of the described divider output that is used to add up, the output digital control signal, the transfer function of described digital loop filters is

α, ρ are Control Parameter;

Digital controlled oscillator is used for producing synthetic clock signal according to the digital control signal of described digital loop filters output, and the transfer function of described digital controlled oscillator is

Optionally, described phase-locked loop circuit comprises that also free ring shakes, and is used to provide multi-phase clock signal, and the cycle of described synthetic clock signal equals the product in the time interval on the effective edge edge of phase clock signal adjacent in digital control signal and the multi-phase clock signal.

Optionally, described time detector comprises:

Logical block is used for generating first signal according to the synthetic clock signal of reference clock signal and described digital controlled oscillator feedback; , as the cycle count maximum periodicity of described synthetic clock signal is counted with the divider ratio that obtained; At the effective edge of reference clock signal along calculating the peaked residue no count of the described relatively cycle count of the current number of count cycle value, the three digital signal of output representative residue no count corresponding time of value, described three digital signal equal the digital control signal of described digital loop filters output and the product of residue no count value;

Described time-to-digit converter is used under the multi-phase clock signal that provides is provided described free ring respectively the instantaneous value of first signal of described logical block output is formed discrete signal; As discrete signal represent respectively described first signal to effective edge along upset or from effective edge along when upset, the distance between described two discrete signals is exported with the 4th digital signal;

Adder is used for the three digital signal of described logical block output and the 4th digital signal of described time-to-digit converter output are carried out add operation, exports first digital signal.

Optionally, described digital loop filters comprises: first multiplier, second multiplier, the 3rd adder, the 4th adder and transfer function are z ^-1Delay unit, the multiplication factor of described first multiplier is Control Parameter α, the multiplication factor of described second multiplier is Control Parameter ρ, wherein, described second digital signal obtains an input of described the 3rd adder through described first multiplier, described second digital signal obtains an input of described the 4th adder through described second multiplier, described the 4th adder is output as another input of described the 3rd adder, the output of described the 4th adder obtains another input of described the 4th adder behind described delay unit, described the 3rd adder is output as described digital control signal.

Optionally, described digital controlled oscillator comprises:

First adder and second adder, being respectively applied for adds up to the digital control signal that is received obtains corresponding selection address;

First latch, second latch are used for the selection address sampling of described first adder output is deposited, and sampling clock is the inversion signal of the synthetic clock signal of output;

The 3rd latch, quad latch are used for the selection address sampling of described second adder output is deposited, and sampling clock is respectively the inversion signal and the synthetic clock signal of the synthetic clock signal of output;

The first clock selecting unit and second clock selected cell are respectively applied for the selection address according to described second latch and quad latch output, select the output of respective phase clock signal from the phase clock signal that is received;

The first lap selected cell and the second circle selected cell, be respectively applied for the effective impulse of the phase clock signal of the described first clock selecting unit and second clock selected cell output is counted, count results and the digital control signal that is received are compared, and produce the selection signal that is used to select phase clock signal effective edge edge according to comparative result and the digital control signal that is received;

The 5th latch and the 6th latch, be respectively applied for selection signal according to the described first lap selected cell and the second circle selected cell output, at the corresponding effective edge of the phase clock signal of described very first time selected cell and the output of the second selection of time unit along the described phase clock signal of output;

The 3rd clock selecting unit is used for the phase clock signal of selecting the 5th latch or the 6th latch to export according to the synthetic clock signal on the selecting side;

The output signal unit is used for when the phase clock signal of described the 3rd clock selecting unit output is effective the synthetic clock signal of output.

Phase-locked loop framework compared to existing technology based on phase field, the time detector of technique scheme deducts the periodic accumulation value of reference clock signal the periodic accumulation value (promptly the periodic accumulation of synthetic clock signal is on duty with divider ratio) of feedback clock signal on time-domain, the output signal that obtains is the digital signal that is used for express time; And make up the transfer function of whole loop by the transfer function of setting digital loop filters and digital controlled oscillator, therefore, above-mentioned phase-locked loop circuit is based on the framework of time-domain, only need set the Control Parameter of digital loop filters, just can be subjected to the loop damping factor of divider ratio, incoming frequency, output frequency and process variations influence, and the natural resonance frequency that is directly proportional with incoming frequency.Based on the all-digital phase-locked loop circuit of above-mentioned architecture design need not extra increase with time signal change into phase signal multiplier, be used for the direct adjustment unit of slight error adjustment and be used to adjust the digital controlled oscillator gain adjusting unit of the linearity of digital controlled oscillator, thereby circuit structure is simple, power consumption is also less, area is less, and is a more stable system.

For addressing the above problem, embodiment of the present invention also provides a kind of phase-locked loop circuit, comprising:

Time detector is used to export first digital signal, and described first digital signal is used to represent periodic accumulation value poor of the periodic accumulation value of reference clock signal and synthetic clock signal on time-domain;

Digital loop filters, first digital signal of the described time detector output that is used to add up, the output digital control signal, the transfer function of described digital loop filters is

α, ρ are Control Parameter;

Digital controlled oscillator is used for producing described synthetic clock signal according to the digital control signal of described digital loop filters output, and the transfer function of described digital controlled oscillator is

Phase-locked loop framework compared to existing technology based on phase field, the time detector of technique scheme deducts the periodic accumulation value of reference clock signal the periodic accumulation value of synthetic clock signal on time-domain, the output signal that obtains is the digital signal that is used for express time; And make up the transfer function of whole loop by the transfer function of setting digital loop filters and digital controlled oscillator, therefore, above-mentioned phase-locked loop circuit is based on the framework of time-domain, only need set the Control Parameter of digital loop filters, just can be subjected to the loop damping factor of divider ratio, incoming frequency, output frequency and process variations influence, and the natural resonance frequency that is directly proportional with incoming frequency.Based on the all-digital phase-locked loop circuit of above-mentioned architecture design need not extra increase with time signal change into phase signal multiplier, be used for the direct adjustment unit of slight error adjustment and be used to adjust the digital controlled oscillator gain adjusting unit of the linearity of digital controlled oscillator, thereby circuit structure is simple, power consumption is also less, area is less, and is a more stable system.

Description of drawings

Fig. 1 is the structural representation of existing a kind of all-digital phase-locked loop circuit;

Fig. 2 is the basic structure schematic diagram of the phase-locked loop circuit of embodiment of the present invention;

Fig. 3 is the structural representation of the phase-locked loop circuit of the embodiment of the invention;

Fig. 4 is the timing diagram of the reference clock signal of the phase-locked loop circuit of the embodiment of the invention, synthetic clock signal, first signal, three digital signal and the 4th digital signal;

Fig. 5 is the structural representation of an embodiment of time-to-digit converter shown in Figure 3;

Fig. 6 is the structural representation of the embodiment of pulse unit shown in Figure 5;

Fig. 7 is the structural representation of the embodiment of commencing signal unit shown in Figure 5;

Fig. 8 is the structural representation of the embodiment of end signal unit shown in Figure 5;

Fig. 9 is the structural representation of embodiment of the encoder of first coding unit shown in Figure 5;

Figure 10 is the structural representation of another embodiment of time-to-digit converter shown in Figure 3;

Figure 11 is the structural representation of the embodiment of assembled unit shown in Figure 10;

Figure 12 is the structural representation of the embodiment of digital loop filters shown in Figure 3;

Figure 13 is the structural representation of the embodiment of digital controlled oscillator shown in Figure 3;

Figure 14 is the structural representation of an embodiment of first lap selected cell shown in Figure 13;

Figure 15 is the structural representation of the embodiment of first counting unit shown in Figure 14;

Figure 16 is the structural representation of the embodiment of first comparing unit shown in Figure 14;

Figure 17 is the structural representation of another embodiment of first lap selected cell shown in Figure 13.

Embodiment

Embodiment of the present invention is by make up the transfer function of phase-locked loop circuit in time-domain (Time Domain), to obtain stable system.

Fig. 2 is the basic block diagram of the phase-locked loop circuit of embodiment of the present invention, and the phase-locked loop circuit shown in the figure can all be realized by digital circuit, therefore can be called the all-digital phase-locked loop circuit again.Phase-locked loop circuit shown in Figure 2 comprises: time detector P1, divider P2, digital loop filters P3 and digital controlled oscillator P4.

Time detector P1, be used to export first digital signal, described first digital signal is used to represent periodic accumulation value poor of the periodic accumulation value of reference clock signal and feedback clock signal on time-domain, the periodic accumulation value of described feedback clock signal is expressed as the periodic accumulation value of synthetic clock signal and the product of divider ratio on time-domain;

Divider P2, first digital signal that is used for described time detector P1 is exported is exported second digital signal divided by divider ratio N;

Digital loop filters P3, second digital signal of the described divider P2 output that is used to add up, the output digital control signal, the transfer function of described digital loop filters P3 is

α, ρ are Control Parameter;

Digital controlled oscillator P4 is used for producing synthetic clock signal according to the control signal of described digital loop filters P3 output, and the transfer function of described digital controlled oscillator P4 is

Wherein, the cycle of described synthetic clock signal equals the product in the time interval on the effective edge edge of phase clock signal adjacent in digital control signal and the multi-phase clock signal, and described multi-phase clock signal is shaken by free ring to be provided.

On specific implementation, time detector P1 shown in Figure 2 is used to detect the effective edge of reference clock signal and feedback clock signal along (rising edge or trailing edge), for example the rising edge of reference clock signal is compared with the rising edge of feedback clock signal, perhaps, the trailing edge of reference clock signal is compared the time difference of exporting both with the form (i.e. first digital signal) of digital signal with the trailing edge of feedback clock signal.The function of time detector P1 shows as reference clock signal and ceaselessly adds up its cycle on time domain, the cycle of adding up with feedback clock signal subtracts each other then, and the function of frequency divider in the phase field shows as on time domain accordingly the periodic accumulation of the synthetic clock signal periodic accumulation value that obtains feedback clock signal with divider ratio N on duty.

The periodic accumulation value of reference clock signal can be according to the effective edge of reference clock signal cycle time along the reference clock signal that adds up, for example, the cycle of reference clock signal is 5ns, accumulator receive a reference clock signal on jump along the time just the periodic accumulation value is added 5ns.Similarly, the periodic accumulation value of synthetic clock signal can be synthesized the cycle time of clock signal along adding up according to the effective edge of synthetic clock signal.

In addition, at divider ratio N is 1 o'clock, first digital signal of time detector P1 output is directly inputted into digital loop filters P3 (promptly can contraction in division device P2), and the synthetic clock signal of digital controlled oscillator P4 output directly inputs to time detector P1 as feedback clock signal.

Usually, by the transfer function of constructing system, can analyze and judge the stability of system to system.The transfer function of the digital loop filters of the phase-locked loop circuit of embodiment of the present invention is

The transfer function of digital controlled oscillator is

The open loop of this phase-locked loop circuit so (disconnection feedback path) transfer function is: $\mathrm{Hopen}\left(z\right)=\frac{\mathrm{\&alpha;}(z-1)+\mathrm{\&rho;}}{{(z-1)}^2},$ The closed loop transmission function is:

$\mathrm{Hclose}\left(z\right)=\frac{\mathrm{Hopen}\left(z\right)}{1+\mathrm{Hopen}\left(z\right)}=\frac{\mathrm{\&alpha;}(z-1)+\mathrm{\&rho;}}{{(z-1)}^2+\mathrm{\&alpha;}(z-1)+\mathrm{\&sigma;}}---\left(1\right)$

Under the very little situation of s, have following approximate: $Z=e^{s/f_R}\&ap;1+\frac{s}{f_R},$ Wherein, s is the variable in Laplace transform territory, and z is the variable of z transform domain, f _RBe the frequency of reference clock signal, its substitution formula (1) obtained:

$\mathrm{Hclose}\left(s\right)=\frac{\mathrm{\&alpha;}(z-1)+\mathrm{\&rho;}}{{(z-1)}^2+\mathrm{\&alpha;}(z-1)+\mathrm{\&rho;}}=\frac{\mathrm{\&alpha;}{f}_{R}s+{\mathrm{\&rho;}{f}_R}^2}{s^2+{\mathrm{\&alpha;f}}_{R}s+{\mathrm{\&rho;}{f}_R}^2}---\left(2\right)$

In second order closed-loop control theory, the closed loop transmission function of phase-locked loop can be represented with following formula (3):

$\mathrm{Hclose}\left(s\right)=\frac{2{\mathrm{\&xi;\&omega;}}_{n}s+{{\mathrm{\&omega;}}_n}^s}{s^{2+}2{\mathrm{\&xi;\&omega;}}_{n}s+{{\mathrm{\&omega;}}_n}^2}---\left(3\right)$

Wherein, ξ is the damping factor of loop, ω _nBe natural resonance frequency, relatively formula (2), (3) can obtain 2 ξ ω _n=α f _R, ω _n ²=ρ f _R ², ${{\mathrm{\&omega;}}_n}^2={{\mathrm{\&rho;f}}_R}^2,$ That is:

$\mathrm{\&xi;}=\frac{1}{2}\&CenterDot;\frac{\mathrm{\&alpha;}}{\sqrt{\mathrm{\&rho;}}}---\left(4\right)$

${\mathrm{\&omega;}}_n=\sqrt{\mathrm{\&rho;}}{\&CenterDot;f}_R---\left(5\right)$

The damping factor ξ of loop and natural resonance frequency ω _nBe two the whether stable important parameters of system that are used to judge phase-locked loop circuit, can see from formula (4), the damping factor ξ of loop is only by the decision of the Control Parameter of digital loop filters, and all has nothing to do with frequency, output signal frequency, divider ratio and the technique change etc. of the input signal of phase-locked loop; Can see natural resonance frequency ω from formula (5) _nBe directly proportional with the frequency of the reference clock signal of importing.Therefore, the phase-locked loop circuit based on time-domain shown in Figure 2 has the characteristic of high-performance, low jitter, is not subject to the influence that technology, voltage and temperature (PVT) change.

On the phase-locked loop circuit and the basis of transfer function thereof based on time-domain shown in Figure 2, can adopt different digital circuits to realize.Be further analyzed and described below in conjunction with accompanying drawing and concrete circuit specific implementation phase-locked loop circuit shown in Figure 2.Please refer to Fig. 3, the phase-locked loop circuit of present embodiment comprises: free ring shakes 1, time-to-digit converter 2, logical block 3, adder 4, divider 5, digital loop filters 6 and digital controlled oscillator 7, wherein, the function of the time detector P1 of Fig. 2 realizes by time-to-digit converter 2, logical block 3 and adder 4.

Logical block 3 is used for generating first signal according to the synthetic clock signal of reference clock signal and digital controlled oscillator 7 feedbacks; , as the cycle count maximum periodicity of described synthetic clock signal is counted with the divider ratio N that obtained; At the effective edge of the reference clock signal that is obtained along calculating the peaked residue no count of the described relatively cycle count of the current number of count cycle value, and according to the three digital signal of digital control signal output representative residue no count corresponding time of value of representative cycle time of digital loop filters 6 outputs;

Described time-to-digit converter 2 is used under 1 multi-phase clock signal that provides is provided free ring respectively the instantaneous value of first signal of described logical block 3 outputs is formed discrete signal, as discrete signal represent respectively described first signal to effective edge along upset or from effective edge along when upset, with the distance between described two discrete signals with the 4th digital signal to described adder 4 outputs;

Described adder 4 is used for the 4th digital signal of the three digital signal of described logical block 3 outputs and 2 outputs of described time-to-digit converter is carried out add operation, exports first digital signal;

Described divider 5 is used for carrying out division arithmetic according to the add operation result that divider ratio N exports described adder 4, exports second digital signal;

Described digital loop filters 6 is used for second digital signal of divider 5 outputs is added up, and on behalf of the digital control signal of described cycle time, output be transferred to described digital controlled oscillator 7, and feeds back to described logical block 3;

Described digital controlled oscillator 7 is used for selecting phase clock signal and corresponding effective edge edge according to the digital control signal that is obtained from free ring 1 multi-phase clock signal that provides that shakes, to export synthetic clock signal and to feed back to described logical block 3.

With reference to shown in Figure 3, the function of described logical block 3 comprises two aspects: 1) described logical block 3 the reference clock signal that receives reach effective edge along the time, what begin to export first signal effectively begins the edge, and after this, the synthetic clock signal of described digital controlled oscillator 7 outputs that receive reach effective edge along the time, export effective end edge of first signal, thereby finish the output of first signal.For example, with reference to shown in Figure 4, before reference clock signal arrives, the synthetic clock signal that described logical block 3 is received is jumped the edge through a plurality of going up, received reference clock signal reach jump along the time, described logical block 3 is just exported going up of first signal and is jumped the edge, and the synthetic clock signal that receives reach jump on the next one along the time, just export the following jumping edge of first signal, thereby finish output first signal.

2) carrying out with divider ratio N according to the divider ratio N that is obtained to the efficient clock edge of the synthetic clock signal of the digital controlled oscillator that received 7 feedbacks is peaked counting.And the reference clock signal that receives reach effective edge along the time, the effective edge that calculates described maximum count value and the current synthetic clock signal of counting is poor along number, and with the form output of digital signal.For example, divider ratio N is 10, and then described logical block 3 just counts 1 when whenever receiving the efficient clock edge of a described synthetic clock signal, reach 10 up to counting, count down to 10 since 1 again then.Promptly carry out the cycle count of 1-10.Then the reference clock signal that receives reach effective edge along the time, calculate the value that also remains how many no counts, for example effective edge that described logical block 3 has been counted 8 synthetic clock signals along after receive the effective edge edge of reference clock signal, then also have 2 remaining no count values, then output valve is the digital signal of 2 cycle correspondences, digital control signal according to representative cycle time of described digital loop filters 6 feedbacks, if be 20 the cycle time of feedback, Shu Chu three digital signal is 40 so, and binary form is shown: 101000.

The effect of described in fact logical block 3 is exactly that the synthetic clock signal that is received is carried out bit comparison mutually with reference clock signal, the time difference on the synthetic clock signal of first signal representative of output and the effective edge edge of reference clock signal, described first signal reflected in fact described reference clock signal go up to jump going up of edge and next synthetic clock signal jump along between time difference, just the form of this time difference with digital signal can be showed by described time-to-digit converter 2.

Described time-to-digit converter 2 is based on free ring and shakes 1, and promptly described time-to-digit converter 2 shakes the significant level time that 1 signal with a plurality of phase clocks (multi-phase clock signal) that provides calculates first signal that described logical block 3 sends by free ring.Described free ring shakes and 1 provides a plurality of clock signals with out of phase to described time-to-digit converter 2, for example provide one group of phase clock signal with Fixed Time Interval to described time-to-digit converter 2, it is all identical with the delay time (phase delay) on the effective edge edge of adjacent phase clock signal to be each phase clock signal, for example second phase clock signal postpones 50ps than first phase clock signal, and the 3rd phase clock signal postpones 50ps by that analogy than second phase clock signal.Described time-to-digit converter 2 described free ring shake 1 each phase clock signal that provides on jump along described first signal of sampling.

Structure below by the time-to-digit converter of a specific embodiment comes the function of described time-to-digit converter 2 is described further, and with reference to shown in Figure 5, described time-to-digit converter comprises:

At least four trigger 21a, 21b, 21c, 21d, be used for phase clock signal in correspondence reach effective edge along the time, the instantaneous value of first signal that obtains is exported as discrete signal, and the corresponding effective edge of the phase clock signal of wherein said each trigger correspondence is along postponing successively;

At least two commencing signal unit 22,22 ', be used for continuous three discrete signals that obtained represent first signal to effective edge along when upset, pairing phase clock signal reach effective edge along the time export effective commencing signal, the corresponding effective edge of the phase clock signal of described continuous three discrete signal correspondences is along delay successively, and middle discrete signal is corresponding with described commencing signal unit;

At least two pulse units 23,23 ', be used at the discrete signal in the centre of continuous three discrete signals that obtained double when the same effective value, pairing phase clock signal reach effective edge along the time output pulse signal, the corresponding effective edge of the phase clock signal of described continuous three discrete signal correspondences is along postponing successively;

At least two end signal unit 24,24 ', be used for when continuous three discrete signals that obtained are represented first signal from effective edge along upset, pairing phase clock signal reach effective edge along the time export effective end signal, the corresponding effective edge of the phase clock signal of described continuous three discrete signal correspondences is along delay successively, and middle discrete signal is corresponding with described end signal unit;

Counting unit 25 is used for the pulse count signal to being obtained, and obtains an output signal high position;

First coding unit 26 is used for the commencing signal element address that obtains exporting described effective commencing signal according to the effective commencing signal that is obtained;

Second coding unit 27 is used for the end signal element address that obtains exporting described effective end signal according to the effective end signal that is obtained;

Subtrator 28 is used to calculate the commencing signal element address of the effective commencing signal of described output and export the distance of the end signal element address of effective end signal, obtains the output signal low level.

As mentioned above, described time-to-digit converter forms discrete signal by trigger obtains first signal under phase clock signal instantaneous value.If a plurality of triggers are arranged, and control all different words of phase place of the phase clock signal of each trigger, the instantaneous value of first signal that so described a plurality of triggers receive under each self-corresponding phase clock signal is just different, thereby the discrete signal of output also is different.Continue with reference to shown in Figure 5, the shake number of 1 phase clock signal that provides of the quantity of described trigger and described free ring is corresponding.For example, described free ring shakes provides 32 phase clock signals, and then the quantity of described trigger also is 32, and described trigger is the rising edge d type flip flop, described d type flip flop is at the rising edge of the phase clock signal of correspondence, and the instantaneous value of first signal that output is obtained at this moment forms discrete signal.Below in order to narrate unified and convenience, do following the setting: the quantity of trigger is M, M=1,2,3 ..32, the 1st to corresponding successively from left to right first phase clock signal of M trigger, second phase clock signal, M phase clock of the 3rd phase clock signal.For example, when first phase clock signal rising edge, first signal instantaneous value at this moment is a low level, and then the discrete signal of first trigger output is " 0 "; And because the rising edge of second phase clock signal has delay with respect to the rising edge of first phase clock signal, when the rising edge of second phase clock signal, the instantaneous value of first signal may overturn to high level, and then the discrete signal of second trigger output is exactly " 1 ".

The quantity of described pulse unit is identical with the quantity of described trigger, also is 32.Suppose that current pulse unit is a M pulse unit, three inputs of M pulse unit are the output of M trigger accordingly, the output of M-1 trigger (M trigger left side adjacent flip-flops), the output of M+1 trigger (M trigger the right adjacent flip-flops).0 and the phase clock signal of M-1, M and M+1 pulse unit correspondence also is respectively M-1 phase clock signal, a M phase clock signal and M+1 phase clock signal.

With reference to shown in Figure 6, described pulse unit comprises: be used for the not gate 230 with the discrete signal negate of M-1 trigger output, being used for will be through the discrete signal of negate, the discrete signal of M trigger output, the discrete signal of M+1 trigger output carry out with computing with door 232, the T end links to each other with described output with door 232, the T trigger 233 of clock end CLKB input phase clock signal, selecting side s links to each other with the output of described T trigger 233, according to the output of T trigger 233 selector 235 with the output of the signal on the first input end in1 or the second input in2.Described first input end in1 connects M phase clock signal, and the second input in2 connects constant 0 unit 234.Described pulse unit also comprise be used for to T trigger 233 carry out clearly 0 so that T trigger 233 become initial condition or door 231, described or door 231 connects the output of M-1 trigger and the output of M trigger, when M-1 and M trigger are output as " 0 ", to described T trigger 233 clear 0.

For example, when the signal of M-1 trigger, a M trigger and M+1 trigger output was 011, the output discrete signal " 0 " of M-1 trigger became " 1 " after not gate 230 negates.The output signal " 1 " of output signal of M trigger " 1 " and M+1 trigger and through the signal of M-1 trigger after the negate through with door 232 with computing after to the T end output " 1 " of T trigger 233.Described T trigger 233 is a trailing edge T trigger, and by the principle of trailing edge T trigger, when T was 1, at the trailing edge of clock, the T trigger can and be exported the initial condition upset, and T is 0 o'clock, and at the trailing edge of clock, the output of T trigger remains unchanged.The initial condition of described T trigger is traditionally arranged to be " 0 ".Therefore, when with door 232 during to the T of T trigger 233 end output " 1 ", at the trailing edge of M phase clock signal, T trigger 233 is with the initial condition upset and export " 1 ".And the selecting side s of selector 235 selects the signal output of first input end in1 when s is 1, selects the signal output of the second input in2 when s is 0.Because T trigger 233 is output as " 1 ", the selecting side s that connects the selector 235 of T trigger 233 outputs also is " 1 ".Therefore, when T trigger 233 exports 1 at M phase clock trailing edge, selector 235 is selected M phase clock signal output on the first input end in1, because at this moment M phase clock signal also is in trailing edge " 0 ", so the output signal of selector 235 temporarily still is " 0 ".And when M phase clock signal rising edge arrived, selector 235 will be exported the pulse signal " 1 " of a high level.When the next trailing edge of M phase clock signal arrives, if M-1, the output of M trigger still is high level, then because the T of T trigger 233 end is " 0 ", the output of T trigger 233 remains unchanged, therefore selector 235 is still selected M phase clock signal output, and then when the rising edge of M phase clock signal arrived, selector 235 continued the pulse signal of output high level.Up to M-1, M trigger while during output low level, just stop output pulse signal.If M trigger exported m high level continuously like this, then pulse unit can be exported the pulse signal of m high level.

According to above-mentioned description, have only when M-1, M and M+1 trigger are output as 011, T trigger 233 just can be exported high level, and selector 235 just has the pulse signal output of high level, and the output of other pulse unit all is low level at this moment.

Described commencing signal unit and described pulse unit are supporting, quantity also is 32, suppose that current commencing signal unit is M commencing signal unit, three inputs of M commencing signal unit are the output of M trigger accordingly, the output of M-1 trigger (M trigger left side adjacent flip-flops), the output of M+1 trigger (M trigger the right adjacent flip-flops).Wherein, M-1 trigger of the 1st commencing signal unit correspondence is last 1 trigger, and M+1 trigger of last 1 commencing signal unit correspondence is the 1st trigger.And M-1 is individual, M is individual and phase clock signal M+1 commencing signal unit correspondence also is respectively M-1 phase clock signal, a M phase clock signal and M+1 phase clock signal.

With reference to shown in Figure 7, the commencing signal unit comprises: be used for the not gate 236 with the discrete signal negate of M-1 trigger output, be used for carrying out through the discrete signal of the discrete signal of the signal of negate, a M trigger output, a M+1 trigger output with computing with door 237, T hold link to each other with described output with door 237, the T trigger 238 of clock end CLKB input phase clock signal.For example, when the output signal of described three triggers was 011, the output discrete signal " 0 " of M-1 trigger became " 1 " after not gate 236 negates.The output discrete signal " 1 " of M trigger and the output discrete signal " 1 " of M+1 trigger and through the signal of M-1 trigger after the negate through with door 237 with computing after to the T end output " 1 " of T trigger 238.Described T trigger is a trailing edge T trigger, and by the principle of trailing edge T trigger, when T was 1, at the trailing edge of clock, the T trigger can and be exported the initial condition upset, and T is 0 o'clock, and at the trailing edge of clock, the output of T trigger remains unchanged.The initial condition of described T trigger is traditionally arranged to be " 0 ", the clear 0 clear 0 end CLR control (before time detector work next time, being controlled the time detector zero clearing by clear 0 end CLR) by the clear 0 signal CLR of connection of described T trigger.Therefore, when with door 237 during to the T of T trigger 238 end output " 1 ", at the trailing edge of M phase clock signal, T trigger 238 is with the initial condition upset and export " 1 ", promptly exports effective commencing signal.

Described end signal unit and described commencing signal unit are supporting, quantity also is 32, suppose that current end signal unit is M end signal unit, three inputs of M end signal unit are the output of M trigger accordingly, the output of M-1 trigger (M trigger left side adjacent flip-flops), the output of M+1 trigger (M trigger the right adjacent flip-flops).Wherein, M-1 trigger of the 1st end signal unit correspondence is last 1 trigger, and M+1 trigger of last 1 end signal unit correspondence is the 1st trigger.And M-1 is individual, M is individual and phase clock signal M+1 end signal unit correspondence also is respectively M-1 phase clock signal, a M phase clock signal and M+1 phase clock signal.

With reference to shown in Figure 8, the end signal unit comprises: be used for the not gate 239 with the discrete signal negate of M-1 trigger output, be used for carrying out through the signal of the signal of the signal of negate, a M trigger output, a M+1 trigger output NOR gate 239 of NOR-operation ', T hold with described NOR gate 239 ' output link to each other, the T trigger 239 of clock end CLKB input phase clock signal ".For example, when the output signal of described three triggers was 100, the output signal of N-1 trigger " 1 " became " 0 " after not gate 239 negates.The output signal " 0 " of output signal of M-1 trigger " 0 " and M+1 trigger and through the signal of M-1 trigger after the negate through NOR gate 239 ' NOR-operation after to T trigger 239 " T end output " 1 ".Described T trigger is a trailing edge T trigger, and by the principle of trailing edge T trigger, when T was 1, at the trailing edge of clock, the T trigger can and be exported the initial condition upset, and T is 0 o'clock, and at the trailing edge of clock, the output of T trigger remains unchanged.The initial condition of described T trigger is traditionally arranged to be " 0 ", the clear 0 clear 0 end CLR control (before time detector work next time, being controlled the time detector zero clearing by clear 0 end CLR) by the clear 0 signal CLR of connection of described T trigger.Therefore when T end output " 1 " ", at the trailing edge of M phase clock signal, T trigger 239 " promptly exports effective end signal with the initial condition upset and export " 1 ", when NOR gate 239 ' to T trigger 239.

When handling for first signal with the level pulse that grows tall, for same trigger, may reach at the phase clock signal of correspondence jump along the time, the instantaneous value of first signal that is received is " 1 " once more, and at this time just needing counting unit to write down is which time obtains " 1 ".The function of setting counting unit is output " 1 " when obtaining for the second time the high level pulse signal of pulse unit output, and promptly the count results of counting unit is that the high level pulse number of signals that pulse unit is exported subtracts 1.Described counting unit comprises: that the pulse signal of paired pulses unit output carries out exclusive disjunction or door, the counter that the high level output of described or door is counted and count results subtracted 1 and the subtracter of output.The output of described counter constitutes the output signal high position of described time-to-digit converter, and representative should add the product that blanking time between twice output of same trigger " 1 " and same trigger are exported the number of times of " 1 " once more when the result of calculation of high level pulse of described first signal of output.For example, counting unit output " 1 ", the number of times of then representing same trigger to export " 1 " once more is 1, the result of calculation of the high level pulse of then described first signal just should add the blanking time between 1 times twice output of same trigger " 1 ".32 reference clock signals that have phase delay successively are provided in this example, the blanking time between twice output of then described same trigger " 1 ", promptly refer to the upward jumping edge of the 1st phase clock signal and going up the time of jumping between the edge of the 32nd phase clock.

By above analysis as can be known, the signal transient of the satisfied effective commencing signal of output or effective end signal condition all has only a kind of, and therefore described 32 commencing signal unit or end signal unit all have only a meeting output useful signal.Described first coding unit and second coding unit are exactly in order to know which commencing signal unit or end signal unit exported useful signal.Described first coding unit is identical with the structure of second coding unit.

Be example with first coding unit below, which commencing signal unit what described first coding unit 26 obtained by the output signal of 32 commencing signal unit being obtained is encoded to export effective commencing signal is, suppose that be 0～31 by from left to right order to the 1st to the 32nd commencing signal element number, then available 52 system numbers are represented the 1st to the 32nd commencing signal unit, and with the described numbering address of signal element to start with.If, need not extra coding, therefore only need choose 1xxxx, x1xxx, xx1xx, xxx1x, the output signal coding of the commencing signal unit that xxxx1 representative numbering is corresponding because the 1st commencing signal unit output commencing signal is exactly 00000.

Details are as follows to choose the mode of output signal of described commencing signal unit: suppose that 52 system numbers data bit from left to right is the 1st data bit to the 5 data bit, connect the output of the commencing signal unit that is numbered 1xxxx with an encoder, 1xxxx is that the 1st data bit is 152 system numbers, promptly 10000～11111, Dai Biao commencing signal unit is numbered 16～31 respectively; Connect the output of the commencing signal unit that is numbered x1xxx with encoder, x1xxx is that the 2nd data bit is 152 system numbers, promptly 01000～01111,11000～11111, and Dai Biao commencing signal unit is numbered 8～15,24～31 respectively; Connect the output of the commencing signal unit that is numbered xx1xx with an encoder, xx1xx is that the 3rd data bit is 152 system numbers, promptly 00100～00111,01100～01111,10100～10111,11100～11111, Dai Biao commencing signal unit is numbered 4～7,12～15,20～23,28～31 respectively; Connect the output of the commencing signal unit that is numbered xxx1x with an encoder, xxx1x is that the 4th data bit is 152 system numbers, promptly 00010～00011,00110～00111,01010～01011,01110～01111,10010～10011,10110～10111,11010～11011,11110～11111, Dai Biao commencing signal unit is numbered 2～3,6～7,10～11,14～15,18～19,22～23,26～27,30～31 respectively; Connect the output of the commencing signal unit that is numbered xxxx1 with an encoder, xxxx1 is that the 5th data bit is 152 system numbers, promptly 00001,00011,00101,00111,01001,01011,01101,01111,10001,10011,10101,10111,11001,11011,11101,11111, Dai Biao commencing signal unit is numbered 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31 respectively.

Mode by the above-mentioned output signal of choosing the commencing signal unit as can be known, the commencing signal that any one output high level is arranged in described 32 commencing signal unit, connect the commencing signal that the encoder of described commencing signal unit output can both pass through to be obtained and encode, thereby which commencing signal unit what obtain exporting commencing signal is.Wherein, the simplest coded system is exactly that the output signal of 16 commencing signal unit that each encoder is obtained is carried out exclusive disjunction, as long as any one output high level commencing signal is arranged in 16 commencing signal unit that described encoder connects, the output of described encoder is high level just.With 1xxxx, x1xxx, xx1xx, xxx1x, the output sequence arrangement of xxxx1 corresponding codes device becomes 52 system numbers, just can represent to export the numbering of the commencing signal unit of high level commencing signal.

Because 16 exclusive disjunction is directly used or door realizes that delay can be very long, the encoder in this example uses NOR gate and NAND gate to realize the exclusive disjunction of 16 signals.With reference to shown in Figure 9, described encoder comprises the level Four circuit, first order circuit is used to receive the commencing signal of commencing signal unit output, comprise 2 input NOR gate 41～48, the input of described 8 NOR gate links to each other with the corresponding output that connects 16 commencing signal unit of described encoder respectively, for example, and NOR gate 41 received signal D1, D2, NOR gate 42 receives output signal D3, D4, by that analogy; Second level circuit comprises 2 input nand gates 410～413, described NAND gate 410～413 is respectively applied for the output of the NOR gate 41～48 that receives the first order, for example, NAND gate 410 receives the output of NOR gate 41 and NOR gate 42, NAND gate 411 receives the output of NOR gate 43 and NOR gate 44, by that analogy; Tertiary circuit comprises 2 input NOR gate 414～415, described NOR gate 414～415 is respectively applied for the output that receives partial NAND gate 410～413, for example, NOR gate 414 receives the output of NAND gate 410 and NAND gate 411, and NOR gate 415 receives the output of NAND gate 412 and NAND gate 413; Fourth stage circuit comprises 2 input nand gates 416, and described NAND gate 416 is used to receive the output of NOR gate 414 and NOR gate 415.

Described encoder is exemplified below: what effective commencing signal was exported in supposition is to be numbered 8 commencing signal unit.Aforesaid, the encoder that links to each other with the output that is numbered 8 commencing signal unit is the encoder that above-mentioned being connected is numbered the commencing signal unit of 1xxxx, continue with reference to shown in Figure 9, suppose that the output signal that is numbered 8 commencing signal unit inputs to the D1 end of the NOR gate 41 of described encoder, then the signal of D1 end is a high level, and other inputs D2～D16 of described encoder is because the output of the commencing signal unit that connects all is low level, then have only NOR gate 41 to be output as 0 in the first order NOR gate, the output of other NOR gate all is 1, have only NAND gate 410 to be output as 1 in the NAND gate of the second level, the output of other NAND gate all is 0, third level NOR gate 414 is output as 0, NOR gate 415 is output as 1, and fourth stage NAND gate 416 is output as 1.And other connections are numbered 1xxxx, xx1xx, xxx1x, the encoder of the commencing signal unit of xxxx1 do not link to each other with the output that is numbered 8 commencing signal unit, therefore the output of described four encoders all is 0, then with 1xxxx, x1xxx, xx1xx, xxx1x, the output sequence arrangement of xxxx1 corresponding codes unit becomes 52 system numbers, is exactly 01000, promptly exports the commencing signal element address (01000=8) of effective commencing signal.

Described subtrator 28 is used for the commencing signal element address of the end signal element address of second coding unit, 27 outputs and 26 outputs of first coding unit is subtracted each other, and obtains to sample and jumps the trigger on edge on first signal and sample the distance of jumping the trigger on edge under first signal.The output of described subtrator 28 also is 52 system numbers, with the output of the described subtrator 28 output signal low level as described time-to-digit converter 2.

If the time of the high level pulse of described first signal less than going up of the 1st phase clock signal jump going up of edge and the 32nd phase clock signal jump along between time, the high position of then described time-to-digit converter 2 is output as 00000, and low level output is exactly the output of described subtrator 28.And if the time of the high level pulse of described first signal greater than going up of the 1st phase clock signal jump going up of edge and the 32nd phase clock signal jump along between time, then the high position of described time-to-digit converter is output as the output of described counting unit 25, and low level output is exactly the output of described subtrator 28.For example, receiving the distance of jumping the trigger on edge on first signal and receiving the trigger on jumping edge under first signal is 5, and described counting unit is output as 2, and the output high position of then described time-to-digit converter 2 is 00010, low level is 00101, and complete output is exactly 0001000101.It is exactly 2 * 32+5=69 that described 10 2 system output signals are converted to 10 system numbers, the time delay that goes up the jumping edge by the adjacent phase clock signal of supposing before is 50ps, going up the following time of jumping between the edge of jumping edge and measured signal of so described first signal, promptly the high level pulse width of first signal is 69 * 50=3450ps.Therefore, the value of the digital signal of described time data transducer 2 last outputs is exactly the multiple of going up the time delay of jumping the edge of described adjacent phase clock signal in fact.

With reference to shown in Figure 10, second kind of embodiment of described time-to-digit converter comprises: at least four trigger 100a, 100b, 100c, 100d; Assembled unit 200,200 '; Counting unit 500; First coding unit 600; Second coding unit 700 and subtrator 800, described trigger 100a, 100b, 100c, 100d, counting unit 500, first coding unit 600, trigger 21a, 21b, 21c, the 21d of second coding unit 700 and subtrator 800 and earlier figures 5, counting unit 25, the first coding units 26, second coding unit 27 and subtrator 28 are identical, have just described no longer one by one here.And the function of described assembled unit 200 is aforesaid pulse unit 23, the function summation of commencing signal unit 22 and end signal unit 24, be described assembled unit 200 be used for continuous three discrete signals that obtained represent first signal to effective edge along when upset, pairing phase clock signal reach effective edge along the time export effective commencing signal; Be used at the discrete signal of the trigger of correspondence output double during for same effective value, pairing phase clock signal reach effective edge along the time output pulse signal; Be used for when continuous three discrete signals that obtained are represented first signal from effective edge along upset, pairing phase clock signal reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively.Described assembled unit 200 ' function and described assembled unit 200 identical.

In conjunction with Fig. 6, Fig. 7, Fig. 8 and shown in Figure 11, the circuit of described assembled unit is exactly with pulse unit in fact, the parts that have identical function in commencing signal unit and the end signal unit are merged into common component, for example with the not gate in the pulse unit 230, not gate 236 in the commencing signal unit and the not gate 239 in the end signal unit merge into shared not gate 10 ', with in the pulse unit with door 232 and commencing signal unit in door 237 merge into shared and door 12 ', miscellaneous part is all identical with parts in the corresponding unit, for example or door 11 ' with pulse unit in or 231 identical, T trigger 13 ' identical with T trigger 233 in the pulse unit, constant 0 unit 14 ' identical with constant 0 unit 234 in the pulse unit, selector 15 ' identical with selector 235 in the pulse unit, T trigger 16 ' identical with T trigger 238 in the commencing signal unit, NOR gate 17 ' with the end signal unit in NOR gate 239 ' identical, T trigger 18 ' " identical with T trigger 239 in the end signal unit.Describe the description that please refer to paired pulses unit, commencing signal unit and end signal unit in above-mentioned first kind of execution mode about each functions of components wherein, just repeated no more here.

Can see from above-mentioned description time-to-digit converter, the numerical value of the digital signal representative of described time-to-digit converter 2 outputs is exactly the shake multiple of blanking time of 1 multi-phase clock signal that provides of described free ring in fact, for example output signal is 00010,00101, i.e. 2 * 32+5=69, it is exactly the multiple of the blanking time of described multi-phase clock signal, then if choosing the above-mentioned time interval is 50ps, then the pulsewidth of first signal of output signal representative is exactly 69*50ps=3450ps.Therefore, the 4th digital signal of the output of described time-to-digit converter 2 just can be thought based on the shake output signal of blanking time of the multiphase clock that provided of free ring.

Continue with reference to shown in Figure 4, described time-to-digit converter 2 is according to first signal of described logical block 3 transmission, in free ring the 4th digital signal that multi-phase clock signal down-sampling first signal that provides obtained of shaking is exactly A, and the three digital signal of the output of logical block 3 is exactly B.Through the add operation of adder 4, the so actual first synthetic digital signal represents to be exactly A+B.

Continue with reference to shown in Figure 3, after adder 4 obtains first digital signal, divider 5 can carry out division arithmetic to first digital signal of adder 4 outputs according to the divider ratio N that is received, and obtains second digital signal, that is to say that second digital signal equals first digital signal divided by N.

Described digital loop filters 6 then is the processing that adds up for second digital signal that divider 5 is exported, and the high fdrequency component in filtering second digital signal, obtains digital control signal.

Please refer to Figure 12, described digital loop filters 6 comprises: multiplication factor is that the first multiplier 6a, the multiplication factor of Control Parameter α is the second multiplier 6b of Control Parameter ρ, and the 3rd adder 6c, the 4th adder 6d and transfer function are z ^-1Delay unit 6e (for example, d type flip flop DFF).

Second digital signal obtains the input of the 3rd adder 6c through the first multiplier 6a, second digital signal obtains the input of the 4th adder 6d through the second multiplier 6b, the 4th adder 6d is output as another input of the 3rd adder 6c, the output of the 4th adder 6d feeds back to the 4th adder 6d (promptly obtaining another input of the 4th adder 6d) behind delay unit 6e, the 3rd adder 6c is output as the digital control signal of digital loop filters 6 outputs.

Continue with reference to shown in Figure 3,7 digital control signals according to digital loop filters 6 outputs of described digital controlled oscillator select corresponding phase clock signal and corresponding clock to jump along output from 1 multi-phase clock signal that provides is provided described free ring.With reference to shown in Figure 13, described digital controlled oscillator comprises: phase clock selected cell (sign), the first lap selected cell 75 and the second circle selected cell 75 ', the 5th latch 76 and the 6th latch 76 ', the 3rd clock selecting unit 77, output signal unit 78, inverter 79 and inverter 79 '.Described phase clock selected cell is used for the digital control signal that is received added up and selects the address, and selects corresponding phase clock signal output from the multi-phase clock signal that is received, and comprising:

First adder 71 and second adder 71 ', be respectively applied for digital control signal＜31:0 to being received 〉,＜32:28〉adding up obtains corresponding selection address;

First latch 72, second latch 73 are used for the selection address sampling of first adder 71 outputs is deposited, and sampling clock is the inversion signal CLK2 of the synthetic clock signal clk 1 of output;

The 3rd latch 72 ', quad latch 73 ', be used for the sampling of the selection address of second adder 71 ' output is deposited, sampling clock is respectively the inversion signal CLK2 and the synthetic clock signal clk 1 of the synthetic clock signal clk 1 of output;

The first clock selecting unit 74 and second clock selected cell 74 ', be respectively applied for selection address, from the phase clock signal＜31:0 that is received according to second latch 73 and quad latch 73 ' output〉select the output of respective phase clock signal.

The described first lap selected cell 75 and the second circle selected cell 75 ', be respectively applied for the effective impulse of the phase clock signal of the first clock selecting unit 74 and second clock selected cell 74 ' output is counted, with count results and digital control signal＜35:33 of being received〉relatively, and according to comparative result and digital control signal＜32 that received produce the selection signal that is used to select phase clock signal effective edge edge.

Described the 5th latch 76 and the 6th latch 76 ', be respectively applied for selection signal according to first lap selected cell 75 and second circle selected cell 75 ' output, at the corresponding effective edge of the phase clock signal of the very first time selected cell 74 that is received and the second selection of time unit 74 ' output along exporting described phase clock signal.

Described the 3rd clock selecting unit 77 is used for the phase clock signal according to 1 selection the 5th latch 76 of the synthetic clock signal clk on the selecting side or the 6th latch 76 ' output.

Described output signal unit 78 is used for when the phase clock signal of the 3rd clock selecting unit 77 outputs is effective the synthetic clock signal clk 1 of output.

Described inverter 79 is used for the synthetic clock signal phase negate of described output signal unit 78 output is obtained the inversion signal CLK2 of synthetic clock signal, and described inverter 79 ' be used for is with the synthetic clock signal negate of described output signal unit 78 outputs and feed back to the input of described output signal unit 78.

Digital control signal＜35:0〉by digital loop filters 6 outputs, wherein, digital control signal＜31:0〉as the input of first adder 71, digital control signal＜32:28 as second adder 71 ' input, digital control signal＜35:32〉as circle selected cell 75,75 ' input.

With reference to shown in Figure 14, a kind of embodiment of described first lap selected cell 75 comprises:

First counting unit 502 is used for the effective impulse of the phase clock signal that receives is counted, and count results is sent to first comparing unit 503, and wherein, count results is 0 when reset signal is effective;

First comparing unit 503, be used for the count results that first counting unit 502 is sent and the digital control signal that is received '＜35:32 relatively, to first selected cell, 504 outputs, first comparative result;

Second counting unit 502 ', be used for the effective impulse of the inversion signal of the phase clock signal that receives is counted, and with count results send to second comparing unit 503 ', wherein, count results is 0 when reset signal is effective;

Second comparing unit 503 ', be used for second counting unit 502 ' count results of transmission and the expansion control signal＜35:32 that is received relatively, to selected cell 504 outputs second comparative result;

Selected cell 504 is used for according to the digital control signal that is received＜32 〉, select the selection signal on phase clock signal effective edge edge to export as being used to first comparative result or second comparative result.

Described second circle selected cell 75 ' comprise equally first counting unit, first comparing unit, second counting unit, second comparing unit and the selected cell, the corresponding units of its structure and described first lap selected cell 75 is identical, the reset signal of different is described first lap selected cell 75 is synthetic clock signal clk 1, the described second circle selected cell 75 ' reset signal be the inversion signal CLK2 of synthetic clock signal clk 1, just repeated no more here.

With reference to shown in Figure 15, described first counting unit 502 comprises: first d type flip flop 505, second d type flip flop 506 and the 3d flip-flop 507.Set described d type flip flop when reset signal is low level to the d type flip flop zero clearing, the Q end output that is about to d type flip flop is changed to " 0 ", normally counts when reset signal is high level.Output D0, D1, the D2 of first d type flip flop 505, second d type flip flop 506 and 3d flip-flop 507 constitute count results, and wherein count results D2 is high-order, and D0 is a lowest order, and therefore output is D2, D1, D0.The principle of described d type flip flop is: when clock is high level, and Q end output D end signal, when clock was low level, Q end hold mode was constant.The initial condition hypothesis D end of d type flip flops at different levels is " 1 ".

Because when reset signal is low level, the Q end output of d type flip flop is by reset, the count results of described counting unit is exactly " 000 ", operation principle procedure declaration when therefore only reset signal being high level below is as follows: the supposition d type flip flop is the d type flip flop that rising edge triggers, when the 1st rising edge of the CLK of d type flip flop end signal arrives, d type flip flop 505 is by the initial condition upset, and promptly d type flip flop 505 is exported " 1 " at the 1st rising edge of CLK end signal by the Q end, and! Q end is " 0 ", the D end because with! The Q end links to each other, and also becomes " 0 ".When the 2nd rising edge of CLK end signal, the Q of d type flip flop 505 end will be exported " 0 ",! The Q end is " 1 ", and the D end also becomes " 1 ".When the 3rd rising edge of CLK signal, the Q of d type flip flop 505 end will be exported " 1 ",! The Q end is " 0 ", and the D end also becomes " 0 ".When the 4th rising edge of CLK signal, the Q of d type flip flop 505 end will be exported " 0 ",! The Q end is " 1 ", and the D end also becomes " 1 ".

The CLK termination of d type flip flop 506 is received d type flip flop 505! Q holds output, when d type flip flop 505! When the Q end was " 1 " for the first time, promptly at the 2nd rising edge of CLK end signal, d type flip flop 506 was exported " 1 " by the initial condition upset by the Q end, and! Q end is " 0 ", and the D end also becomes " 0 ", and when d type flip flop 505! The output of Q end is " 1 " for the second time, and promptly when the 4th rising edge of CLK end signal, the Q of d type flip flop 506 end will be exported " 0 ",! The Q end is " 1 ".

The CLK termination of d type flip flop 507 is received d type flip flop 506! Q holds output, when d type flip flop 506! When the Q end was " 1 ", promptly at the 4th rising edge of CLK end signal, d type flip flop 507 was exported " 1 " by the initial condition upset by the Q end, and! Q end is " 0 ", and the D end also becomes " 0 ", and when d type flip flop 506! The output of Q end is " 1 " once more, and promptly when the 12nd rising edge of CLK end signal, the Q of d type flip flop 506 end will be exported " 0 ",! The Q end is " 1 ".

According to foregoing description, at the 1st rising edge of CLK end signal, the count results D2 of counting unit, D1, D0 are " 001 ", the 2nd rising edge, and the count results of counting unit is " 010 ".

And the d type flip flop number of described counting unit is not limited to 3, can require to be configured according to required output signal frequency.

Described second counting unit 502 ' comprise equally: first d type flip flop, second d type flip flop and 3d flip-flop, the corresponding units of its structure and described first counting unit 502 is identical, has just repeated no more here.

With reference to shown in Figure 16, described first comparing unit 503 comprises: first XOR gate 510 and connect the not gate 510 of first XOR gate 510 ', second XOR gate 509 and connect the not gate 509 of second XOR gate 509 ', the 3rd XOR gate 508 and connect the not gate 508 of the 3rd XOR gate 508 ', and receive not gate 510 ', 509 ' and 508 ' output with door 511.

Described second comparing unit 503 ' internal structure and described first comparing unit 503 identical, just repeated no more here.Count results and digital control signal＜35:33 when first comparing unit 503 or second comparing unit 503 ' reception〉in full accord, then output " 1 ", otherwise just output " 0 ".

504 of described selected cells are according to the digital control signal that is received＜32〉select the output of corresponding comparing unit to select signal output as the edge, digital control signal＜32 for example〉be " 0 ", then select second comparing unit 503 ' output as the selection signal on effective edge edge, digital control signal＜32〉be " 1 ", then select the selection signal of the output of first comparing unit 503 as the effective edge edge.

With reference to shown in Figure 17, the another kind of embodiment of described first lap selected cell 75 comprises:

Combinatorial enumeration unit 502 "; be used for count obtain first count results and send to combination comparing unit 503 effective impulse of the phase clock signal that receives " is used for obtaining second count results and sending to combination comparing unit 503 counting with the effective impulse of the inversion signal of the phase clock signal that is received ";

Combination comparing unit 503 "; be used for first count results that will be received and the digital control signal＜35:33 that is received〉relatively; " output first comparative result to selected cell 504, be used for second count results that will be received and the digital control signal＜35:33 that is received〉relatively, to selected cell 504 " output second comparative result;

Selected cell 504 ", be used for according to the digital control signal that is received＜32, first comparative result or second comparative result are exported as the selection signal on phase clock effective edge edge.

Described combinatorial enumeration unit 502 " be above-mentioned first counting unit 502 and second counting unit 502 ' the function sum.Described combination comparing unit 503 " be above-mentioned first comparing unit 503 and second comparing unit 503 ' the function sum.Described selected cell 504 " function and above-mentioned selected cell 504 identical.Therefore, can specifying with reference to above-mentioned corresponding units.

Described second circle selected cell 75 ' comprise the equally combinatorial enumeration unit, combination comparing unit and selected cell, the corresponding units of its structure and described first lap selected cell 75 is identical, different just reset signal, just do not giving unnecessary details here.

Below in conjunction with Figure 13, Figure 14, Figure 15, Figure 16 above-mentioned circle selected cell is given an example so that explanation is clearer.

Suppose that digital controlled oscillator will choose multi-phase clock signal＜31:0〉the 16th phase clock signal and the 3rd of the 16th phase clock signal go up and jump along producing synthetic clock signal.Owing to do not jump the edge if do not select going up of phase clock signal, all jump along sampling from the 1st, the number of going up the jumping edge that therefore will increase is exactly 2, promptly 010, Dui Ying digital control signal＜35:33 then 〉=010, and digital control signal＜32 〉=0, suppose that the initial condition of clock signal clk 1 and CLK2 is respectively " 0 " and " 1 ".

Be initially 1 by CLK2, then at first the operation be second the circle selected cell 75 '.Set when selecting control signal be " 0 ", choose second comparing unit 503 ' comparative result output, then only need consideration second counting unit 502 ' with second comparing unit 503 ' the course of work get final product.Continuation is in conjunction with Figure 13, Figure 14 and shown in Figure 15, CLK2 as second counting unit 502 ' reset signal, this moment is because CLK2 is " 1 ", 502 ' not the zero clearing of described second counting unit, then in conjunction with above-mentioned description to counting unit, because second counting unit 502 ' be effective impulse counting to the signal opposite with phase clock signal, thereby be to jump down along triggering, jump the edge down for the 1st of phase clock signal in input, described second counting unit 502 ' count results be " 001 ".Described second comparing unit 503 ' with digital control signal＜35:33〉press bit comparison with " 001 ", obvious second comparing unit 503 ' comparative result be " 0 ", then the 6th latch 76 ' (D-latch) do not overturn, output signal unit 78 (d type flip flop) does not obtain triggering signal yet, so the state of CLK2 is constant.

Continuation is according to foregoing description, jump the edge down for the 2nd at phase clock signal, second counting unit 502 ' count results be " 010 ", described second comparing unit 503 ' with digital control signal＜35:33〉press bit comparison with " 010 ", obviously comparative result is " 1 ", the high level along the output phase clock signal is jumped in then the 6th latch 76 ' (D-latch) upset on the 3rd of phase clock signal.And the 3rd selected cell 77 CLK1 select when " 0 " the 6th latch 76 ' output, then the 3rd selected cell 77 is when the 6th latch 76 ' output high level, high level is transferred to output signal unit 78, output signal unit 78 is after the triggering signal that obtains high level, just the D end value is exported from the Q end, since the D end signal by CLK1 via inverter 79 ' provide, the value of therefore initial D end is " 1 ", then the value of the CLK1 of Q end just becomes " 1 " at this moment, and promptly CLK1 jumps on the 3rd of phase clock signal along becoming " 1 " by " 0 ".And CLK2 is opposite with the CLK1 phase place, then becomes " 0 " by " 1 ".The then second circle selected cell, 75 ' zero clearing, the 6th latch 76 ' do not overturn.

The ensuing clock cycle, operation be exactly by the first lap selected cell 75 of CLK1 as reset signal.Described first lap selected cell 75 also will according to above-mentioned second circle selected cell 75 ' identical operating process, export the selection signal on the effective edge edge of corresponding selection phase clock signal, therefore the operating process of first lap selected cell 75 can just repeat no more with reference to above-mentioned explanation herein.

Can get according to the above description, variation by reset signal CLK1 and CLK2 state, the first lap selected cell 75 and the second circle selected cell 75 ' with regard to alternate run just can alternately provide the selection signal on jumping edge on each demand of selected phase clock to output signal unit 78.

The function of described digital controlled oscillator 7 can be summarized with following formula in fact:

T _Cycle=CN * Δ, wherein T _CycleBe the cycle of the synthetic clock signal of described digital controlled oscillator output, CN is the digital control signal of the described digital controlled oscillator 7 of input, the time interval of each adjacent phase clock signal that Δ provides for described free ring shakes.By above-mentioned according to digital control signal＜35:33 select the 3rd to go up the example of jumping along producing output signal, the cycle of the synthetic clock signal of final output is exactly 2 times clock interval in fact.Therefore, the synthetic clock signal of described digital controlled oscillator output also can be thought based on the shake output signal of blanking time of the multiphase clock that provided of free ring.And, can obtain by described formula, the cycle of the synthetic clock signal of described digital controlled oscillator also is a linear change, therefore need not the extra functional unit of regulating the digital controlled oscillator gain that increases again, power consumption also reduces.

The multi-phase clock signal that time-to-digit converter in the phase-locked loop circuit shakes and provides according to free ring, the instantaneous value that obtains received signal under each phase clock signal respectively forms discrete signal, and obtains the significant level time of described signal and be converted to digital signal by the distance of calculating discrete signal.And the digital controlled oscillator of described phase-locked loop circuit also is to choose the next synthetic output clock of phase clock and corresponding effective edge edge according to digital control signal from the multiphase clock that provides is provided free ring.

By illustrating about time-to-digit converter and digital controlled oscillator, described time-to-digit converter and digital controlled oscillator can be thought based on the shake output signal of blanking time of the multi-phase clock signal that provided of free ring, so its gain is also more stable.For whole phase-locked loop circuit, just need not again the extra functional unit of regulating gain that increases.

In sum, in the phase-locked loop circuit of embodiment of the present invention, time detector deducts the periodic accumulation value of reference clock signal the periodic accumulation value (promptly the periodic accumulation of synthetic clock signal is on duty with divider ratio) of feedback clock signal on time-domain, the output signal that obtains is the digital signal that is used for express time; And make up the transfer function of whole loop by the transfer function of setting digital loop filters and digital controlled oscillator, therefore, above-mentioned phase-locked loop circuit is based on the framework that time-domain is analyzed, only need set the Control Parameter of digital loop filters, just can be subjected to the loop damping factor of divider ratio, incoming frequency, output frequency and process variations influence, and the natural resonance frequency that is directly proportional with incoming frequency.Based on the all-digital phase-locked loop circuit of above-mentioned architecture design need not extra increase with time signal change into phase signal multiplier, be used for the direct adjustment unit of slight error adjustment and be used to adjust the digital controlled oscillator gain adjusting unit of the linearity of digital controlled oscillator, thereby circuit structure is simple, power consumption is also less, area is less, and is a more stable system.

Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims (12)

1. a phase-locked loop circuit is characterized in that, comprising:

Time detector, be used to export first digital signal, described first digital signal is used to represent periodic accumulation value poor of the periodic accumulation value of reference clock signal and feedback clock signal on time-domain, the periodic accumulation value of described feedback clock signal is expressed as the periodic accumulation value of synthetic clock signal and the product of divider ratio on time-domain;

Divider, first digital signal that is used for described time detector is exported is exported second digital signal divided by described divider ratio;

Digital loop filters, second digital signal of the described divider output that is used to add up, the output digital control signal, the transfer function of described digital loop filters is

α, ρ are Control Parameter;

Digital controlled oscillator is used for producing synthetic clock signal according to the digital control signal of described digital loop filters output, and the transfer function of described digital controlled oscillator is

2. phase-locked loop circuit as claimed in claim 1, it is characterized in that, comprise that also free ring shakes, be used to provide multi-phase clock signal, the cycle of described synthetic clock signal equals the product in the time interval on the effective edge edge of phase clock signal adjacent in digital control signal and the multi-phase clock signal.

3. phase-locked loop circuit as claimed in claim 2 is characterized in that, described time detector comprises:

Logical block is used for generating first signal according to the synthetic clock signal of reference clock signal and described digital controlled oscillator feedback; , as the cycle count maximum periodicity of described synthetic clock signal is counted with the divider ratio that obtained; At the effective edge of reference clock signal along calculating the peaked residue no count of the described relatively cycle count of the current number of count cycle value, the three digital signal of output representative residue no count corresponding time of value, described three digital signal equal the digital control signal of described digital loop filters output and the product of residue no count value;

Time-to-digit converter is used under the multi-phase clock signal that provides is provided described free ring respectively the instantaneous value of first signal of described logical block output is formed discrete signal; As discrete signal represent respectively described first signal to effective edge along upset or from effective edge along when upset, with described first signal of expression to effective edge along the discrete signal of upset and represent described first signal from effective edge the distance between the discrete signal along upset export with the 4th digital signal;

Adder is used for the three digital signal of described logical block output and the 4th digital signal of described time-to-digit converter output are carried out add operation, exports first digital signal.

4. phase-locked loop circuit as claimed in claim 3 is characterized in that, described time-to-digit converter comprises:

At least four triggers, be used for phase clock signal in correspondence reach effective edge along the time, the instantaneous value of first signal that output is obtained forms discrete signal, the corresponding effective edge of the phase clock of wherein said at least four trigger correspondences is along postponing successively;

At least two commencing signal unit, be used for continuous three discrete signals that obtained represent first signal to effective edge along when upset, pairing phase clock signal reach effective edge along the time export effective commencing signal, the corresponding effective edge of the phase clock of described continuous three discrete signal correspondences is along delay successively, and middle discrete signal is corresponding with described commencing signal unit;

At least two pulse units, be used at the discrete signal in the centre of continuous three discrete signals that obtained double when the same effective value, pairing phase clock signal reach effective edge along the time output pulse signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;

At least two end signal unit, be used for when continuous three discrete signals that obtained are represented first signal from effective edge along upset, pairing phase clock signal reach effective edge along the time export effective end signal, the corresponding effective edge of the phase clock of described continuous three discrete signal correspondences is along delay successively, and middle discrete signal is corresponding with described end signal unit;

Counting unit is used for the pulse count signal to being obtained, and obtains an output signal high position;

First coding unit is used for the commencing signal element address that obtains exporting described effective commencing signal according to the effective commencing signal that is obtained;

Second coding unit is used for the end signal element address that obtains exporting described effective end signal according to the effective end signal that is obtained;

Subtrator is used to calculate the commencing signal element address of the effective commencing signal of described output and export the distance of the end signal element address of effective end signal, obtains the output signal low level.

5. phase-locked loop circuit as claimed in claim 3 is characterized in that, described time-to-digit converter comprises:

At least four triggers, be used for phase clock signal in correspondence reach effective edge along the time, the instantaneous value of first signal that output is obtained forms discrete signal, the corresponding effective edge of the phase clock of wherein said at least four trigger correspondences is along postponing successively;

At least two assembled units, be used for continuous three discrete signals that obtained represent first signal to effective edge along when upset, pairing phase clock signal reach effective edge along the time export effective commencing signal; Be used at the discrete signal of the trigger of correspondence output double during for same effective value, pairing phase clock signal reach effective edge along the time output pulse signal; Be used for when continuous three discrete signals that obtained are represented first signal from effective edge along upset, pairing phase clock signal reach effective edge along the time export effective end signal, the corresponding effective edge of described continuous three discrete signal corresponding reference clocks is along postponing successively;

Counting unit is used for the pulse count signal to being obtained, and obtains an output signal high position;

First coding unit is used for the commencing signal element address that obtains exporting described effective commencing signal according to the effective commencing signal that is obtained;

Second coding unit is used for the end signal element address that obtains exporting described effective end signal according to the effective end signal that is obtained;

Subtrator is used to calculate the commencing signal element address of the effective commencing signal of described output and export the distance of the end signal element address of effective end signal, obtains the output signal low level.

6. phase-locked loop circuit as claimed in claim 2 is characterized in that, described digital loop filters comprises: first multiplier, second multiplier, the 3rd adder, the 4th adder and transfer function are z ^-1Delay unit, the multiplication factor of described first multiplier is Control Parameter α, the multiplication factor of described second multiplier is Control Parameter ρ, wherein,

Described second digital signal obtains an input of described the 3rd adder through described first multiplier, described second digital signal obtains an input of described the 4th adder through described second multiplier, described the 4th adder is output as another input of described the 3rd adder, the output of described the 4th adder obtains another input of described the 4th adder behind described delay unit, described the 3rd adder is output as described digital control signal.

7. phase-locked loop circuit as claimed in claim 2 is characterized in that, described digital controlled oscillator comprises:

First adder and second adder, being respectively applied for adds up to the digital control signal that is received obtains corresponding selection address;

First latch, second latch are used for the selection address sampling of described first adder output is deposited, and sampling clock is the inversion signal of the synthetic clock signal of output;

The 3rd latch, quad latch are used for the selection address sampling of described second adder output is deposited, and sampling clock is respectively the inversion signal and the synthetic clock signal of the synthetic clock signal of output;

The first clock selecting unit and second clock selected cell are respectively applied for the selection address according to described second latch and quad latch output, select the output of respective phase clock signal from the phase clock signal that is received;

The first lap selected cell and the second circle selected cell, be respectively applied for the effective impulse of the phase clock signal of the described first clock selecting unit and second clock selected cell output is counted, count results and the digital control signal that is received are compared, and produce the selection signal that is used to select phase clock signal effective edge edge according to comparative result and the digital control signal that is received;

The 5th latch and the 6th latch, be respectively applied for selection signal according to the described first lap selected cell and the second circle selected cell output, at the corresponding effective edge of the phase clock signal of described first clock selecting unit and the output of second clock selected cell along the described phase clock signal of output;

The 3rd clock selecting unit is used for the phase clock signal of selecting the 5th latch or the 6th latch to export according to the synthetic clock signal on the selecting side;

The output signal unit is used for when the phase clock signal of described the 3rd clock selecting unit output is effective the synthetic clock signal of output.

8. phase-locked loop circuit as claimed in claim 7 is characterized in that, described first lap selected cell comprises:

First counting unit is used for the effective impulse of the phase clock signal that received is counted;

First comparing unit is used for count results with the output of described first counting unit and compares with the digital control signal that is received and obtain first comparative result;

Second counting unit is used for the effective impulse of the inversion signal of the phase clock signal that received is counted;

Second comparing unit is used for count results with the output of described second counting unit and compares with the digital control signal that is received and obtain second comparative result;

Selected cell is used for according to the digital control signal that is received, and selects the selection signal on phase clock signal effective edge edge to export as being used to described first comparative result or second comparative result, perhaps,

Described first lap selected cell comprises:

The combinatorial enumeration unit is used for the effective impulse of the phase clock signal that received is counted to get first count results, and the effective impulse of the inversion signal of the phase clock signal that received is counted to get second count results;

The combination comparing unit is used for described first count results and the digital control signal that received are compared, and obtains first comparative result, is used for described second count results compared with the digital control signal that is received obtaining second comparative result;

Selected cell is used for according to the digital control signal that is received, and selects the selection signal on phase clock signal effective edge edge to export as being used to described first comparative result or second comparative result.

9. phase-locked loop circuit as claimed in claim 7 is characterized in that, the described second circle selected cell comprises:

First counting unit is used for the effective impulse of the phase clock signal that received is counted;

First comparing unit is used for count results with the output of described first counting unit and compares with the digital control signal that is received and obtain first comparative result;

Second counting unit is used for the effective impulse of the inversion signal of the phase clock signal that received is counted;

Second comparing unit is used for count results with the output of described second counting unit and compares with the digital control signal that is received and obtain second comparative result;

Selected cell is used for according to the digital control signal that is received, and selects the selection signal on phase clock signal effective edge edge to export as being used to described first comparative result or second comparative result, perhaps,

The described second circle selected cell comprises:

The combinatorial enumeration unit is used for the effective impulse of the phase clock signal that received is counted to get first count results, and the effective impulse of the inversion signal of the phase clock signal that received is counted to get second count results;

The combination comparing unit is used for described first count results and the digital control signal that received are compared, and obtains first comparative result, is used for described second count results compared with the digital control signal that is received obtaining second comparative result;

Selected cell is used for according to the digital control signal that is received, and selects the selection signal on phase clock signal effective edge edge to export as being used to described first comparative result or second comparative result.

10. a phase-locked loop circuit is characterized in that, comprising:

Time detector is used to export first digital signal, and described first digital signal is used to represent periodic accumulation value poor of the periodic accumulation value of reference clock signal and synthetic clock signal on time-domain;

Digital loop filters, first digital signal of the described time detector output that is used to add up, the output digital control signal, the transfer function of described digital loop filters is

α, ρ are Control Parameter;

Digital controlled oscillator is used for producing described synthetic clock signal according to the digital control signal of described digital loop filters output, and the transfer function of described digital controlled oscillator is

11. phase-locked loop circuit as claimed in claim 10, it is characterized in that, comprise that also free ring shakes, be used to provide multi-phase clock signal, the cycle of described synthetic clock signal equals the product in the time interval on the effective edge edge of phase clock adjacent in digital control signal and the multi-phase clock signal.

12. phase-locked loop circuit as claimed in claim 11, it is characterized in that, described digital loop filters comprises: first multiplier, second multiplier, the 3rd adder, the 4th adder and transfer function are the delay unit of z-1, the multiplication factor of described first multiplier is Control Parameter α, the multiplication factor of described second multiplier is Control Parameter ρ, wherein

An input of described the 3rd adder that described first multiplier of described first digital signal process obtains, described first digital signal obtains an input of described the 4th adder through described second multiplier, described the 4th adder is output as another input of described the 3rd adder, the output of described the 4th adder obtains another input of described the 4th adder behind described delay unit, described the 3rd adder is output as described digital control signal.

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