CN205430206U - Phase locked loop circuit - Google Patents
Phase locked loop circuit Download PDFInfo
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- CN205430206U CN205430206U CN201620223819.9U CN201620223819U CN205430206U CN 205430206 U CN205430206 U CN 205430206U CN 201620223819 U CN201620223819 U CN 201620223819U CN 205430206 U CN205430206 U CN 205430206U
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- resistance
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- electric capacity
- operational amplifier
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Abstract
Phase locked loop circuit. The utility model relates to a phase locked loop circuit that the software and hardware combines. The utility model provides a control algorithm is simple, and response speed is fast and uneven insensitive to grid voltage, the high phase locked loop circuit of stability. Including hardware subtotal software part, the hardware part is including voltage follower, low pass filter, voltage complete period zero cross detection circuit module and CPU, voltage follower, low pass filter, voltage complete period zero cross detection circuit and CPU connect gradually, the software part is including voltage sensor and operation module, voltage sensor arrange in on the electric wire netting and with operation module connects, CPU with operation module connects. The utility model discloses owing to adopted software hardware to combine to carry on the phase locking, so compare with simple software phase -locked loop that to have a control algorithm simple, advantage that response speed is fast, it has voltage unbalance sensitively to compare with single hardware phase -locked loop, and response speed is fast, the high advantage of stability.
Description
Technical field
This utility model relates to a kind of phase-locked loop circuit, particularly relates to the phase-locked loop circuit of a kind of software and hardware combining.
Background technology
In Active Power Filter-APF control, in order to realize, its net side is meritorious, Reactive Power Control.Need to dynamically obtain electric network voltage phase information, thus require that line voltage is carried out phase-locked by phaselocked loop.In actual applications, often requiring that Active Power Filter-APF adapts to non-ideal power grid environment, this proposes higher technical property requirements to corresponding phase lock control.Visible, PHASE-LOCKED LOOP PLL TECHNIQUE is as one of the core of active power filter control technique, and its performance directly influences the service behaviour of Active Power Filter-APF.
Phaselocked loop is generally divided into hardware phase-locked-loop and software phase-lock loop, State Intellectual Property Office 2013-05-15 discloses a utility application (application number: 2011103552024 titles: a kind of phase-locked loop circuit) and specifically discloses a kind of for warbled phase-locked loop circuit, and this phase-locked loop circuit is made up of phase discriminator (101), loop filter (103), voltage controlled oscillator (104), switch element (106) and voltage feedback unit (107).Use above-mentioned phase-locked loop circuit, during modulation frequency signal, after phase lock loop locks frequency, by switch element (106) and voltage feedback unit (107), the frequency control voltage of voltage controlled oscillator (104) is controlled, will not because of cycle of phase-locked loop open loop time cause the frequency control voltage of voltage controlled oscillator (104) to change the most greatly, thus reduce the frequency shifts of voltage controlled oscillator.It is substantially a kind of hardware phase-locked-loop, has the defect that dynamic response is slow, sensitive to unbalanced source voltage.
State Intellectual Property Office 2012-07-25 discloses a utility application (application number: 2012100696790 titles: a kind of software phase-lock loop implementation method based on average value filtering algorithm) and specifically discloses a kind of software phase-lock loop implementation method based on average value filtering algorithm, the method accelerates corresponding speed, and dynamic corresponding time is extremely short.Software phase-lock loop implementation method based on average value filtering algorithm of the present utility model, it comprises the following steps: 1) first carry out three-phase power grid voltage rotating DQ coordinate transform, extracts its meritorious and idle component according to three-phase coordinate transform；2) be averaged value filtering again to Q axis signal, and Q axle is averaged in T/6 interval, obtains the DC quantity of correspondence；3) filtered signal obtains required synchronized angle through the output of increment type pi regulator；4) 32 bit DSPs are used to be programmed, it is achieved software phlase locking.Simple software phase-lock loop, because of control accuracy demand, needs complicated control algolithm, and owing to the defect that dynamic response is slow the most easily occurs in control algolithm complexity.
Utility model content
This utility model is for problem above, it is provided that a kind of control algolithm is simple, fast response time and insensitive to unbalanced source voltage, the phase-locked loop circuit that stability is high.
The technical solution of the utility model is: include hardware components and software section, described hardware components includes voltage follower, low pass filter, voltage complete period zero cross detection circuit module and CPU, and described voltage follower, low pass filter, voltage complete period zero cross detection circuit and CPU are sequentially connected with；
Described software section includes that voltage sensor and computing module, described voltage sensor are placed on electrical network and are connected with described computing module, and described CPU is connected with described computing module.
Described voltage follower includes that operational amplifier one, the outfan of described operational amplifier one are connected with inverting input, and the in-phase input end of described operational amplifier one is connected with described voltage sensor.
Described low pass filter includes resistance one, resistance two, resistance three, electric capacity one, electric capacity two, electric capacity three and operational amplifier two；
The outfan of the one described operational amplifier one of termination of described electric capacity one, one end of another described resistance one of termination of described electric capacity one；
The other end of described resistance one connects one end of described resistance two, one end of electric capacity two and one end of electric capacity three respectively, another termination earth terminal of described resistance two；
The other end of described electric capacity two connects the normal phase input end of described operational amplifier two, and the other end of described electric capacity three connects the outfan of described operational amplifier two；
One end of described resistance three connects the normal phase input end of described operational amplifier two；
The other end of described resistance three connects the outfan of described operational amplifier two.
Voltage complete period zero cross detection circuit module includes voltage comparator, resistance four, resistance five, resistance six and electric capacity four；
The normal phase input end of described voltage comparator is connected with the outfan of described operational amplifier two, is provided with resistance four between the outfan and the normal phase input end of described voltage comparator of described operational amplifier two；
The inverting input of described voltage comparator connects one end of resistance five, another termination earth terminal of described resistance five；
One end of the outfan of described voltage comparator connecting resistance six respectively and one end of electric capacity four, another termination 5V DC source of described resistance five, another termination earth terminal of described electric capacity four.
The outfan of described voltage comparator connects described computing module and connects.
It is phase-locked that this utility model utilizes software and hardware combining technology to carry out, software phase-lock loop carries out simple operation, hardware phase-locked-loop carries out hardware phase lock high precision, the difference utilizing hardware phase-locked-loop and software phase-lock loop carries out computing again after comparing and draws final phase-locked value, this utility model is incorporated into horizontal lock owing to have employed hardware and software, so it is simple to have control algolithm compared with simple software phase-lock loop, the advantage of fast response time, have Voltage unbalance sensitive compared with single hardware phase-locked-loop, fast response time, the advantage that stability is high.
Accompanying drawing explanation
Fig. 1 is this utility model structural representation,
Fig. 2 is hardware circuit diagram in this utility model；
In figure, 1 is operational amplifier one, and 2 is operational amplifier two, and 3 is voltage comparator, C1 is electric capacity one, and C2 is electricity two, and C3 is electric capacity three, C4 is electric capacity four, and R1 is resistance one, and R2 is resistance two, R3 is resistance three, R4 is resistance four, and R5 is resistance five, and R6 is resistance six, VCC is 5V DC source, and GND is earth terminal.
Detailed description of the invention
This utility model is as shown in Figure 1, including hardware components and software section, it is characterized in that, described hardware components includes voltage follower, low pass filter, voltage complete period zero cross detection circuit module and CPU, and described voltage follower, low pass filter, voltage complete period zero cross detection circuit and CPU are sequentially connected with；
Described software section includes that voltage sensor and computing module, described voltage sensor are placed on electrical network and are connected with described computing module, and described CPU is connected with described computing module.Software and hardware combining technology is utilized to carry out phase-locked, software phase-lock loop carries out simple operation, hardware phase-locked-loop carries out hardware phase lock high precision, the difference utilizing hardware phase-locked-loop and software phase-lock loop carries out computing again after comparing and draws final phase-locked value, this utility model is incorporated into horizontal lock owing to have employed hardware and software, so it is simple to have control algolithm compared with simple software phase-lock loop, the advantage of fast response time, have Voltage unbalance sensitive compared with single hardware phase-locked-loop, fast response time, the advantage that stability is high.
This utility model is as in figure 2 it is shown, described voltage follower includes that operational amplifier 1, the outfan of described operational amplifier 1 are connected with inverting input, and the in-phase input end of described operational amplifier 1 is connected with described voltage sensor.Export for being acquired the amplification of signal, convenient identification.
Described low pass filter includes resistance one R1, resistance two R2, resistance three R3, electric capacity one C1, electric capacity two C2, electric capacity three C3 and operational amplifier 22；The outfan of the one described operational amplifier 1 of termination of described electric capacity one C1, one end of described resistance one R1 of another termination of described electric capacity one C1；The other end of described resistance one R1 connects one end of described resistance two R2, one end of electric capacity two C2 and one end of electric capacity three C3 respectively, another termination earth terminal GND of described resistance two R2；The other end of described electric capacity two C2 connects the normal phase input end of described operational amplifier 22, and the other end of described electric capacity three R3 connects the outfan of described operational amplifier 22；One end of described resistance three R3 connects the normal phase input end of described operational amplifier 22；The other end of described resistance three R3 connects the outfan of described operational amplifier 22.Low frequency signal is passed through, high-frequency signal is filtered, reduce interference during utility model works.
Voltage complete period zero cross detection circuit module includes voltage comparator 3, resistance four R4, resistance five R5, resistance six R6 and electric capacity four C4；The normal phase input end of described voltage comparator is connected with the outfan of described operational amplifier 22, is provided with resistance four R4 between the outfan and the normal phase input end of described voltage comparator 3 of described operational amplifier 22；The inverting input of described voltage comparator 3 connects one end of resistance five R5, another termination earth terminal GND of described resistance five R5；One end of the outfan of described voltage comparator connecting resistance six respectively and one end of electric capacity four, another termination 5V DC source VCC of described resistance five, another termination earth terminal GND of described electric capacity four.Send pulse signal when voltage waveform is by zero point, implement phase locking operation, it is to avoid starting the arc phenomenon occurs, protect power grid security.
The outfan of described voltage comparator connects described computing module and connects.Voltage after comparing exports the result phase comparison of computing module and software section, the result that final output accuracy is high.
It is phase-locked that this utility model utilizes software and hardware combining technology to carry out, software phase-lock loop carries out simple operation, hardware phase-locked-loop carries out hardware phase lock high precision, the difference utilizing hardware phase-locked-loop and software phase-lock loop carries out computing again after comparing and draws final phase-locked value, this utility model is incorporated into horizontal lock owing to have employed hardware and software, so it is simple to have control algolithm compared with simple software phase-lock loop, the advantage of fast response time, have Voltage unbalance sensitive compared with single hardware phase-locked-loop, fast response time, the advantage that stability is high.
Claims (5)
1. phase-locked loop circuit, including hardware components and software section, it is characterized in that, described hardware components includes voltage follower, low pass filter, voltage complete period zero cross detection circuit module and CPU, and described voltage follower, low pass filter, voltage complete period zero cross detection circuit and CPU are sequentially connected with；
Described software section includes that voltage sensor and computing module, described voltage sensor are placed on electrical network and are connected with described computing module, and described CPU is connected with described computing module.
Phase-locked loop circuit the most according to claim 1, it is characterized in that, described voltage follower includes that operational amplifier one, the outfan of described operational amplifier one are connected with inverting input, and the in-phase input end of described operational amplifier one is connected with described voltage sensor.
Phase-locked loop circuit the most according to claim 2, it is characterised in that described low pass filter includes resistance one, resistance two, resistance three, electric capacity one, electric capacity two, electric capacity three and operational amplifier two；
The outfan of the one described operational amplifier one of termination of described electric capacity one, one end of another described resistance one of termination of described electric capacity one；
The other end of described resistance one connects one end of described resistance two, one end of electric capacity two and one end of electric capacity three respectively, another termination earth terminal of described resistance two；
The other end of described electric capacity two connects the normal phase input end of described operational amplifier two, and the other end of described electric capacity three connects the outfan of described operational amplifier two；
One end of described resistance three connects the normal phase input end of described operational amplifier two；
The other end of described resistance three connects the outfan of described operational amplifier two.
Phase-locked loop circuit the most according to claim 3, it is characterised in that voltage complete period zero cross detection circuit module includes voltage comparator, resistance four, resistance five, resistance six and electric capacity four；
The normal phase input end of described voltage comparator is connected with the outfan of described operational amplifier two, is provided with resistance four between the outfan and the normal phase input end of described voltage comparator of described operational amplifier two；
The inverting input of described voltage comparator connects one end of resistance five, another termination earth terminal of described resistance five；
One end of the outfan of described voltage comparator connecting resistance six respectively and one end of electric capacity four, another termination 5V DC source of described resistance five, another termination earth terminal of described electric capacity four.
Phase-locked loop circuit the most according to claim 4, it is characterised in that the outfan of described voltage comparator connects described computing module and connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620223819.9U CN205430206U (en) | 2016-03-22 | 2016-03-22 | Phase locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620223819.9U CN205430206U (en) | 2016-03-22 | 2016-03-22 | Phase locked loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205430206U true CN205430206U (en) | 2016-08-03 |
Family
ID=56548670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620223819.9U Expired - Fee Related CN205430206U (en) | 2016-03-22 | 2016-03-22 | Phase locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205430206U (en) |
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2016
- 2016-03-22 CN CN201620223819.9U patent/CN205430206U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160803 Termination date: 20170322 |