CN102412860B - Transmitting/receiving system with frequency and phase detector - Google Patents
Transmitting/receiving system with frequency and phase detector Download PDFInfo
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- CN102412860B CN102412860B CN201010294501.7A CN201010294501A CN102412860B CN 102412860 B CN102412860 B CN 102412860B CN 201010294501 A CN201010294501 A CN 201010294501A CN 102412860 B CN102412860 B CN 102412860B
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Abstract
The invention provides a transmitting/receiving system with a frequency and phase detector. The system comprises a clock/information reply type receiver, a frequency eliminator and a transmitter, wherein the clock/information reply type receiver is used for receiving external signals from a mainframe device, and analyzing the external signals to form a clock signal and an information signal; the frequency eliminator is used for executing frequency elimination on the frequency of the clock signal so as to form a reference clock signal; and the transmitter is used for transmitting an output information content to the mainframe device according to the reference clock signal.
Description
Technical field
The present invention, about a kind of transmission/reception system, relates to a kind of transmission/reception system with frequency and phase detectors especially.
Background technology
In electronic data processing system (EDPS), data transmission and data receive to be needed according to a concussion with reference to clock pulse (Crystal Reference Clock) REF, as shown in Figure 1, for having the block diagram of circumscribed concussion with reference to the transmission/reception system (Transceiver) 100 of clock pulse in prior art, this transmission/reception system 100 comprises clock pulse/data reply type receiver (Clock and Data Recovery Type Receiver) 102, crystal oscillator 104 and conveyer (Transmitter) 106.This clock pulse/data reply type receiver (CDR Type Receiver) 102 receives an external signal RX with a transmission frequency, that is this external signal RX transmits signal to this clock pulse/data reply type receiver 102 with this transmission frequency, and this crystal oscillator 104 provide respectively concussion with reference to clock pulse to this clock pulse/data reply type receiver 102 and conveyer 106.In order to make this clock pulse/data reply type receiver 102 can correctly receive this external signal RX, this concussion must equal the transmission frequency of this external signal RX with reference to clock pulse REF, that is the concussion that this crystal oscillator 104 offers this clock pulse/data reply type receiver 102 must lock (lock) to this transmission frequency with reference to clock pulse, this clock pulse/data reply type receiver 102 could start to receive this external signal RX, but the lock operation of this frequency must could operate by many group testing circuits, but this testing circuit is difficult for being accurately locked to the frequency of this transmission clock pulse, cause the use elasticity of the frequency of operation of this clock pulse/data reply type receiver 102 to be subject to sizable limitation, that is concussion with reference to the frequency-splitting between clock pulse and this transmission frequency must be accurate to ± 0.5% in, this clock pulse/data reply type receiver 102 is just enough to lock this external signal, to produce clock signal and data signal, and make conveyer 106 produce output data.And this transmission/reception system 100 also must additionally arrange this crystal oscillator 104 to produce this concussion with reference to clock pulse, causes increasing manufacturing cost.In view of this, need to develop a kind of new-type transmission/reception system, to address the above problem.
Summary of the invention
One object of the present invention is to provide a kind of transmission receiving system with frequency/phase detector, the clock signal parsing by reception one external signal, as the reference clock signal of conveyer, to simplify the circuit design of transmission/reception system, and save manufacturing cost.
Another object of the present invention is to provide a kind of transmission receiving system with frequency/phase detector, lock frequency and the phase place of this external signal by a receiver, even if make frequency-splitting between initial voltage-controlled oscillator signal and the transmission frequency of this external signal under larger error range, for example ± 10%, still can be adjusted to the frequency accuracy scope that receiver can be worked, to increase the use elasticity of this transmission receiving system.
For reaching above-mentioned purpose, the invention provides a kind of transmission/reception system with frequency/phase detector, this transmission/reception system comprises clock pulse/data reply type receiver, frequency eliminator and conveyer.This clock pulse/data reply type receiver receives the external signal (S_ext) from this host apparatus, and resolves this external signal to form a clock signal (S_clk) and a data signal (S_dat).This frequency eliminator is carried out frequency elimination processing in order to the frequency to this clock signal, to form one with reference to clock signal (S_ref).This conveyer according to this with reference to clock signal to transmit an output data content (S_out) to this host apparatus.
Because only utilizing the clock signal (S_clk) that this clock pulse/data reply type receiver can parse by an external signal (S_ext), this conveyer exports data content (S_out) as transmitting with reference to clock signal (S_ref), therefore the transmission/reception system of the present invention with frequency/phase detector can produce a clock signal (S_clk) by the clock signal (S_clk) parsing, simplify the circuit design of transmission/reception system, and save manufacturing cost.
Specifically, this clock pulse/data reply type receiver comprises comparator, phase detectors, frequency detector, loop filter, switch, digital-analog convertor (Digital to Analog Converter, DAC), voltage-controlled oscillator (VCO) (Voltage-controlled Oscillator, VCO) and modulator.This comparator is according to a sample frequency (S_sfre), so that this external signal (S_ext) is sampled, to produce this data signal (S_dat) and a sampled signal (S_sam).These phase detectors are in order to detect the first voltage-controlled oscillator signal (S_vco1) and this sampled signal (S_sam) phase difference between the two, to produce a first-phase potential difference xor signal (S_ph1), and these phase detectors detect one second voltage-controlled oscillator signal (S_vco2) and this sampled signal (S_sam) phase difference between the two, to produce a second-phase potential difference xor signal (S_ph2).This frequency detector is coupled to described phase detectors, in order to detect the frequency of this first-phase potential difference xor signal (S_ph1), to produce a first frequency difference signal (S_fre1), and this frequency detector detects the frequency of this second-phase potential difference xor signal (S_ph2), to produce a second frequency difference signal (S_fre2).
This modulator is in order to this first frequency difference signal (S_fre1) relatively and this second frequency difference signal (S_fre2), if this second frequency difference signal (S_fre2) is less than this first frequency difference signal (S_fre1), continue to downgrade this second frequency difference signal (S_fre2) until level off to a minimum frequency poor (S_fmin), if this second frequency difference signal (S_fre2) is greater than this first frequency difference signal (S_fre1), continue to downgrade this first frequency difference signal (S_fre1) until level off to this minimum frequency poor (S_fmin).This voltage-controlled oscillator (VCO) is in order to produce described the first voltage-controlled oscillator signal (S_vco1), and when described frequency detector according to this first frequency difference signal (S_fre1) when adjusting the frequency of described voltage-controlled oscillator (VCO), produce described the second voltage-controlled oscillator signal (S_vco2) by described voltage-controlled oscillator (VCO), so that this first voltage-controlled oscillator signal (S_vco1) and this second voltage-controlled oscillator signal (S_vco2) both one of them level off to the transmission frequency of this external signal (S_ext); In one embodiment, this voltage-controlled oscillator (VCO) can directly send the signal of sample frequency or the transmission frequency close to external signal, or utilizes multiple phase (Multi-phase) processing mode that sample frequency or transmission frequency are divided into multiple cell frequencies to be issued to respectively this comparator.This switch is electrically connected to this voltage-controlled oscillator (VCO) in order to switch this frequency detector and this phase detectors both one of them.
The transmission/reception system with frequency/phase detector of the present invention, by resolving a clock signal that receives external signal, simultaneously as the reference clock signal of conveyer and the reference clock signal for the treatment of circuit, to simplify the circuit design of transmission/reception system.Further lock frequency and the phase place of this external signal by a receiver, make frequency-splitting between initial voltage-controlled oscillator signal and the transmission frequency of this external signal under in a big way, the frequency accuracy scope that still initial voltage-controlled oscillator signal to the receiver of capable of regulating can be worked, and then the data of parsing external signal, to increase the use elasticity of this transmission receiving system.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below:
Brief description of the drawings
Fig. 1 has the block diagram of circumscribed concussion with reference to the transmission/reception system of clock pulse in prior art.
Fig. 2 is the block diagram of the built-in transmission/reception system with reference to clock pulse in the embodiment of the present invention.
Fig. 3 is the more detailed block diagram of clock pulse/data reply type receiver in Fig. 2 of the present invention.
Fig. 4 is the timing waveform of the phase difference between voltage-controlled oscillator signal and this sampled signal in the embodiment of the present invention.
Fig. 5 is the adjust frequency wavy curve schematic diagram of detector of modulator in the embodiment of the present invention.
Fig. 6 A-6B is the flow chart of the built-in transmission/reception method with reference to clock pulse in the embodiment of the present invention.
Label described in accompanying drawing is respectively:
100 transmission/reception system 102 clock pulses/data reply type receivers
104 crystal oscillator 106 conveyers
200 transmission/reception system 202 clock pulses/data reply type receivers
204 frequency eliminator 206 conveyers
208 host apparatus 210 treatment circuits
212 coder/decoder 300 comparators
302 phase detectors 304 frequency detectors
306 loop filter 308 switchs
310 digital-analog convertor 312 voltage-controlled oscillator (VCO)s
314 modulator 316 wavy curves
Embodiment
Preferred embodiment of the present invention is described in detail by accompanying drawing and explanation below, different graphic in, identical component symbol represents same or analogous element.
With reference to figure 2, it is the block diagram of the built-in transmission/reception system 200 with frequency/phase detector with reference to clock pulse in the embodiment of the present invention.This transmission/reception system 200 couples this host apparatus 208 in treatment circuit 210, this transmission/reception system 200 receives the external signal (S_ext) of this host apparatus 208, and after processing through this treatment circuit 210, the foundation one output data content (S_out) of passing processing back with reference to clock signal (S_ref) is to this host apparatus 208.This transmission/reception system 200 comprises clock pulse/data reply type receiver 202, frequency eliminator 204 and conveyer 206.This clock pulse/data reply type receiver 202 is coupled to this host apparatus 208, this frequency eliminator 204 is coupled to this clock pulse/data reply type receiver 202, this conveyer 206 is coupled to this frequency eliminator 204 and this treatment circuit 210, and this frequency eliminator 204 is coupled to this treatment circuit 210.
This clock pulse/data reply type receiver 202 receives and comes from the external signal (S_ext) of this host apparatus 208, and resolves this external signal (S_ext) to form a clock signal (S_clk) and a data signal (S_dat).This frequency eliminator 204 is carried out frequency elimination processing in order to the frequency to this clock signal (S_clk), to form one with reference to clock signal (S_ref), to reduce the frequency of this clock signal (S_clk).In another embodiment, also can make process of frequency multiplication.This conveyer 206 according to this with reference to clock signal (S_ref) to transmit an output data content (S_out) to this host apparatus 208.
Because only utilizing the clock signal (S_clk) that this clock pulse/data reply type receiver 202 produces, this conveyer 206 exports data content (S_out) as transmitting with reference to clock signal (S_ref), use and this crystal oscillator 104 is additionally set to produce this concussion with reference to clock pulse compared to prior art, as shown in Figure 1, not accurately and comparatively complicated, cost is high, and the clock signal (S_clk) that the transmission/reception system 200 with frequency/phase detector of the present invention parses by reception one external signal (S_ext), effectively simplify the circuit design of transmission/reception system 200, and saving manufacturing cost.
With reference to figure 2 and Fig. 3, Fig. 3 is the more detailed block diagram of clock pulse/data reply type receiver 202 in Fig. 2 of the present invention.This clock pulse/data reply type receiver 202 comprises comparator 300, phase detectors 302, frequency detector 304, loop filter 306, switch 308, digital-analog convertor (Digital toAnalog Converter, DAC) 310, voltage-controlled oscillator (VCO) (Voltage-controlled Oscillator, VCO) 312 and modulator 314.This comparator 300 is coupled to this host apparatus 208, these phase detectors 302 are coupled to this comparator 300, this frequency detector 304 is coupled to this phase detectors 302, this loop filter 306 couples these phase detectors 302 to this switch 308, this digital-analog convertor (DAC) 310 couples this frequency detector 304 to this switch 308, this switch respectively selectivity couples this loop filter 306 and this digital-analog convertor (DAC) 310 to this voltage-controlled oscillator (VCO) (VCO) 312, this voltage-controlled oscillator (VCO) (VCO) 312 is coupled to this comparator 300, and this frequency eliminator 204 is coupled between this voltage-controlled oscillator (VCO) (VCO) 312 and this comparator 300, this modulator 314 is coupled to this frequency detector 304.
This comparator 300 is according to a sample frequency (S_sfre), so that this external signal (S_ext) is sampled, to produce this data signal (S_dat) and a sampled signal (S_sam).These phase detectors 302 are in order to detect the first voltage-controlled oscillator signal (S_vco1) and this sampled signal (S_sam) phase difference between the two, to produce a first-phase potential difference xor signal (S_ph1), and these phase detectors detect one second voltage-controlled oscillator signal (S_vco2) and this sampled signal (S_sam) phase difference between the two, to produce a second-phase potential difference xor signal (S_ph2).This frequency detector 304 is in order to detect the frequency of this first-phase potential difference xor signal (S_ph1), to produce a first frequency difference signal (S_fre1), and this frequency detector 304 detects the frequency of this second-phase potential difference xor signal (S_ph2), to produce a second frequency difference signal (S_fre2).
This modulator 314 is in order to this first frequency difference signal (S_fre1) relatively and this second frequency difference signal (S_fre2), if this second frequency difference signal (S_fre2) is less than this first frequency difference signal (S_fre1), continue to downgrade this second frequency difference signal (S_fre2) until level off to a minimum frequency poor (S_fmin), if this second frequency difference signal (S_fre2) is greater than this first frequency difference signal (S_fre1), continue to downgrade this first frequency difference signal (S_fre1) until level off to this minimum frequency poor (S_fmin).This voltage-controlled oscillator (VCO) 312 is in order to produce described the first voltage-controlled oscillator signal (S_vco1), and when described frequency detector according to this first frequency difference signal (S_fre1) when adjusting the frequency of described voltage-controlled oscillator (VCO), produce described the second voltage-controlled oscillator signal (S_vco2) by described voltage-controlled oscillator (VCO), so that this first voltage-controlled oscillator signal (S_vco1) and this second voltage-controlled oscillator signal (S_vco2) both one of them level off to the transmission frequency of this external signal (S_ext); In one embodiment, this voltage-controlled oscillator (VCO) 312 can directly send the signal of sample frequency (for example 10GHz) or the transmission frequency (for example 5GHz) close to external signal, or (for example 1Ghz) is issued to respectively this comparator 300 to utilize multiple phase (Multi-phase) that sample frequency or transmission frequency are divided into multiple cell frequencies.This switch 308 is electrically connected to this voltage-controlled oscillator (VCO) 312 in order to switch this frequency detector 304 and this phase detectors 302 both one of them.
The sample frequency (S_sfre) of this comparator 300 is respectively the multiple of this first voltage-controlled oscillator signal (S_vco1) and this second voltage-controlled oscillator signal frequency (S_vco2).For example utilize frequency multiplier (not shown) that this first voltage-controlled oscillator signal (S_vco1) and this second voltage-controlled oscillator signal frequency (S_vco2) are carried out being sent to this comparator 300 after process of frequency multiplication, as this sample frequency (S_sfre).In addition, it should be noted, this clock signal (S_clk) and this are Frequency Synchronization with reference to clock signal (S_ref), and this Frequency Synchronization refers to that frequency is identical or via tool certain proportion relation after frequency elimination/frequency multiplication.
With reference to figure 3 and Fig. 4, Fig. 4 is the timing waveform of the phase difference between voltage-controlled oscillator signal in the embodiment of the present invention (S_vco1, S_vco2) and this sampled signal (S_sam).Transverse axis represents the time, and the longitudinal axis represents signal amplitude.This first-phase potential difference xor signal (S_ph1) is in order to represent this leading this sampled signal of the first voltage-controlled oscillator signal (S_vco1) (S_sam) or this first voltage-controlled oscillator signal (S_vco1) lags behind this sampled signal (S_sam), this second-phase potential difference xor signal (S_ph2) is in order to represent this leading this sampled signal of the second voltage-controlled oscillator signal (S_vco2) (S_sam) or this second voltage-controlled oscillator signal (S_vco2) lags behind this sampled signal (S_sam), and sampled signal (S_sam) refers to that sample frequency (S_sfre) is to external signal (S_ext) signal producing of sampling herein.In one embodiment, sample frequency (S_sfre) is this first voltage-controlled oscillator signal (S_vco1) or the twice of this second voltage-controlled oscillator signal (S_vco2), also can be multiple arbitrarily.
With reference to figure 3 and Fig. 5, Fig. 5 is adjust frequency wavy curve 316 schematic diagrames of detector 304 of modulator 314 in the embodiment of the present invention.Transverse axis represents the frequency of voltage-controlled oscillator signal, and the longitudinal axis represents the poor absolute value of signal frequency.According to this wavy curve 316, this modulator 314 is the frequency size of this first voltage-controlled oscillator signal (S_vco1) and this second voltage-controlled oscillator signal (S_vco2) relatively, when this second voltage-controlled oscillator signal (S_vco2) is greater than this first voltage-controlled oscillator signal (S_vco1), if this second frequency difference signal (S_fre2) is less than this first frequency difference signal (S_fre1), continue to downgrade this second frequency difference signal (S_fre2) until level off to a minimum frequency poor (S_fmin), so that the frequency approach of this second voltage-controlled oscillator signal (S_vco2) is in this transmission frequency of this external signal (S_ext), as shown in arrow label I, herein, the Frequency Locking that minimum frequency poor (S_fmin) represents voltage-controlled oscillator signal is to this transmission frequency, if this second frequency difference signal (S_fre2) is greater than this first frequency difference signal (S_fre1), continue to downgrade this first frequency difference signal (S_fre1) until level off to this minimum frequency poor (S_fmin), so that the frequency approach of this first voltage-controlled oscillator signal (S_vco1) is in this transmission frequency, as shown in arrow label II.
According to this wavy curve 316, when this second voltage-controlled oscillator signal (S_vco2) is less than this first voltage-controlled oscillator signal (S_vco1), if this second frequency difference signal (S_fre2) is less than this first frequency difference signal (S_fre1), continue to downgrade this second frequency difference signal (S_fre2) until level off to this minimum frequency poor (S_fmin), so that the frequency approach of this second voltage-controlled oscillator signal (S_vco2) is in this transmission frequency, as shown in arrow label III; If this second frequency difference signal (S_fre2) is greater than this first frequency difference signal (S_fre1), continue to downgrade this first frequency difference signal (S_fre1) until level off to this minimum frequency poor (S_fmin), so that the frequency approach of this first voltage-controlled oscillator signal (S_vco1) is in this transmission frequency, as shown in arrow label IV.
Before this frequency detector 304 not yet completes this voltage-controlled oscillator signal and external signal (S_ext) Frequency Synchronization, this switch 308 switches to this frequency detector 304, when this frequency detector 304 completes after this voltage-controlled oscillator signal (S_vco1, S_vco2) and external signal (S_ext) Frequency Synchronization, this switch 308 switches to this phase detectors 302.
According to above-mentioned, frequency-splitting between this first, second voltage-controlled oscillator signal (S_vco1, S_vco2) and the transmission frequency of this external signal (S_ext) is within a looser scope, for example ± 10%, this clock pulse/data reply type receiver 202 can be adjusted the initial frequency precise accuracy of voltage-controlled oscillator signal in can working range via aforesaid way, then resolves the data of external signal (S_ext); Then after this frequency detector 304 completes this voltage-controlled oscillator signal (S_vco1, S_vco2) and external signal (S_ext) Frequency Synchronization, this switch 308 switches to this phase detectors 302.Therefore, the transmission receiving system with frequency/phase detector of the present invention, by frequency and the phase place of one clock pulse/data reply type receiver, 202 these external signals of locking (S_ext), adjust in the scope that the frequency-splitting between voltage-controlled oscillator signal (S_vco1, S_vco2) and the transmission frequency of this external signal (S_ext) can work at receiver, to increase the use elasticity of this transmission receiving system.
In addition,, in clock pulse/data reply type receiver 202, this loop filter 306 is in order to the noise signal of this first-phase potential difference xor signal (S_ph1) of filtering and this second-phase potential difference xor signal (S_ph2).This digital-analog convertor 310 is in order to change this first frequency difference signal (S_fre1) and this second frequency difference signal (S_fre2).In one embodiment, this transmission/reception system 200 is coupled to a coder/decoder 212, with reference to clock signal (S_ref), this data signal (S_dat) is carried out to the processing of coding/decoding according to this, this coder/decoder 212 is for example arranged in this treatment circuit 210.
With reference to figure 2, Fig. 3 and Fig. 6 A and 6B, Fig. 6 A and 6B are the flow chart of the built-in transmission/reception method with reference to clock pulse in the embodiment of the present invention, the method is applicable to a transmission/reception system 200, this transmission/reception system is connected in a host apparatus 208, wherein this transmission/reception system 200 comprises one clock pulse/data reply type receiver 202, one frequency eliminator 204 and a conveyer 206, this clock pulse/data reply type receiver 202 comprises a comparator 300, one phase detectors 302, one frequency detector 304, one voltage-controlled oscillator (VCO) 312, modulator 314 and a switch 308, this transmission/reception method comprises the following steps, as shown in Figure 6A.
In step S600, the external signal (S_ext) that this clock pulse/data reply type receiver 202 receives from this host apparatus 208.
In step S602, this clock pulse/data reply type receiver 202 is resolved this external signal (S_ext), to form a clock signal (S_clk) and a data signal (S_dat).
In step S604, this frequency eliminator 204 is carried out frequency elimination processing to the frequency of this clock signal (S_clk), to form one with reference to clock signal (S_ref), wherein this clock signal (S_clk) and this are Frequency Synchronization with reference to clock signal (S_ref).
In step S606, this conveyer 206 according to this with reference to clock signal (S_ref) to transmit an output data content (S_out) to this host apparatus 208.
In step S602, also comprise the following steps, as shown in Figure 6B.
In step S602-1, this comparator 300 is according to a sample frequency (S_sfre), so that this external signal (S_ext) is sampled, to produce this data signal (S_dat) and a sampled signal (S_sam).
In step S602-2, these phase detectors 302 detect one first voltage-controlled oscillator signal (S_vco1) and this sampled signal (S_sam) phase difference between the two, to produce a first-phase potential difference xor signal (S_ph1).
In step S602-3, this frequency detector 304 detects the frequency of this first-phase potential difference xor signal (S_ph1), to produce a first frequency difference signal (S_fre1).
In step S602-4, this frequency detector 304 is according to this first frequency difference signal (S_fre1), to adjust the frequency of this voltage-controlled oscillator (VCO) 312, to form one second voltage-controlled oscillator signal (S_fre2).
In step S602-5, these phase detectors 302 detect this second voltage-controlled oscillator signal (S_vco2) and this sampled signal (S_sam) phase difference between the two, to produce a second-phase potential difference xor signal (S_ph2), wherein this sample frequency (S_sfre) is respectively the multiple of this first voltage-controlled oscillator signal (S_vco1) and this second voltage-controlled oscillator signal (S_vco2) frequency.
In step S602-6, this frequency detector 304 detects the frequency of this second-phase potential difference xor signal (S_ph2), to produce a second frequency difference signal (S_fre2).
In step S602-7, relatively this first frequency difference signal (S_fre1) and this second frequency difference signal (S_fre2), if this second frequency difference signal (S_fre2) is less than this first frequency difference signal (S_fre1), continue to downgrade this second frequency difference signal (S_fre2) until level off to a minimum frequency poor (S_fmin), if this second frequency difference signal (S_fre2) is greater than this first frequency difference signal (S_fre1), continue to downgrade this first frequency difference signal (S_fre1) until level off to this minimum frequency poor (S_fmin), wavy curve 316 as shown in Figure 5.In step S602-7, also comprise step: the relatively frequency size of this first voltage-controlled oscillator signal (S_vco1) and this second voltage-controlled oscillator signal (S_vco2), when this second voltage-controlled oscillator signal (S_vco2) is greater than this first voltage-controlled oscillator signal (S_vco1), if this second frequency difference signal (S_fre2) is less than this first frequency difference signal (S_fre1), continue to downgrade this second frequency difference signal (S_fre2) until level off to a minimum frequency poor (S_fmin), so that the frequency approach of this second voltage-controlled oscillator signal (S_vco2) is in a transmission frequency of this external signal (S_ext), if this second frequency difference signal (S_fre2) is greater than this first frequency difference signal (S_fre1), continue to downgrade this first frequency difference signal (S_fre1) until level off to this minimum frequency poor (S_fmin), so that the frequency approach of this first voltage-controlled oscillator signal (S_vco1) is in this transmission frequency, when this second voltage-controlled oscillator signal (S_vco2) is less than this first voltage-controlled oscillator signal (S_vco1), if this second frequency difference signal (S_fre2) is less than this first frequency difference signal (S_fre1), continue to downgrade this second frequency difference signal (S_fre2) until level off to this minimum frequency poor (S_fmin), so that the frequency approach of this second voltage-controlled oscillator signal (S_vco2) is in this transmission frequency, if this second frequency difference signal (S_fre2) is greater than this first frequency difference signal (S_fre1), continue to downgrade this first frequency difference signal (S_fre1) until level off to this minimum frequency poor (S_fmin), so that the frequency approach of this first voltage-controlled oscillator signal (S_vco1) is in this transmission frequency.
In step S602-8, this switch 308 switches to this phase detectors 302 by this frequency detector 304, adjust the phase place of this voltage-controlled oscillator signal (S_vco1, S_vco2) according to this second-phase potential difference xor signal (S_ph2), so that the phase place of this voltage-controlled oscillator signal (S_vco1, S_vco2) levels off to the phase place of this sampled signal (S_sam).
In one embodiment, this first-phase potential difference xor signal (S_ph1) is in order to represent this leading this sampled signal of the first voltage-controlled oscillator signal (S_vco1) (S_sam) or this first voltage-controlled oscillator signal (S_vco1) lags behind this sampled signal (S_sam), this second-phase potential difference xor signal (S_ph2) is in order to represent this leading this sampled signal of the second voltage-controlled oscillator signal (S_vco2) (S_sam) or this second voltage-controlled oscillator signal (S_vco2) lags behind this sampled signal (S_sam), as shown in Figure 4.
In sum, the invention provides a kind of transmission/reception system with frequency/phase detector, by resolving a clock signal that receives external signal, simultaneously as the reference clock signal of conveyer and the reference clock signal of other devices, to simplify the circuit design of transmission/reception system, and save manufacturing cost.Further lock frequency and the phase place of this external signal by a receiver, make the frequency-splitting between voltage-controlled oscillator signal and the transmission frequency of this external signal only need be in a big way, can resolve the data of external signal, to increase the use elasticity of this transmission receiving system.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; persond having ordinary knowledge in the technical field of the present invention; without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations; for example Frequency Synchronization refers to that two signal frequencies are identical or after frequency elimination/frequency multiplication; tool certain proportion relation; or two signal tool same phase or constant phase difference; all belong to the model that Frequency Synchronization comprises and raise, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (15)
1. a transmission/reception system, is connected in a host apparatus, it is characterized in that, described transmission/reception system comprises:
One clock pulse/data reply type receiver, receives the external signal from described host apparatus, and resolves described external signal to form a clock signal and a data signal;
One frequency eliminator, is coupled to described clock pulse/data reply type receiver, carries out frequency elimination processing, to form one with reference to clock signal in order to the frequency to described clock signal; And
One conveyer, is coupled to described frequency eliminator, according to described with reference to clock signal to transmit an output data content to described host apparatus;
Wherein, described clock pulse/data reply type receiver also comprises:
One comparator, according to a sample frequency, so that described external signal is sampled, to produce described data signal and a sampled signal;
One phase detectors, be coupled to described comparator, in order to detect one first voltage-controlled oscillator signal and described sampled signal phase difference between the two, to produce a first-phase potential difference xor signal, and described phase detectors detect one second voltage-controlled oscillator signal and described sampled signal phase difference between the two, to produce a second-phase potential difference xor signal;
One frequency detector, be coupled to described phase detectors, in order to detect the frequency of described first-phase potential difference xor signal, to produce a first frequency difference signal, and described frequency detector detects the frequency of described second-phase potential difference xor signal, to produce a second frequency difference signal;
One voltage-controlled oscillator (VCO), in order to produce described the first voltage-controlled oscillator signal, and when described frequency detector according to described first frequency difference signal when adjusting the frequency of described voltage-controlled oscillator (VCO), produce described the second voltage-controlled oscillator signal by described voltage-controlled oscillator (VCO), so that described the first voltage-controlled oscillator signal and described the second voltage-controlled oscillator signal both one of them level off to the transmission frequency of described external signal; And
One switch, is electrically connected to described voltage-controlled oscillator (VCO) in order to switch described frequency detector and described phase detectors both one of them.
2. transmission/reception system according to claim 1, it is characterized in that, described first-phase potential difference xor signal is in order to represent the leading described sampled signal of described the first voltage-controlled oscillator signal or described the first voltage-controlled oscillator signal lags behind described sampled signal, and described second-phase potential difference xor signal is in order to represent the leading described sampled signal of described the second voltage-controlled oscillator signal or described the second voltage-controlled oscillator signal lags behind described sampled signal.
3. transmission/reception system according to claim 1, it is characterized in that, also comprise a modulator, be coupled to described frequency detector, in order to more described first frequency difference signal and described second frequency difference signal, if described second frequency difference signal is less than described first frequency difference signal, continue to downgrade described second frequency difference signal until to level off to a minimum frequency poor, if described second frequency difference signal is greater than described first frequency difference signal, continue to downgrade described first frequency difference signal until to level off to described minimum frequency poor.
4. transmission/reception system according to claim 3, it is characterized in that, the frequency size of more described the first voltage-controlled oscillator signal of described modulator and described the second voltage-controlled oscillator signal, when described the second voltage-controlled oscillator signal is greater than described the first voltage-controlled oscillator signal, if described second frequency difference signal is less than described first frequency difference signal, continue to downgrade described second frequency difference signal until to level off to a minimum frequency poor, so that the frequency approach of described the second voltage-controlled oscillator signal is in the described transmission frequency of described external signal, if described second frequency difference signal is greater than described first frequency difference signal, continue to downgrade described first frequency difference signal until to level off to described minimum frequency poor, so that the frequency approach of described the first voltage-controlled oscillator signal is in described transmission frequency, when described the second voltage-controlled oscillator signal is less than described the first voltage-controlled oscillator signal, if described second frequency difference signal is less than described first frequency difference signal, continue to downgrade described second frequency difference signal until to level off to described minimum frequency poor, so that the frequency approach of described the second voltage-controlled oscillator signal is in described transmission frequency, if described second frequency difference signal is greater than described first frequency difference signal, continue to downgrade described first frequency difference signal until to level off to described minimum frequency poor, so that the frequency approach of described the first voltage-controlled oscillator signal is in described transmission frequency.
5. transmission/reception system according to claim 1, it is characterized in that, described clock pulse/data reply type receiver also comprises a loop filter, be coupled between described phase detectors and described switch, in order to the noise signal of first-phase potential difference xor signal described in filtering and described second-phase potential difference xor signal.
6. transmission/reception system according to claim 1, it is characterized in that, described clock pulse/data reply type receiver also comprises a digital-analog convertor, be coupled between described frequency detector and described switch, in order to change described first frequency difference signal and described second frequency difference signal.
7. transmission/reception system according to claim 1, is characterized in that, the described sample frequency of described comparator is respectively the multiple of described the first voltage-controlled oscillator signal and described the second voltage-controlled oscillator signal frequency.
8. transmission/reception system according to claim 1, is characterized in that, also comprises a coder/decoder, according to the described processing of with reference to clock signal, described data signal being carried out coding/decoding.
9. transmission/reception system according to claim 1, is characterized in that, described clock signal and described be Frequency Synchronization with reference to clock signal.
10. one kind has the transmission/reception method of frequency and phase-detection, be applicable to a transmission/reception system, described transmission/reception system is connected in a host apparatus, it is characterized in that, described transmission/reception system comprises one clock pulse/data reply type receiver, a frequency eliminator and a conveyer, described clock pulse/data reply type receiver comprises a comparator, phase detectors, a frequency detector, a voltage-controlled oscillator (VCO) and a switch, and described transmission/reception method comprises the following steps:
(a) described clock pulse/data reply type receiver receives the external signal from described host apparatus;
(b) described clock pulse/data reply type receiver is resolved described external signal, to form a clock signal and a data signal;
(c) described frequency eliminator is carried out frequency elimination processing to the frequency of described clock signal, to form one with reference to clock signal; And
(d) described conveyer according to described with reference to clock signal to transmit an output data content to described host apparatus;
Wherein, in step (b), also comprise the following steps:
(b1) described comparator is according to a sample frequency, so that described external signal is sampled, to produce described data signal and one
Sampled signal;
(b2) described phase detectors detect one first voltage-controlled oscillator signal and described sampled signal phase difference between the two, to produce a first-phase potential difference xor signal;
(b3) described frequency detector detects the frequency of described first-phase potential difference xor signal, to produce a first frequency difference signal;
(b4) described frequency detector is according to described first frequency difference signal, to adjust the frequency of described voltage-controlled oscillator (VCO), to form one second voltage-controlled oscillator signal;
(b5) described phase detectors detect described the second voltage-controlled oscillator signal and described sampled signal phase difference between the two, to produce a second-phase potential difference xor signal;
(b6) described frequency detector detects the frequency of described second-phase potential difference xor signal, to produce a second frequency difference signal; And
(b7) more described first frequency difference signal and described second frequency difference signal, if described second frequency difference signal is less than described first frequency difference signal, continue to downgrade described second frequency difference signal until to level off to a minimum frequency poor, if described second frequency difference signal is greater than described first frequency difference signal, continue to downgrade described first frequency difference signal until to level off to described minimum frequency poor.
11. transmission/reception methods according to claim 10, it is characterized in that, described first-phase potential difference xor signal is in order to represent the leading described sampled signal of described the first voltage-controlled oscillator signal or described the first voltage-controlled oscillator signal lags behind described sampled signal, and described second-phase potential difference xor signal is in order to represent the leading described sampled signal of described the second voltage-controlled oscillator signal or described the second voltage-controlled oscillator signal lags behind described sampled signal.
12. transmission/reception methods according to claim 10, it is characterized in that, in step (b7), also comprise step (b7-1): the frequency size of more described the first voltage-controlled oscillator signal and described the second voltage-controlled oscillator signal, when described the second voltage-controlled oscillator signal is greater than described the first voltage-controlled oscillator signal, if described second frequency difference signal is less than described first frequency difference signal, continue to downgrade described second frequency difference signal until to level off to a minimum frequency poor, so that the frequency approach of described the second voltage-controlled oscillator signal is in a transmission frequency of described external signal, if described second frequency difference signal is greater than described first frequency difference signal, continue to downgrade described first frequency difference signal until to level off to described minimum frequency poor, so that the frequency approach of described the first voltage-controlled oscillator signal is in described transmission frequency, when described the second voltage-controlled oscillator signal is less than described the first voltage-controlled oscillator signal, if described second frequency difference signal is less than described first frequency difference signal, continue to downgrade described second frequency difference signal until to level off to described minimum frequency poor, so that the frequency approach of described the second voltage-controlled oscillator signal is in described transmission frequency, if described second frequency difference signal is greater than described first frequency difference signal, continue to downgrade described first frequency difference signal until to level off to described minimum frequency poor, so that the frequency approach of described the first voltage-controlled oscillator signal is in described transmission frequency.
13. transmission/reception methods according to claim 10, it is characterized in that, also comprise afterwards step (b8) in step (b7): described switch switches to described phase detectors by described frequency detector, adjust the phase place of described voltage-controlled oscillator signal according to described second-phase potential difference xor signal, so that the phase place of described voltage-controlled oscillator signal levels off to the phase place of described sampled signal.
14. transmission/reception methods according to claim 10, is characterized in that, described sample frequency is respectively the multiple of described the first voltage-controlled oscillator signal and described the second voltage-controlled oscillator signal frequency.
15. transmission/reception methods according to claim 10, is characterized in that, described clock signal and described be Frequency Synchronization with reference to clock signal.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6215835B1 (en) * | 1997-08-22 | 2001-04-10 | Lsi Logic Corporation | Dual-loop clock and data recovery for serial data communication |
| CN101436856A (en) * | 2007-11-13 | 2009-05-20 | 华硕电脑股份有限公司 | Frequency synchronization device, frequency synchronization method and frequency generating apparatus using the method |
| CN101465723A (en) * | 2007-12-21 | 2009-06-24 | 阿尔特拉公司 | Transceiver system with reduced latency uncertainty |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6215835B1 (en) * | 1997-08-22 | 2001-04-10 | Lsi Logic Corporation | Dual-loop clock and data recovery for serial data communication |
| CN101436856A (en) * | 2007-11-13 | 2009-05-20 | 华硕电脑股份有限公司 | Frequency synchronization device, frequency synchronization method and frequency generating apparatus using the method |
| CN101465723A (en) * | 2007-12-21 | 2009-06-24 | 阿尔特拉公司 | Transceiver system with reduced latency uncertainty |
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