WO2007037086A1 - Substrat avec composant intégré et procédé de fabrication d'un tel substrat - Google Patents

Substrat avec composant intégré et procédé de fabrication d'un tel substrat Download PDF

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Publication number
WO2007037086A1
WO2007037086A1 PCT/JP2006/316833 JP2006316833W WO2007037086A1 WO 2007037086 A1 WO2007037086 A1 WO 2007037086A1 JP 2006316833 W JP2006316833 W JP 2006316833W WO 2007037086 A1 WO2007037086 A1 WO 2007037086A1
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WO
WIPO (PCT)
Prior art keywords
component
wiring
wiring board
board
embedded
Prior art date
Application number
PCT/JP2006/316833
Other languages
English (en)
Japanese (ja)
Inventor
Koichi Hirano
Tsukasa Shiraishi
Shingo Komatsu
Toshiyuki Kojima
Yukihiro Ishimaru
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2007037086A1 publication Critical patent/WO2007037086A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Definitions

  • the present invention relates to a component built-in substrate in which an electronic component is built.
  • the present invention also relates to an electronic device provided with such a component-embedded substrate, and a background art relating to a method of manufacturing the component-embedded substrate.
  • active parts for example, semiconductor elements
  • passive parts for example, capacitors
  • the circuit component built-in module 400 shown in FIG. 9 includes a substrate 401 in which insulating substrates 401a, 401b, and 401c are stacked, and self-turn lines 402a, 402b, 402c, and 402d formed on the main surface and inside of the substrate 401. , Put yourself in the inner part of board 401 And a circuit component 403 connected to the wiring pattern.
  • FIGS. 7 to 8 of Patent Document 2 there is a proposal of projecting an electrically insulating layer of a substrate on which a semiconductor element is mounted to form a stepped shape.
  • Patent Document 1 Japanese Patent Laid-Open No. 11-220262
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2004-281578 (FIGS. 7 to 8)
  • each layer (402a, 402b, 402c, 402d) is electrically connected by an inner via 404.
  • the inner via connection method is used, only necessary layers can be connected, and the circuit component is excellent in mountability, so that it can be preferably used.
  • the conventional component circuit board including the circuit component built-in module 400 ensures electrical communication between the upper surface and the lower surface by the conductive via 404.
  • the surface itself of the circuit component built-in module 400 is often used as a component mounting surface, it is not possible to expose all the inspection terminals of the built-in electronic component 403c on the surface of the circuit component built-in module 400. Unreasonableness occurs. In other words, high density mounting is possible.
  • the component built-in board configuration it is designed to provide an electrical extraction electrode on the surface (upper surface or bottom surface) of the component built-in board only for inspecting the built-in electronic components. If such a design is adopted, the area of the component-embedded board will increase and the number of unnecessary terminals will increase.
  • the surface of the protruding substrate is covered with an electrical insulating layer that also serves as a support material, so that the wiring layer is not exposed to the outside. It was difficult to inspect the electronic components.
  • the present invention has been made in view of the above points, and provides a component-embedded substrate and a method for manufacturing the same, in which a built-in electronic component can be easily inspected.
  • the component-embedded substrate of the present invention is a component-embedded substrate in which an electronic component is embedded, and the component-embedded substrate is configured by laminating a plurality of wiring layers, and the plurality of wiring layers Among them, at least one of the inner layers on which the active component is mounted protrudes from the other wiring layers, and the wiring patterns of the inner layers are exposed.
  • a method for manufacturing a component-embedded substrate according to the present invention is a method for manufacturing a component-embedded substrate in which an electronic component is embedded, and an inner layer wiring board on which an active component is mounted and an upper layer sandwiching the inner layer wiring board.
  • a step of interposing a sheet-like resin composition between the wiring board and the lower wiring board, between the inner wiring board and the upper wiring board, and between the inner wiring board and the lower wiring board (a ), Projecting at least one layer of the inner layer on which the active component is mounted with another wiring layer force and exposing the wiring pattern of the inner layer, the upper layer wiring board, the inner layer wiring board, and the It includes a step (c) of laminating and integrating the lower wiring board.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in substrate in one embodiment of the present invention.
  • FIG. 2 is a plan view schematically showing a configuration of a component built-in substrate in one embodiment of the present invention.
  • FIGS. 3A and 3B are diagrams illustrating a method of manufacturing a component-embedded substrate according to an embodiment of the present invention. It is process sectional drawing for demonstrating a method.
  • FIG. 4A to FIG. 4C are process cross-sectional views for explaining a method for manufacturing a component-embedded substrate in one embodiment of the present invention.
  • FIG. 5A and FIG. 5B are process cross-sectional views for explaining a method for manufacturing a component-embedded substrate in one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view schematically showing a component built-in board according to another embodiment of the present invention.
  • FIG. 7 is a cross-sectional view schematically showing a component-embedded substrate in still another embodiment of the present invention.
  • FIG. 8 is a cross-sectional view schematically showing a component-embedded substrate in still another embodiment of the present invention.
  • FIG. 9 is a perspective view showing a configuration of a conventional component-embedded substrate.
  • the present invention at least a part of the inner layer on which the active component is mounted among the plurality of wiring layers constituting the component-embedded substrate protrudes from the other wiring layer, and the wiring pattern of the inner layer is Since it is exposed, it is possible to provide a component-embedded board that can easily inspect the built-in electronic component.
  • a terminal of the wiring pattern is formed in a portion where the wiring pattern is exposed.
  • the terminal of the wiring pattern is preferably an inspection terminal.
  • the component-embedded substrate of this embodiment is a component-embedded substrate in which an electronic component (for example, a semiconductor element) is embedded.
  • the component built-in substrate is configured by laminating a plurality of wiring layers.
  • at least a part of at least one inner layer on which a built-in component (for example, a semiconductor element) is mounted protrudes from the other wiring layers among the plurality of wiring layers.
  • the terminal of the inner layer wiring pattern is exposed.
  • the built-in electronic components are inspected through the exposed wiring pattern terminals.
  • a chip component for adjusting electrical characteristics is mounted on the terminal of the wiring pattern. This facilitates inspection.
  • the active component is a semiconductor element, and the semiconductor element is preferably subjected to information writing via a terminal of the wiring pattern.
  • a gap is formed in the laminate composed of the plurality of wiring layers, and the active component is mounted on the wiring layer in which the gap is formed.
  • the plurality of wiring layers are stacked via a conductive member formed in a thickness direction of the substrate! /.
  • the inspection terminals formed on the inner layer wiring board at portions protruding from the outer edges of the upper layer wiring board and the lower layer wiring board are used. It is preferable to perform an inspection of active components mounted on the inner layer wiring board.
  • the active component mounted on the inner layer wiring board in the step (a) is a semiconductor element. Further, after the step (c), the outer edge force of the upper layer wiring board and the lower layer wiring board is also determined. Information is preferably written to the semiconductor element mounted on the inner wiring board by using electrode terminals formed on the protruding inner wiring board.
  • step (c) it is preferable that after the step (c), a step of cutting a portion of the inner layer wiring board protruding from an outer edge of the upper layer wiring board and the lower layer wiring board is performed.
  • FIG. 1 schematically shows a cross-sectional configuration of the component-embedded substrate 100 of the present embodiment.
  • FIG. 2 is an example of a top surface configuration of the component-embedded substrate 100 in the present embodiment.
  • the component-embedded substrate 100 of the present embodiment is a component-embedded substrate in which an electronic component 10 (for example, 10a, 10b) is embedded.
  • the component-embedded substrate 100 has a plurality of wiring layers ll (l la, l ib, 1 lc, l id) are stacked.
  • at least one of the inner layers (l lb, 11c) on which the built-in component (semiconductor element) 10c is mounted among the plurality of wiring layers 11, other wiring layer (11a or l id) forces also protrude.
  • the wiring pattern 13 of the inner layer (l lb, 11c) is exposed in the protruding region 50.
  • the terminal 15 of the wiring pattern is formed in the area 50 where the wiring pattern 13 is exposed.
  • the lower wiring board 11a is a multilayer wiring board.
  • a chip component for example, a chip capacitor, a chip inductor, a chip resistor
  • the semiconductor element 10a for example, a bare chip.
  • an inner wiring board l ib is laminated via an interlayer connection resin composition 12.
  • the interlayer connection resin composition 12 has a conductive via 17 formed in the sheet-shaped resin composition.
  • the second inner-layer wiring board 11c is also formed on the inner-layer wiring board ib via the interlayer connection resin composition 12.
  • the sheet-like resin composition constituting the interlayer connection resin composition 12 for example, a composite material composed of an inorganic filler and a resin can be used.
  • the conductive via (interlayer electrical connection member) 17 is made of, for example, a conductive paste.
  • An upper layer wiring board id is laminated on the inner layer wiring board 11c via an interlayer connection resin composition 12.
  • An electronic component 20 such as the semiconductor element 20a or the chip component 2 Ob can be mounted on the upper wiring board id.
  • a semiconductor element 10c which is an active component, is mounted on the inner layer wiring board ib or 11c.
  • the semiconductor element 10c is electrically connected to the terminal (land) 13a of the wiring pattern 13 formed on the inner layer wiring boards llb and 11c. Note that chip components other than the semiconductor element 10c can be mounted on the inner wiring boards llb and 11c.
  • Inner layer wiring board l lb, 11c is, for example, glass woven fabric impregnated epoxy resin, aramid nonwoven fabric impregnated epoxy resin, polyimide resin, liquid crystal polymer resin, polyetheretherketone resin (PEEK), polyphenylene oxide resin (PPO), polyphenylene ether resin (PPE), or bismaleimide 'tri It is composed of azine resin (BT) and fluorine resin.
  • a double-sided wiring board is used as the inner layer wiring boards ib, 11c, and the wiring pattern 13 also has, for example, copper power.
  • the upper wiring board l id is the same as the inner wiring boards l lb and 11c.
  • the inner wiring board l ib or 11c is formed so as to protrude from the lower wiring board l la and the upper wiring board 11d.
  • the wiring pattern 13 extends, and terminals 15 of the wiring pattern 13 are formed there.
  • the terminal 15 functions as an inspection terminal, for example, and the terminal 15 can be used to inspect the connection state of the semiconductor element 10c mounted on the inner layer wiring boards llb and 11c.
  • an electronic component (for example, a chip component) 30 for adjusting electrical characteristics can be mounted on the terminal 15 of the wiring pattern 13, or the wiring pattern 13 in the protruding region 50 is trimmed.
  • the characteristic adjustment here means adjustment of an electrical constant, for example, matching of characteristic impedance.
  • a built-in component (semiconductor element). At least one of the inner layers l lb and 11c on which 10c is mounted protrudes from the other wiring layers (l la and l id), so that the wiring pattern 13 of the inner layer (l lb and 11c) is exposed in the region 50. ing. Therefore, it becomes easy to inspect the built-in component (semiconductor element) 1 Oc using the wiring pattern 13 located in the region 50.
  • connection inspection and the operation inspection of the built-in component 1 Oc can be easily performed. Also, adjustment after inspection is possible. After the inspection, the wiring pattern 13 located in the region 50 may be removed by cutting. Alternatively, as shown in FIG. 1, an electronic component 30 for adjusting electrical characteristics 30 may be attached.
  • the electronic component 10 is prepared on the lower wiring board 11a and mounted thereon.
  • the electronic component 10 is, for example, a semiconductor element (such as a bare chip or a CSP (chip size package)) 10a or a chip component 10b.
  • a circuit board 14 as shown in FIG. 3B is obtained.
  • the semiconductor element 10a is a flip chip.
  • the chip component 10b is connected by solder 16.
  • FIG. 4A after preparing the sheet-like cocoon yarn and the composition 21, a through hole 22 is formed in the structure, and the structure shown in FIG. 4B is obtained. Thereafter, as shown in FIG. 4C, the through hole 22 is filled with a conductive paste to form a conductive via 17. In this way, the interlayer connection resin composition 12 to be sandwiched between the wiring boards 11 described with reference to FIGS. 5A-B is formed.
  • the sheet-like resin composition (sheet-like substrate) 21 of the present embodiment is a composite material sheet containing a resin (for example, thermosetting resin and Z or thermoplastic resin) and an inorganic filler. Is formed.
  • thermosetting resin is used as the resin. It is also possible to construct the sheet-shaped resin composition 21 solely from the thermosetting resin without substantially using an inorganic filler.
  • the thermosetting resin is, for example, epoxy resin, and when an inorganic filler is added, the inorganic filler is, for example, Al 2 O 3.
  • the sheet-like resin composition 21 including the composite material containing the inorganic filler is preferable to form the sheet-like resin composition 21 including the composite material containing the inorganic filler.
  • a lower wiring board 11a and an upper wiring board l id are prepared, and an inner layer wiring board l having a larger area than the lower wiring board 11a and the upper wiring board l id is prepared between them.
  • the inner layer wiring boards l lb and 11c protrude from the lower wiring board 11a and the upper wiring board l id by 3 to LOmm.
  • the protrusion may be a part of any one of the side surfaces as viewed from the plane, or may be the whole. In other words, when the wiring board is rectangular, there are four side faces, one of which is one or more and four or less side faces. If one side face is taken up, it may be part or all.
  • An interlayer connection resin composition 12 is interposed between the lower layer wiring board 11a, the inner layer wiring board l ib, the inner layer wiring board 11c, and the upper layer wiring board l id.
  • each wiring board (l la, l ib, l lc, l id) is laminated, as shown in FIG. 5B, the active component 10a, the chip component 10b, and the built-in component are connected to the interlayer connection resin composition 12.
  • the component-embedded substrate 100 of this embodiment is obtained by embedding 10c.
  • the conductive via 17 of the interlayer connection resin composition 12 and one of the electrodes of each wiring board (l la, l ib, l lc, l id) are connected.
  • the lamination and integration of each layer is performed by interposing a thermosetting resin and curing the thermosetting resin by heating and pressing.
  • a pressure condition of 0.1 to LOMPa is preferable in a temperature range of 120 to 250 ° C.
  • Inspection of the semiconductor element 10c embedded in the component-embedded substrate 100 can be performed using the inspection terminal 15. Thereby, a pass product and a defective product can be distinguished easily. After the inspection, the protruding region 50 may be cut. Alternatively, the electrode terminal 15 may be used to write and rewrite data in the embedded semiconductor element (for example, memory chip) 10c. That is, even after the wiring boards 11 are stacked, according to the configuration of the present embodiment, information can be written to the embedded semiconductor element 10c. For example, it is possible to debug software after design or after manufacture by this writing.
  • FIG. 6 schematically shows a configuration of a component-embedded substrate 100 of a type (non-embedded type) in which the embedded active component 10a and embedded component 10c are not embedded by the interlayer connection resin composition 12.
  • 19a and 19b are voids.
  • the non-embedded component-embedded substrate 100 shown in FIG. 6 can achieve the same effects as the embedded component-embedded substrate 100 shown in FIG. That is, the inner wiring board 11c on which the semiconductor element 10c is mounted protrudes from the other wiring boards (lla, lid), and the terminal 15 of the wiring pattern 13 located in the protruding region 50 is used. It becomes easy to inspect the built-in semiconductor element 10c. Alternatively, the effect of the present invention can also be obtained with the component-embedded substrate 100 shown in FIG. 19c and 19d are gaps. Interlayer connection resin composition 12 is electrically connected to solder balls (conductive members) that are not connected by conductive vias 17 as shown in Fig. 6. Therefore, interlayer connection is achieved.
  • FIG. 8 is a cross-sectional view schematically showing a component-embedded substrate according to still another embodiment of the present invention, and shows a shape without a protruding portion at the left end of the inner-layer wiring board ib, 11c in FIG. .
  • the protruding length on the right side of the inner layer wiring board l lb, 11c was 3 to LOmm longer than the lower layer wiring board 11a and the upper layer wiring board id.
  • the built-in semiconductor element 10c could be inspected using the terminal 15.
  • the component-embedded substrate 100 as described above is preferably used by being mounted on an electronic device.
  • the force V is suitable for use in portable electronic devices (for example, mobile phones, PDAs, etc.) that have strict restrictions on the mounting area. .
  • JP-A-10-321760 and JP-A-2004-2 examples include, for example, JP-A-10-321760 and JP-A-2004-2.
  • Rigid 'flexible board is constructed by superimposing a rigid board and a flexible board. Due to its basic configuration, it has a flexible board with a larger area than the rigid board. It does not exist to inspect electronic components. As evidence, it is not possible to cut a flexible substrate that protrudes from a rigid 'flexible substrate. This is because, when such cutting is performed, the advantages of the rigid / flexible substrate are lost, and the rigid / flexible substrate is no longer used.
  • Example 1 the component-embedded substrate (see FIGS. 1 and 2) according to Embodiment 1 described above was manufactured by the method shown in FIGS. The materials used and the detailed manufacturing method will be described with reference to Figs.
  • the lower wiring board 11a a glass-epoxy base material having a length of 30 mm, a width of 30 mm, and a thickness of 0.3 mm was used.
  • the semiconductor element 10a a silicon semiconductor element for connection test was used, in which electrodes were formed with a size of 6 mm square, a thickness of 100 / zm, and a pitch of 120 m on the periphery. A gold wire with a diameter of 25 / zm is ultrasonically bonded onto the electrode of the semiconductor element 10a. As a result, bumps were formed.
  • a bump bonder (STB-2 manufactured by Matsushita Electric Industrial Co., Ltd.) was used for bump formation.
  • a 50 ⁇ m thick epoxy resin sheet manufactured by Sony Chemical Corporation
  • a silica filler was prepared. This was cut to approximately the size of the semiconductor element 10a and temporarily bonded onto the lower wiring board 11a. After that, after aligning the electrode of the semiconductor element 10a and the electrode on the lower wiring board 1la, the semiconductor element 10a is mounted on the lower wiring board 11a, and a pressure of 3 MPa is applied with a pressure jig heated to 200 ° C. The underfill 19 was cured while applying pressure to mount the semiconductor element 10a.
  • solder paste (M705 made by Senju Metal) is printed on a predetermined electrode position of the lower wiring board 11a, and a chip having a length of 0.6 mm, a width of 0.3 mm, and a thickness of 0.2 mm is formed thereon. Part 10b was installed. Thereafter, the chip component 10b was soldered to the lower wiring board 11a with a reflow apparatus (manufactured by Matsushita Electric Works) to produce a circuit board 14 (see FIG. 3B).
  • a reflow apparatus manufactured by Matsushita Electric Works
  • inner layer wiring board l ib, 11c with length: 45mm, width: 45mm, thickness: 0.08mm and length: 30mm, width: 30mm, thickness: 0.2mm upper layer wiring board l id
  • the semiconductor element 10c and the electronic components 20a and 20b were mounted in the same way as described above.
  • a solid content containing 80% by mass of fused silica powder and 20% by mass of epoxy resin (including a curing agent) and methyl ethyl ketone (MEK) as a solvent are mixed with a planetary mixer. Kneaded. The mixing ratio (mass ratio) of the solid content and the solvent was 10: 1. This mixture was applied onto a carrier film made of polyethylene terephthalate by a doctor blade method. Thereafter, MEK was evaporated to prepare a sheet-shaped rosin composition 21 (thickness: 0.4 mm) (see FIG. 3A).
  • This sheet-shaped resin composition 21 was processed by a punching machine (manufactured by UHT) to form through holes 22 (see Fig. 4B). Then, 87% by mass of silver-coated copper powder and 13% by mass of epoxy resin (including a curing agent) were kneaded with three rolls to prepare a conductive paste. The conductive paste was filled in the through-holes 22 by a printing method to produce an interlayer connection resin composition 12 having a conductive via 17 (conductive paste) as shown in FIG. 4C.
  • FIG. 5A Next, as shown in FIG. 5A, four circuit boards and three interlayer connection resin compositions 12 were alternately laminated, and a mold was used at a temperature of 200 ° C and a pressure of 3 MPa. Heat for 15 minutes under pressure
  • the conductive vias (conductive paste) 17 are cured to form via conductors, and the circuit boards 11 are electrically connected to produce a component built-in board 100 as shown in FIG. 5B. .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

L'invention concerne une pluralité de couches de câblage qui sont empilées dans un substrat (100) comportant des composants intégrés. Parmi les couches de câblage (11), au moins une des couches intérieures (11b, 11c) sur laquelle est monté un composant actif (10c) dépasse des autres couches de câblage (11a, 11d) sur au moins une section de plan du substrat (100), et un motif de câblage (13) des couches intérieures (11b, 11c) est exposé. Ainsi, le composant électronique intégré du substrat peut être inspecté facilement.
PCT/JP2006/316833 2005-09-28 2006-08-28 Substrat avec composant intégré et procédé de fabrication d'un tel substrat WO2007037086A1 (fr)

Applications Claiming Priority (2)

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JP2005-281760 2005-09-28
JP2005281760A JP2008311243A (ja) 2005-09-28 2005-09-28 部品内蔵基板、部品内蔵基板を備えた電子機器、および、部品内蔵基板の製造方法

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
WO2009057654A1 (fr) * 2007-11-01 2009-05-07 Dai Nippon Printing Co., Ltd. Carte de câblage semi-intégrée, et procédé de fabrication pour la carte de câblage semi-intégrée
CN104106320A (zh) * 2012-02-17 2014-10-15 株式会社村田制作所 元器件内置基板
CN109041458A (zh) * 2018-09-25 2018-12-18 郑州云海信息技术有限公司 一种线路板及其制造方法

Families Citing this family (1)

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WO2013121977A1 (fr) * 2012-02-17 2013-08-22 株式会社村田製作所 Composant intégré à un substrat

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JPH04144266A (ja) * 1990-10-05 1992-05-18 Nec Corp 混成集積回路の製造方法
JPH11176987A (ja) * 1997-12-15 1999-07-02 Kyocera Corp 高周波用電力増幅器
JPH11220262A (ja) * 1997-11-25 1999-08-10 Matsushita Electric Ind Co Ltd 回路部品内蔵モジュールおよびその製造方法
JP2003218273A (ja) * 2002-01-23 2003-07-31 Ibiden Co Ltd 半導体チップ実装用回路基板とその製造方法および半導体モジュール
JP2004158545A (ja) * 2002-11-05 2004-06-03 Denso Corp 多層基板及びその製造方法

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JPH04144266A (ja) * 1990-10-05 1992-05-18 Nec Corp 混成集積回路の製造方法
JPH11220262A (ja) * 1997-11-25 1999-08-10 Matsushita Electric Ind Co Ltd 回路部品内蔵モジュールおよびその製造方法
JPH11176987A (ja) * 1997-12-15 1999-07-02 Kyocera Corp 高周波用電力増幅器
JP2003218273A (ja) * 2002-01-23 2003-07-31 Ibiden Co Ltd 半導体チップ実装用回路基板とその製造方法および半導体モジュール
JP2004158545A (ja) * 2002-11-05 2004-06-03 Denso Corp 多層基板及びその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009057654A1 (fr) * 2007-11-01 2009-05-07 Dai Nippon Printing Co., Ltd. Carte de câblage semi-intégrée, et procédé de fabrication pour la carte de câblage semi-intégrée
US8350388B2 (en) 2007-11-01 2013-01-08 Dai Nippon Printing Co., Ltd. Component built-in wiring board and manufacturing method of component built-in wiring board
US8987901B2 (en) 2007-11-01 2015-03-24 Dai Nippon Printing Co., Ltd. Component built-in wiring board and manufacturing method of component built-in wiring board
CN104106320A (zh) * 2012-02-17 2014-10-15 株式会社村田制作所 元器件内置基板
CN109041458A (zh) * 2018-09-25 2018-12-18 郑州云海信息技术有限公司 一种线路板及其制造方法

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