WO2007016823A1 - Procédé et appareil de récupération d'un signal de dérivation fondé sur le débit de fuite non entier - Google Patents

Procédé et appareil de récupération d'un signal de dérivation fondé sur le débit de fuite non entier Download PDF

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Publication number
WO2007016823A1
WO2007016823A1 PCT/CN2005/001831 CN2005001831W WO2007016823A1 WO 2007016823 A1 WO2007016823 A1 WO 2007016823A1 CN 2005001831 W CN2005001831 W CN 2005001831W WO 2007016823 A1 WO2007016823 A1 WO 2007016823A1
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Prior art keywords
signal
leak
leakage
bit
bits
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PCT/CN2005/001831
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English (en)
French (fr)
Inventor
Wei Luo
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Zte Corporation
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Priority claimed from CN2005100877086A external-priority patent/CN1855786B/zh
Application filed by Zte Corporation filed Critical Zte Corporation
Priority to CN2005800489873A priority Critical patent/CN101176302B/zh
Publication of WO2007016823A1 publication Critical patent/WO2007016823A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Definitions

  • Branch signal recovery method based on non-integer leakage rate and device thereof
  • the present invention relates to a technique for recovering a PDH (Quasi Synchronous Digital Hierarchy) signal from a VC (Virtual Container) of an SDH (Synchronous Digital Hierarchy), and more particularly to a tributary signal recovery method and implementation based on a non-integer leakage rate when smoothing a signal Device.
  • PDH Quad Synchronous Digital Hierarchy
  • VC Virtual Container
  • SDH Synchronous Digital Hierarchy
  • the PDH tributary signal (hereinafter referred to as the tributary signal) is transmitted in the SDH system, according to the standard, the PDH signal (which is regarded as the payload) needs to be adapted to the SDH virtual container VC by mapping according to a certain mapping structure.
  • the difference between the tributary signal and the standard VC rate is eliminated by the control of the mapping adjustment bit.
  • the adjustment bit indicates that the adjustment position is valid, the adjustment effective position can be loaded into the payload, and conversely, the padding bit is loaded.
  • the tributary signal is encapsulated in the VC, and the VC signal can be independently transmitted, multiplexed and cross-connected in the SDH network system, and the tributary signal is sent to the place where it needs to be reached. After arriving at the destination, the tributary signal needs to be extracted from the VC. This process is called demapping. In order to recover the uniform tributary signal from the VC, it is necessary to recover the original uniform clock signal of the tributary signal. .
  • the tributary signal Since the tributary signal has lost its clock signal when it is packaged into the VC, the clock signal of the tributary signal needs to be recovered from the demapped signal stream, but the stuffing bit and the overhead bit are removed according to the mapping frame structure, and the demapping is performed.
  • the resulting signal stream is a gapped irregular signal stream.
  • the VC of the package tributary signal is not synchronized or out of synchronization during the transmission of the SDH system due to the network itself.
  • the position of the VC will change by 1 byte or 3 bytes in the frame structure of the SDH system, resulting in the content of the actual VC in this frame having up to 8 or 24 bits. Therefore, the recovered signal stream is an irregular signal stream, and the tributary signal clock recovered from the signal stream has a large jitter value. Therefore, in demapping, reducing the jitter of the recovered signal due to the phase transition of the signal stream is a key issue in this process.
  • the change value of the information bits brought by one pointer adjustment it may be considered to save the number of bits that change the pointer adjustment first ( It may be more or less), and then release them evenly one bit at a time.
  • the whole process is equivalent to "dispersing" the concentrated phase changes into multiple smaller changes.
  • the primary torrent is first stored and then gradually leaked out, so it is called a "leakage.”
  • the unit time required to leak one bit each time is called the leak rate. After the tributary signal is processed through the leak, the signal will become evenly hooked, so that a clock signal with less jitter can be obtained.
  • the technical problem to be solved by the present invention is to provide a tributary signal recovery method based on a non-integer leakage rate, so that the processed tributary signal has better smoothness after being accurately leaked once.
  • the present invention also provides a tributary signal recovery device that can implement the method.
  • the present invention provides a branch signal recovery method based on a non-integer leakage rate, comprising the following steps:
  • the above branch signal recovery method may further have the following features: the step (d) In the middle, the initial remainder of the leak rate is the increment and the initial value, and the remainder is accumulated once every one bit leak interval.
  • the integer part of the leak rate M0 is the bit leak interval released by the next bit
  • M0+1 is the bit leak interval released by the next bit and the accumulated remainder value is subtracted to leak The number of bits T.
  • the foregoing branch signal recovery method may further have the following features: in the step (e), counting the minimum leak interval, and generating a positive or negative when the count value is equal to the bit leak interval value Leak the pulse signal and restart counting at the minimum leak interval.
  • the foregoing branch signal recovery method may further have the following features: In the step (b), the average value of all the bit numbers T of the current unit time and the previous continuous unit time is determined to determine the leak. The number of bits.
  • the above-mentioned tributary signal recovery method may further have the following features:
  • the leakage rate is directly taken out from the storage unit according to the number of bits to be leaked, and the storage unit stores all of the storage units in advance. The leak rate corresponding to the number of possible leaks.
  • the foregoing branch signal recovery method may further have the following features: when the step (e) superimposes the leakage pulse signal and the standard rate uniform pulse signal, the pulse signals of the two need to be staggered to avoid The overlap of the pulses, and in the counting of the pulses of the superimposed signals of the two, each time a standard rate signal pulse and a positive leak pulse appear, the count is incremented by one, and every time a negative leak pulse occurs, the count is decremented by one.
  • the above-mentioned branch signal recovery method may further have the following features: In order to achieve a negative leakage pulse count minus one every time, when the high-speed clock is divided, the obtained uniform pulse signal of the standard rate is at a minimum leakage interval. The number of pulses inside is one less than its standard number, if In the case of a minimum leakage interval, there is no negative leakage pulse in the superimposed signal, and the read/write address generated by the counting is further increased by one; if there is a negative leakage pulse, the read/write address generated by the counting remains unchanged.
  • the minimum leakage interval refers to a time corresponding to a signal structure segment that can be repeatedly generated in the signal stream.
  • the foregoing branch signal recovery method may further have the following features: further comprising the step (0: rewriting the read branch signal to another buffer twice by using the uniformly changed read/write address signal generated by the counting Cache, and use the read/write address signal as a phase-detection signal to recover a uniform clock, and then use the uniform clock to read the tributary signal of the secondary buffer to recover the finally needed uniform tributary signal.
  • the present invention provides a tributary signal recovery apparatus based on a non-integer leakage rate, including a level 1 buffer module for buffering the demlocated irregular branch signal and a buffer for providing an address signal to be cached.
  • a signal smoothing module for reading a branch signal, wherein the signal smoothing module further comprises an adjustment influence bit counting unit, a leak interval calculating unit, and a leakage implementing unit, wherein:
  • the adjustment affecting bit counting unit is configured to calculate a bit number ⁇ of the branch signal actually demapped in the selected unit time relative to the standard rate branch signal, and determine and output the next unit time according to the threshold value. The number of bits to leak in the interior ⁇ ;
  • the leak interval calculation unit is configured to calculate a bit leak interval and uniformly change the bit leak interval according to the integer portion ⁇ 0 and the initial remainder portion NO of the leak rate in each unit time, and the number of bits T to be leaked in the unit time is currently The bit leak interval is leaked one by one;
  • the leakage realization unit is configured to generate a leakage pulse signal that is positive and negative with respect to the number of bits to be leaked every one bit leak interval, and the leakage pulse signal has the branch
  • the uniform signal pulse rate of the signal standard rate is superimposed, and the pulse of the superimposed signal is counted up to obtain a uniformly changed read/write address signal, and the buffered branch signal is read out by the read/write address signal.
  • the branch signal recovery device may further have the following features: the adjustment influence bit counting unit further includes a sliding average sub-unit for averaging all the bit numbers T of the current unit time and the previous continuous unit time The number of bits to be leaked is obtained.
  • the branch signal recovery device may further have the following features: the leakage interval calculation unit includes a leakage rate acquisition subunit, a logic operation subunit, and a selector, where the leakage rate acquisition subunit is configured to be used according to The number of leaked bits yields a leak rate including the integer portion M0 and the initial remainder portion NO;
  • the logical operation subunit is configured to add the initial remainder portion of the leakage rate to the initial value, and accumulate the remainder portion once every one bit leakage interval, when the accumulated value ⁇ the number of bits to be leaked, the indication
  • the selector strobes the integer portion M0 of the leak rate, and when the accumulated value ⁇ the number of bits T to be leaked, instructs the selector to strobe the M0+1 value output and subtracts the accumulated remainder portion value The number of bits to be leaked T;
  • the selector is configured to select one of the M0 and M0+1 as the bit leak interval value output released as the next bit according to the indication signal of the logical operation subunit.
  • the branch signal recovery device may further have the following features: the leakage realization unit includes: a minimum leakage interval counter for counting the minimum leakage interval that has elapsed and clearing after outputting the leakage pulse signal; Comparing the count value of the minimum leak interval counter and the bit leak interval value, when the two are equal, generating a leak pulse signal that is positive and negative with the number of bits to be leaked ⁇ ; a frequency divider for the high speed clock Frequency division obtained with the said branch a uniform pulse signal of a standard rate of the road signal; a pulse counter for superimposing the uniform pulse signal and the leakage pulse signal and counting the pulse of the superimposed signal, and counting the result as a read/write address signal output of the first stage buffer module .
  • the leakage realization unit includes: a minimum leakage interval counter for counting the minimum leakage interval that has elapsed and clearing after outputting the leakage pulse signal; Comparing the count value of the minimum leak interval counter and the bit leak interval value, when the two are equal, generating a leak pulse signal that is positive
  • the branch signal recovery device may further have the following features: the leakage rate acquisition subunit includes a memory for storing an integer part M0 and an initial remainder portion of a leak rate corresponding to all possible number of bits to be leaked. The value NO is for removal.
  • branch signal recovery device may further have the following features: further comprising a second level buffer module connected to the first level buffer module, configured to buffer the readout from the first level buffer module The branch signal is read out by a uniform branch clock signal recovered by the address phase.
  • each module of the tributary signal recovery device is connected to a high-speed clock having a higher rate than the tributary signal as each module performs tributary signal smoothing processing.
  • Base clock each module of the tributary signal recovery device is connected to a high-speed clock having a higher rate than the tributary signal as each module performs tributary signal smoothing processing.
  • the apparatus and method of the present invention by processing the initial remainder portion of the leakage rate, not only the number of bits that are increased or decreased with respect to the standard rate signal after the pointer adjustment and mapping adjustment in the selected time can be leaked.
  • the leakage is more accurate, and the smoothness of the bit leak interval is ensured, so that the generated read/write address is more uniform, and the recovered branch clock signal has a smaller jitter value.
  • the device of the present invention uses pure hardware circuits to implement non-integer leakage rate calculation and leakage implementation, without the involvement of an external processor, and without circuitry to eliminate the effects of over-leakage bits.
  • DRAWINGS BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing the structure of a device in accordance with a preferred embodiment of the present invention.
  • FIG. 2 is a flow chart of a method in accordance with a preferred embodiment of the present invention.
  • the device in this embodiment includes a first-level first-in first-out buffer (FIFO1) module, a second-level first-in first-out buffer (FIF02) module, and a signal smoothing module.
  • FIFO1 first-level first-in first-out buffer
  • F02 second-level first-in first-out buffer
  • a signal smoothing module At the same time, it provides a high-speed clock with a frequency higher than the recovery tributary signal clock frequency as the basic clock of each of the above modules for smoothing the tributary signal, wherein ⁇ denotes the summing device and ⁇ denotes the comparator.
  • the first-level FIFO buffer module is configured to cache the demilitarized tributary signals, and read and write the read/write addresses generated by the signal smoothing module to perform signal smoothing.
  • the second stage FIFO buffer module is configured to buffer the tributary signal read from the first stage FIFO buffer module and read it out through the recovered uniform tributary clock signal.
  • the uniform branch clock signal is the highest bit of the uniform read/write address generated by the signal smoothing module and the highest bit signal of the read address signal generated by the recovered clock, and the external control is controlled by low-pass filtering.
  • the circuit's voltage controlled oscillator (VCXO) is recovered.
  • the signal smoothing module further includes: an adjustment influence bit counting unit, a leak interval calculation unit, and a leakage realization unit. among them:
  • the adjustment influence bit counting unit is configured to calculate the number of bits T of the branch signal actually demapped in the selected unit time relative to the standard rate branch signal, and output the next unit time to be leaked after the moving average The number of bits ⁇ .
  • the actual signal counter and the standard rate signal counter in the unit are used to calculate the actual number of effective signal bits and The number of bits of the standard rate tributary signal, after subtracting the difference, the average number of bits T of the current unit time and the previous continuous unit time is calculated by the moving average subunit to obtain the number of bits to be leaked.
  • the leak interval calculation unit is configured to take out the corresponding leak rate including the integer part ⁇ 0 and the initial remainder part NO in the memory with the number of bits to be leaked as the address, and the initial remainder part of the leak rate NO is the initial value and the increment, each pass A bit leak interval is added to the remainder portion.
  • M0+1 is output as the bit leak interval of the next bit release and the accumulated remainder value is subtracted to leak.
  • the number of bits when the accumulated remainder portion value ⁇ the number of bits to be leaked T, outputs the integer portion M0 of the leak rate as the bit leak interval released by the next bit.
  • the bit leak interval here is expressed as the number of minimum leak intervals between two leaks.
  • the leak interval calculation unit has a memory ROM in which an index relationship table corresponding to the number of bits to be leaked, an integer portion M0 of its leak rate, and an initial remainder portion NO, according to the number of bits to be leaked ⁇ You can directly take out M0 and N0, avoiding the problem of dividing the circuit directly with the circuit, and eliminating the need for an external processor to perform the leak rate calculation.
  • the processing speed of the processor is very high.
  • the comparator of the leakage realization unit outputs an indication signal to initiate the above-mentioned accumulation, comparison and subtraction when the values of the minimum leakage interval count and the bit leakage interval are equal (in the figure) Not shown).
  • the alternative selector selects one of ⁇ 0 and M0+1 as the bit leak interval value output for the next bit release based on the comparison of the accumulated value and the number of bits to be leaked.
  • the leakage realization unit is configured to output a leakage pulse signal that is consistent with the number of bits to be leaked when the bit leakage interval value and the minimum leakage interval are equal, and superimpose the standard pulse rate uniform pulse signal obtained by the frequency division. Then, the pulse of the superimposed signal is counted, and a uniformly changed read/write address is obtained, which is used for reading and writing between FIFO1 and FIF02 and address phase discrimination.
  • the leakage realization unit includes a minimum leakage interval counter for counting the minimum leak interval that has elapsed, clearing and recounting after generating a leak pulse signal, and a comparator for comparing the minimum leak interval count and the The value of the bit leakage interval, when the two are equal, generates a leakage pulse signal that is positively and negatively coincident with the number of bits to be leaked; a frequency divider for dividing the high speed clock to obtain a standard rate of the branch signal a uniform pulse signal; a pulse counter for superimposing the uniform pulse signal and the leakage pulse signal and counting the pulses of the superimposed signal, and the result of the counting is output as a read/write address between the first-stage and second-level buffer modules.
  • the minimum leak interval counter, frequency divider, and pulse counter all utilize the high speed clock as the base clock for counting and dividing.
  • the portion of the actual branch signal adjusted by the pointer adjustment and mapping with respect to the standard rate branch signal is uniformly leaked to the standard rate branch signal.
  • Step 100 De-mapping the branch signal from the VC virtual container and writing the signal to the first-level buffer module;
  • Step 110 Calculate the tributary signal that is actually demapped in each selected unit time.
  • the number of bits T increased or decreased relative to the standard rate tributary signal, which reflects the number of bit changes in a unit of time due to pointer adjustment and mapping adjustment;
  • the frequency offset allowed by the pointer adjustment is +-4.6ppm
  • the frequency offset allowed by the PDH tributary signal is +-20ppm. Therefore, regardless of the E3 or T3 signal, the number of bit changes caused by the pointer adjustment and mapping adjustment is finally caused. Within a certain range.
  • Step 120 averaging the total number of bits T of the current unit time and the previous continuous unit time to obtain the number of bits to be leaked ⁇ as the number of bits to be leaked in the next unit time; in the embodiment, 8 units are to be leaked.
  • the data calculated in the time is a moving average, and the value of the first 7 unit time is added to the value obtained by the current unit time and then divided by 8, as the number of bits to be leaked in the next unit time, thus making 8
  • the number of bit changes per unit time is equally divided, further ensuring a smoother change in the number of bits T per selected unit time.
  • Step 130 according to the number of bits to be leaked, ⁇ take out the corresponding leakage rate, including the integer part M0 and the initial remainder part NO;
  • the minimum leakage interval can be determined according to the structure of the tributary signal mapping frame, and the time corresponding to the repetitive signal structure segment in the signal stream can be used as the minimum leakage interval, for example, The time corresponding to one subframe is selected, so the leakage rate here indicates how much minimum leakage interval is required to leak one bit.
  • the signal is repeatedly transmitted in units of one subframe, and the subframe length of E3 is three times that of the T3 subframe, so the minimum leakage interval can be selected as an E3 subframe.
  • the corresponding time interval In 1/3 second, there are 8000 E3 subframes.
  • the number of minimum leakage intervals that can be transmitted per unit time is divided by the number of bits that need to be leaked.
  • the leakage rate corresponding to the ⁇ is obtained, that is, one bit needs to be leaked. How many minimum time intervals are separated, in the embodiment, the leakage rate is a subframe.
  • the value of the leak rate is not necessarily an integer, and the integer part and the remainder part should be taken at the same time for accurate leakage.
  • the present embodiment pre-stores the value of the integer portion ⁇ 0 and the initial remainder portion NO of the leak rate corresponding to the number of bits of all possible leaks in the selected unit time into the ROM storage unit.
  • the index relationship table between each of the number of bits to be leaked ⁇ and the corresponding leak rate integer part M0 and the initial remainder part NO is established.
  • the leak rate integer portion M0 and the initial remainder portion N0 can be directly taken out according to the number T to be leaked. It has been pointed out above that the number of bit changes caused by pointer adjustment and mapping adjustment is within a certain range, but in view of the sudden change in the network out of synchronization, this embodiment also appropriately expands the range of T values.
  • Step 140 In each unit time, with the initial remainder part NO as an increment and an initial value, the remainder part is accumulated once every one bit leakage interval, and when the accumulated remainder part value ⁇ the number of bits to be leaked is 7 , M0 is the bit leak interval released by the next bit, and when the accumulated remainder value ⁇ the number of bits to be leaked, M0+1 is the bit leak interval released by the next bit and the accumulated residual value is subtracted The number of bits leaked T; In the embodiment, after each (1/3 second) unit time starts, the corresponding M0, NO, and NO are taken as the initial value of the remainder of the leakage rate according to the enthalpy calculated in the previous (1/3 second).
  • Quantity, and start sub-frame accumulation count when the sub-frame count value is equal to the leak rate integer part M0, start to leak the first bit, the sub-frame count is cleared to re-count, and the remainder of the leak rate is accumulated, when accumulating
  • the next bit leak interval is taken as M0+1, and the accumulated portion of the remainder is subtracted from the number of bits to be leaked, otherwise the leakage interval is ⁇ 0.
  • the calculated bit leak interval is 12, 13, 12, 13, 12, 13, 12, 13, and the 8 bits are evenly leaked out in one unit time.
  • Step 150 When the bit leak interval is equal to the minimum leak interval count value, generate a positive or negative leak pulse signal (corresponding to an indication signal leaking one bit, and the number of bits to be leaked is a positive leak pulse, Conversely, it is a negative leakage pulse) and clears the minimum leakage interval count value, superimposes the leakage pulse signal on the uniform pulse signal with the standard rate of the branch signal, and counts the pulse of the superimposed signal every time a standard rate signal appears. Pulse and positive leakage pulse, the count is incremented by 1, and every time a negative leakage pulse occurs, the count is decremented by 1;
  • the base clock uses a high speed clock at a rate of 77.76M.
  • the standard rate tributary signal portion we need to obtain a uniform rate of standard rate pulse signal, adding one to the read and write address at each pulse effective position.
  • This standard rate pulse can be obtained by evenly dividing the high-speed clock of 77.76M. As long as the pulse is uniform, the read-write address is incremented and incremented.
  • the 77.76M clock signal there are 3240 clock cycles in one sub-frame 125 s/3
  • the standard rate tributary signal the E3 signal at the rate of 34.368 M has 1432 clocks in the same time. Cycle, the T3 signal with a rate of 44.736368M has 1864 clock cycles, which is to evenly extract 1432 or 1864 clock pulses in 3240 clock cycles. But in the example we only take 1431 and 1863 pulses, which is one less than the standard number, the reason is introduced below.
  • the calculated leakage bit is uniformly superimposed on the standard rate pulse according to the calculated leakage rate. It should be noted that the position of the positive and negative leakage pulses does not overlap with the position of the standard signal pulse. Therefore, according to the leak rate, a pulse indicating a leak is generated at the position of each bit leak. If the number of bits to be leaked is 7 ⁇ , the pulse is a positive leak pulse, and the read/write address is incremented by one at the pulse position; The number of leaked bits T is negative. The pulse is a negative leakage pulse.
  • the read/write address should be decremented by one at the pulse position, but the actual design does not directly decrement the address by one at this position. Because the subtraction of the read/write address is considered to cause the value to change back and forth, resulting in an increase in jitter. Therefore, when calculating the standard rate bit number, only 1431 pulses are taken for E3 in one subframe, T3. Take 1863 pulses, one less than the actual number, which results in a standard frequency deviation of about -700ppm, which is much larger than the range of ⁇ 20ppm. Therefore, if there is no negative time interval corresponding to each sub-frame Leak pulse, read and write address plus one, and when there is a negative leakage pulse, the read and write address remains unchanged, no need to add. This approach also achieves the goal of decrementing one count for each negative leak pulse, but is implemented in one sub-frame, not necessarily at the location of the negative leakage pulse. This solves the problem of a reduction in the number of bits caused by the negative frequency deviation.
  • Step 160 The uniformly changed signal counted by the superimposed signal is used as a read/write address, and the buffered branch signal is smoothly read and written into the second level buffer module; the accumulated read/write address is included Two parts, one is the standard rate tributary signal part, and the other is the leakage part;
  • Step 170 The uniform address signal generated by the counting is used as a phase-detecting signal to recover a uniform clock, and then the secondary clock is used to read the tributary signal of the secondary buffer to recover the final uniform tributary signal.
  • the secondary buffer can further smooth the recovered branch signal.
  • the present invention is not limited to E3, T3 rate signals, and can be used as a general method when the PDH tributary signal is recovered from SDH.
  • the present invention can also perform various transformations.
  • the sliding average of the number of bits T is not essential to the present invention, and the present invention can also be directly applied to the next without averaging the number of bits T.
  • the leakage implementing device and method for uniformly changing the read/write address based on the bit leak interval may also adopt other schemes, such as the use of the branch signal recovery based on the integer leak rate. Program.

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Description

一种基于非整数泄露率的支路信号恢复方法及其装置 技术领域
本发明涉及从 SDH (同步数字体系） 的 VC (虚容器） 中恢复出 PDH (准同步数字体系）信号的技术， 尤其涉及对信号进行平滑时基于非整数 泄露率的支路信号恢复方法及实现装置。 背景技术
在 SDH体系中传送 PDH支路信号 （以后简称支路信号） 的时候， 根 据标准， 首先需要将 PDH信号 （被看做净荷） 通过映射按一定的映射结 构适配到 SDH的虚容器 VC中，支路信号与标准 VC速率的差异经过映射 调整比特的控制来消除， 当调整比特指示调整位置有效的时候， 调整有效 位置可以装入净荷， 反之， 装入填充比特。 经过这样的适配后支路信号就 被封装在 VC中，而 VC信号能够在 SDH的网络体系里面独立地进行传送， 复用和交叉连接， 把支路信号送到需要到达的地方。 到达目的地后， 需要 将支路信号从 VC里面提取出来， 这一过程称为解映射， 而为了从 VC中 恢复出均匀的支路信号来， 就需要恢复出支路信号原来均匀的时钟信号。 而由于支路信号在封装进 VC的时候已经失去了其时钟信号， 需要从解映 射的信号流中再恢复支路信号的时钟信号，但按照映射帧结构去掉塞入比 特和开销比特， 解映射后得出的信号流是一个带缺口的不规则信号流。
而且， 支路信号在 SDH体系中传递时由于指针调整的作用， 当封装 支路信号的 VC在 SDH体系传递的过程中由于网络本身的不同步或失步 出现指针调整时， VC的位置在 SDH体系的 帧结构中会出现 1个字节或 是 3个字节的变化， 导致这一帧里实际 VC的内容有多达 8或 24个比特 的变化， 因此恢复出来的信号流是一个不规则的信号流， 而根据此信号流 恢复出的支路信号时钟具有较大的抖动值。 所以在解映射时， 降低这种由 于信号流相位跃变导致恢复出来的信号抖动过大是这一过程中的一个关 键问题。
因此要降低恢复出的时钟信号的抖动， 就需要对恢复的信号进行平滑 处理， 对于一次指针调整带来的信息比特的变化值， 可以考虑将这些指针 调整带来变化的比特数先保存起来 （可能是多了或者少了）， 然后再将它 们一次一个比特地均匀释放。 而整个过程相当于将集中的相位变化"分散" 成多次较小的变化。 相当于水库一样， 将一次的洪流先存放起来， 然后再 逐渐慢慢泄漏出去， 因此称为"泄漏"。 每一次泄漏掉一个比特所需要的单 位时间则称之为泄漏率。 支路信号通过泄漏处理后， 信号将变得均勾， 从 而可以得到抖动较小的时钟信号。
但在现有技术对支路信号进行泄漏的处理过程中， 却存在以下缺点：
1. 对于计算出来的泄漏率取整数部分来进行泄漏平滑， 而实际上泄 漏率大多是一个非整数数值，这样使得在只用泄漏率的整数部分来泄漏积 累比特的时候， 出现泄漏次数多于需要泄漏的比特数， 不能精确泄漏的问 题。
2. 由于上一问题的存在， 现有技术中需要额外的电路来消除过泄漏 比特的影响， 增加了电路的复杂性。
3. 泄漏率的计算需要外部处理器来完成。 发明内容
本发明要解决的技术问题是提供一种基于非整数泄露率的支路信号 恢复方法， 使得处理后的支路信号经一次精确泄漏后具有更好的平滑性。 本发明还要提供」种可实现该方法的支路信号恢复装置。
为了解决上述技术问题， 本发明提供了一种基于非整数泄露率的支路 信号恢复方法， 包括以下步骤：
步骤 （a): 从虚容器中解映射出支路信号并缓存；
步骤（b ) : 计算出每一个选定的单位时间内， 实际解映射出的支路信 号相对于其标准速率支路信号所增加或减少的比特数 T， 并根据该 Τ值确 定下一个单位时间内要泄漏的比特数 ；
步骤 （c): 根据要泄漏的比特数 和所述单位时间内包含的最小泄漏 间隔数， 得到要泄漏的比特数 ^对应的泄漏率， 包括整数部分 Μ0和初始 余数部分 NO;
步骤 （d): 在每一个单位时间内， 根据泄漏率的整数部分 M0和初始 余数部分 NO 算出为最小泄漏间隔整数倍的比特泄漏间隔并使其均勾变 化， 在该单位时间内将要泄漏的比特数 T按当前的比特泄漏间隔逐一泄漏 掉；
步骤 （e): 每经过一个比特泄漏间隔产生一个与要泄漏的比特数 值 正负一致的泄漏脉冲信号，将该泄漏脉冲信号与具有所述支路信号标准速 率的均匀脉冲信号相叠加， 并对叠加信号的脉冲累加计数， 得到均匀变化 的读写地址信号， 用该读写地址信号将缓存的所述支路信号读出。
进一步地， 上述支路信号恢复方法还可具有以下特点： 所述步骤（d) 中， 是以泄漏率的初始余数部分 NO为增量和初值， 每经过一个比特泄漏 间隔对余数部分累加一次， 当该累加的值 <要泄漏的比特数 Ϊ时， 以泄漏 率的整数部分 M0为下一个比特释放的比特泄漏间隔， 而在该累加的值≥ 要泄漏的比特数 时， 以 M0+1为下一个比特释放的比特泄漏间隔并将该 累加的余数部分值减去要泄漏的比特数 T。
进一步地， 上述支路信号恢复方法还可具有以下特点： 所述步骤（e) 中， 是对所述最小泄漏间隔计数， 在计数值等于所述比特泄漏间隔值时， 产生一个正或负的泄漏脉冲信号并对最小泄漏间隔重新开始计数。
进一步地， 上述支路信号恢复方法还可具有以下特点： 所述步骤（b) 中， 是对当前单位时间和此前的连续单位时间内的所有比特数 T取均值， 来确定所述要泄漏的比特数 。
进一步地， 上述支路信号恢复方法还可具有以下特点： 所述步骤（c) 中， 所述泄漏率是根据要泄漏的比特数 Ϊ从存储单元中直接取出的， 该存 储单元预先存储了所有可能的要泄漏的比特数 所对应的泄漏率。
进一步地， 上述支路信号恢复方法还可具有以下特点： 所述步骤（e) 将所述泄漏脉冲信号和所述标准速率的均匀脉冲信号叠加时，需要将两者 的脉冲信号错开， 以避免脉冲的重叠， 且在对该两者的叠加信号的脉冲计 数时， 每出现一个标准速率信号脉冲和正泄漏脉冲， 计数加 1， 每出现一 个负泄漏脉冲， 计数减 1。
进一步地， 上述支路信号恢复方法还可具有以下特点： 为了实现每出 现一个负泄漏脉冲计数减 1， 在对高速时钟分频时， 使得到的所述标准速 率的均匀脉冲信号在最小泄漏间隔内的脉冲数比其标准数目少一个，如果 在一个最小泄漏间隔内所述叠加信号中没有负泄漏脉冲，则对计数产生的 读写地址再加 1 ; 如果有负泄漏脉冲， 则计数产生的读写地址保持不变。
进一步地， 上述支路信号恢复方法还可具有以下特点： 所述最小泄漏 间隔是指信号流中能够重复出现的信号结构段对应的时间。
进一步地， 上述支路信号恢复方法还可具有以下特点： 还包括步骤 (0： 利用所述计数产生的均匀变化的读写地址信号将读出的支路信号再 写入另一缓存器二次缓存，并将该读写地址信号作为鉴相信号以恢复出均 匀时钟， 然后用该均匀时钟读取二次缓存的支路信号， 恢复出最终需要的 均匀支路信号。
为了实现上述方法， 本发明提供了一种基于非整数泄露率的支路信号 恢复装置，包括用于缓存解映射后不规则支路信号的一级缓存器模块和用 于提供地址信号将缓存的支路信号读出的信号平滑模块， 其特征在于， 所 述信号平滑模块进一步包括调整影响比特计数单元、泄漏间隔计算单元和 泄漏实现单元， 其中：
所述调整影响比特计数单元用于计算选定单位时间内实际解映射出 的支路信号相对于标准速率支路信号增加或减少的比特数 τ， 并根据该 Τ 值确定并输出下一单位时间内要泄漏的比特数 τ；
所述泄漏间隔计算单元用于在每一个单位时间内，根据泄漏率的整数 部分 Μ0和初始余数部分 NO计算比特泄漏间隔并使其均匀变化， 在该单 位时间内将要泄漏的比特数 T按当前的比特泄漏间隔逐一泄漏掉；
所述泄漏实现单元用于每经过一个比特泄漏间隔产生一个与要泄漏 的比特数 Ϊ正负一致的泄漏脉冲信号， 将该泄漏脉冲信号与具有所述支路 信号标准速率的均勾脉冲信号相叠加， 并对叠加信号的脉冲累加计数， 得 到均匀变化的读写地址信号，用该读写地址信号将缓存的所述支路信号读 出。
进一步地， 上述支路信号恢复装置还可具有以下特点： 所述调整影响 比特计数单元还包括一个滑动平均子单元，用于对当前单位时间和此前的 连续单位时间内的所有比特数 T取均值得到所述要泄漏的比特数 Ϊ。
进一步地， 上述支路信号恢复装置还可具有以下特点： 所述泄漏间隔 计算单元包括泄漏率获取子单元、 逻辑运算子单元和选择器， 其中- 所述泄漏率获取子单元， 用于根据要泄漏的比特数 得到包括整数部 分 M0和初始余数部分 NO的泄漏率；
所述逻辑运算子单元， 用于以泄露率的初始余数部分 NO为增量和初 值， 每经过一个比特泄漏间隔对余数部分累加一次， 当该累加的值 <要泄 漏的比特数 时， 指示所述选择器选通泄漏率的整数部分 M0输出， 而在 该累加的值≥要泄漏的比特数 T时， 指示所述选择器选通 M0+1 值输出并 将该累加的余数部分值减去要泄漏的比特数 T；
所述选择器，用于根据所述逻辑运算子单元的指示信号从 M0和 M0+1 中选择一个作为下一个比特释放的比特泄漏间隔值输出。
进一步地， 上述支路信号恢复装置还可具有以下特点： 所述泄漏实现 单元包括： 最小泄漏间隔计数器， 用于对经过的最小泄漏间隔计数并在输 出泄漏脉冲信号后清零； 比较器， 用于比较所述最小泄漏间隔计数器的计 数值和所述比特泄漏间隔值， 在两者相等时产生一个与要泄漏的比特数 τ 正负一致的泄漏脉冲信号； 分频器， 用于对高速时钟分频得到具有所述支 路信号标准速率的均匀脉冲信号； 脉冲计数器， 用于将所述均匀脉冲信号 和泄漏脉冲信号叠加并对叠加信号的脉冲计数，计数结果作为所述第一级 缓存器模块的读写地址信号输出。
进一步地， 上述支路信号恢复装置还可具有以下特点： 所述泄漏率获 取子单元包括一个存储器， 用于存放所有可能的要泄漏的比特数 所对应 的泄漏率的整数部分 M0和初始余数部分值 NO供取出。
进一步地， 上述支路信号恢复装置还可具有以下特点： 还包括一个与 所述第一级缓存器模块连接的第二级缓存器模块，用于缓存从所述第一级 缓存器模块读出的支路信号，并通过地址鉴相恢复出的均匀的支路时钟信 号将其读出。
进一步地， 上述支路信号恢复装置还可具有以下特点： 该支路信号恢 复装置的各个模块均接入了一个速率高于所述支路信号的高速时钟作为 各个模块进行支路信号平滑处理的基础时钟。
由上可知， 采用本发明所述装置和方法通过对泄漏率的初始余数部分 的处理，不仅可以将选定时间内指针调整和映射调整后相对于标准速率信 号增加或减少的比特数全部泄漏掉， 使得泄漏更精确， 同时也保证了比特 泄漏间隔的平滑性， 使得产生的读写地址更均匀， 恢复出的支路时钟信号 有较小的抖动值。进一步地， 本发明所述装置采用纯硬件电路来实现非整 数泄漏率的计算和泄漏实现， 不需要外部处理器的参与， 也无需电路来消 除过泄漏比特的影响。 附图说明 图 1是本发明一较佳实施例的装置结构示意图。
图 2是本发明一较佳实施例的方法流程图。
具体实施方式
如图 1所示，本实施例所述装置包含第一级先进先出缓存器（FIFOl ) 模块， 第二级先进先出缓存器（FIF02)模块以及信号平滑模块。 同时为 其提供一个频率高于恢复支路信号时钟频率的高速时钟，作为实现支路信 号平滑处理的上述各个模块的基础时钟， 其中图中 ©表示求和装置， Θ 表示比较器。
第一级先进先出缓存器模块用于缓存解映射出的不规则的支路信号， 通过信号平滑模块产生的读写地址将其均勾地读出， 实现信号的平滑。
第二级先进先出缓存器模块用于缓存从第一级先进先出缓存器模块 读出的支路信号， 并通过恢复出的均匀支路时钟信号将其读出。如图 1所 示，该均匀的支路时钟信号是利用信号平滑模块产生的均匀的读写地址的 最高位与恢复时钟产生的读地址信号的最高位信号鉴相，通过低通滤波后 控制外部电路的压控振荡器 （VCXO)而恢复的。
信号平滑模块又包括： 调整影响比特计数单元、 泄漏间隔计算单元和 泄漏实现单元。 其中：
调整影响比特计数单元用于计算选定单位时间内实际解映射出的支 路信号相对于标准速率支路信号增加或减少的比特数 T， 对其滑动平均后 输出下一单位时间内要泄漏的比特数^。 如图 1所示， 该单元中的实际信 号计数器和标准速率信号计数器分别用于计算实际有效的信号比特数和 标准速率支路信号的比特数， 相减得到差值后， 在滑动平均计算子单元对 当前单位时间和此前的连续单位时间内的所有比特数 T取均值得到要泄 漏的比特数 ϊ。
泄漏间隔计算单元用于以要泄漏的比特数 Ϊ为地址取出存储器中对 应的包括整数部分 Μ0和初始余数部分 NO的泄漏率， 以泄漏率的初始余 数部分 NO为初值和增量，每经过一个比特泄漏间隔对余数部分累加一次， 在累加的余数部分值≥要泄漏的比特数 T时， 将 M0+1 作为下一个比特释 放的比特泄漏间隔输出并将累加的余数部分值减去要泄漏的比特数 ， 在 累加的余数部分值 <要泄漏的比特数 T时， 将泄漏率的整数部分 M0作为 下一个比特释放的比特泄漏间隔输出。这里的比特泄漏间隔是用两次泄漏 之间的最小泄漏间隔的个数表示的。
如图 1所示， 该泄漏间隔计算单元中有一个存储器 ROM， 其中存有 要泄漏的比特数 Ϊ与其泄漏率的整数部分 M0和初始余数部分 NO对应的 索引关系表，根据要泄漏的比特数 Ϊ就可以直接取出 M0和 N0，避免了直 接用电路计算除法的问题， 也无需外部处理器来进行泄漏率的运算。 当然 通过外部处理器参与计算上述要泄漏的比特数 Ϊ和比特泄漏间隔也是可 以的， 但对处理器的运算速度要求很高。
图中的求和装置 （∑)、 比较器 （∑>= ϊ ) 和减法器 （Σ -Τ ) 组成的 逻辑运算子单元分别用于完成上述余数部分的累加， 累加的余数部分值与 要泄漏的比特数 Ϊ的比较， 以及累加值与要泄漏的比特数 Τ的减法运算。 本实施例中，泄漏实现单元的比较器在最小泄漏间隔计数和比特泄漏间隔 的值相等时， 会输出一个指示信号启动上述累加、 比较和减法运算（图中 未示出）。 二选一的选择器则根据累加值和要泄漏的比特数 的比较结果 从 Μ0和 M0+1中选择一个作为下一个比特释放的比特泄漏间隔值输出。
泄漏实现单元用于在比特泄漏间隔值和最小泄漏间隔的计数值相等 时输出与要泄漏的比特数 Ϊ正负一致的泄漏脉冲信号， 并与分频后得到的 标准速率的均匀脉冲信号叠加， 然后对叠加信号的脉冲计数， 得到均匀变 化的读写地址， 用于 FIFOl和 FIF02之间的读写以及地址鉴相。
从图 1可以看出， 该泄漏实现单元包括最小泄漏间隔计数器， 用于对 经过的最小泄漏间隔计数，在产生泄漏脉冲信号后清零重新计数；比较器， 用于比较最小泄漏间隔计数和所述比特泄漏间隔的值，在两者相等时产生 一个与要泄漏的比特数 Τ正负一致的泄漏脉冲信号； 分频器， 用于对高速 时钟分频得到具有所述支路信号标准速率的均匀脉冲信号； 脉冲计数器， 用于将所述均匀脉冲信号和泄漏脉冲信号叠加并对叠加信号的脉冲计数， 计数的结果作为第一级和第二级缓存器模块之间的读写地址输出。最小泄 漏间隔计数器、分频器和脉冲计数器都利用所述的高速时钟作为计数和分 频的基础时钟。
通过上述装置， 经指针调整和映射调整的实际支路信号相对于标准速 率支路信号增加或减少的部分被均匀地泄漏到标准速率的支路信号上去。
下面将详细介绍本实施例的泄漏方法， 同时以该方法在 Ε/Τ3信号平 滑泄漏中的应用为实例加以说明。 如图 2所示， 具体包括以下步骤- 步骤 100， 从 VC虚容器中解映射出支路信号并写入第一级缓存器模 块中；
步骤 110， 计算出每一个选定的单位时间内实际解映射出的支路信号 相对于标准速率支路信号增加或减少的比特数 T， 该 Τ值反映了指针调整 和映射调整带来的在一个单位时间内的比特变化数；
实施例中， 选取 1/3秒为单位时间， 在该单位时间内根据解映射出的 数据有效指示信号累加出这段时间内实际有效的信号比特数，而对标准速 率 Ε/Τ3信号来说，在该段时间内，对于 Ε3有 34.368*125*8000/3=11456000 个 bit, T3有 44.736* 125*8000/3=14912000个 bit, 用实际有效的信号比特 数与 E3信号的 -11456000或 T3信号的 -14912000个比特值相加， 就可以 知道这段时间内实际信号比标准速率的支路信号增加或减少了多少个比 特。
根据标准， 指针调整所允许的频偏为 +-4.6ppm, PDH支路信号允许的 频偏为 +-20ppm， 因此不管是 E3或是 T3信号， 其指针调整和映射调整最 终导致的比特变化数在一定范围之内。
步骤 120， 对当前单位时间和此前的连续的单位时间内的所有比特数 T取均值得到要泄漏的比特数 Ϊ，作为下一个单位时间内要泄漏的比特数； 实施例中， 将 8个单位时间内计算出来的数据做一个滑动平均， 将前 7个单位时间的值加上当前单位时间得出的值后再除以 8， 作为下一单位 时间内要泄漏的比特数， 这样使得 8个单位时间内的比特变化数被均分， 进一步保证了每个选定的单位时间内比特数 T的变化更具平滑性。
步骤 130， 根据需要泄漏的比特数 Ϊ取出对应的泄漏率， 包括整数部 分 M0和初始余数部分 NO;
最小泄漏间隔可根据支路信号映射帧的结构来确定， 信号流中能够重 复出现的信号结构段对应的时间都可以用来作为最小泄漏间隔， 比如可以 选取一个子帧对应的时间， 因此这里的泄漏率就表示泄漏一个比特需要经 过多少最小泄漏间隔。
根据 PDH信号 E3/T3的帧结构， 可以看到信号是以一个子帧为单位 重复发送的， E3的子帧长是 T3子帧长的 3倍， 因此可选择最小泄漏间隔 为一个 E3子帧对应的时间间隔。 在 1/3秒的时间内， 有 8000个 E3子帧， 用单位时间内可传递的最小泄漏间隔数目除以需要泄漏的比特数 Ϊ就可 得到该 Ϊ对应的泄漏率， 即泄漏一个比特需要间隔多少个最小时间间隔， 实施例， 该泄露率即为子帧。 该泄漏率的值并不一定是整数， 为了精确泄 漏应同时取其整数部分和余数部分。 对 E3信号， 其泄漏率值的整数部分 为 M0=INT (8000/ ), 余数部分为 N0=MOD (8000/T )o
在介绍装置时已提到，本实施例将选定单位时间内所有可能的要泄漏 的比特数 Τ所对应的泄漏率的整数部分 Μ0和初始余数部分 NO的值都预 先存入到 ROM存储单元中， 建立每一个要泄漏的比特数 Ϊ与对应的泄漏 率整数部分 M0和初始余数部分 NO的索引关系表。 这样根据要泄漏的比 特数 T就可以直接取出泄漏率整数部分 M0和初始余数部分 N0。前面已指 出， 指针调整和映射调整最终导致的比特变化数在一定范围之内， 但考虑 到网络失步时候的突变影响， 本实施例还将 T值的范围适当扩大。
步骤 140， 在每一个单位时间内， 以初始余数部分 NO为增量和初值， 每经过一个比特泄漏间隔对余数部分累加一次， 当累加的余数部分值 <要 泄漏的比特数7 Ϊ时， 以 M0为下一个比特释放的比特泄漏间隔， 而在累加 的余数部分值≥要泄漏的比特数 Ϊ时， 以 M0+1 为下一个比特释放的比特 泄漏间隔且将累加的余数值减去要泄漏的比特数 T； 实施例中， 在每一个 （1/3秒） 单位时间开始后， 根据上一 （1/3秒） 计算出来的 Ϊ值取出相应的 M0、 NO, NO作为泄漏率余数部分的初值和增 量， 并开始子帧累加计数， 当子帧计数值等于泄漏率整数部分 M0时， 开 始泄漏掉第一个比特， 子帧计数清零重新计数， 同时累加一次泄漏率的余 数部分， 当累加的余数值大于或等于要泄漏的比特数 的时候， 取下一次 比特泄漏间隔为 M0+1， 并将余数的累加部分减去要泄漏的比特数 ϊ， 否 则取泄漏间隔为 Μ0。 下一次当子帧计数等于比特泄漏间隔时， 又泄漏掉 一个比特， 并重复上边的计算： 子帧计数清零， 累加泄漏率余数部分， 得 出下一次泄漏比特的间隔等。 如此， 直到 （1/3 秒） 单位时间完。 下一个 ( 1/3秒） 单位时间时刻开始， 又根据新的比特数 Τ值取出相应的 Μ0、 NO开始泄漏。
用另一个简单的例子来说明一下， 假定在一个单位时间内有 100个子 帧， 平滑处理后要泄漏的比特数 =8， 则泄漏率的整数部分 Μ0=12， 初始 余数部分 Ν0=4。按本实施例方法， 计算出的比特泄漏间隔依次为 12， 13, 12， 13， 12， 13， 12, 13, 从而将 8个比特在一个单位时间内均匀地泄漏 掉。
步骤 150， 当比特泄漏间隔与最小泄漏间隔计数值相等时， 产生一个 正或负的泄漏脉冲信号（相当于泄漏一个比特的指示信号， 要泄漏的比特 数 Ϊ为正时为正的泄漏脉冲， 反之为负的泄漏脉冲） 并将最小泄露间隔计 数值清零，将泄漏脉冲信号叠加到具有支路信号标准速率的均匀脉冲信号 上， 并对叠加后信号的脉冲计数， 每出现一个标准速率信号脉冲和正泄漏 脉冲， 计数加 1， 每出现一个负泄漏脉冲， 计数减 1 ; 实施例中， 基础时钟采用速率为 77.76M的高速时钟。 对于标准速率 的支路信号部分， 我们需要得到一个标准速率的均匀脉冲信号， 在每一个 脉冲有效位置对读写地址加一。 这个标准速率脉冲可以通过对 77.76M的 高速时钟均匀分频而得到,只要脉冲是均匀的，读写地址累加递增就是均勾 的。 对于 77.76M的时钟信号， 在一个子帧 125 s/3的时间内有 3240个时 钟周期， 而对于标准速率的支路信号来说， 速率 34.368M的 E3信号在相 同的时间内有 1432个时钟周期， 速率 44.736368M的 T3信号则有 1864 个时钟周期， 这就要在 3240个时钟周期中均匀取出 1432或 1864个时钟脉 冲。 但在实例中我们只取 1431和 1863个脉冲， 即比标准数目少一个， 原 因下边介绍。
在标准速率的脉冲上， 我们还要叠加上由于指针调整和映射调整使比 特数目发生变化的部分，也就是要将计算得出的泄漏比特按照计算出的泄 漏率均匀叠加到标准速率的脉冲上去，应该注意的是正负泄漏脉冲的位置 与标准信号脉冲的位置不能重叠。 因此， 根据泄漏率， 在每个比特泄漏的 位置产生泄漏指示的脉冲， 如果要泄漏的比特数7 Ϊ为正， 该脉冲为正泄漏 脉冲， 在该脉冲位置将读写地址加一； 如果要泄漏的比特数 T为负， 该脉 冲为负泄漏脉冲， 在该脉冲位置应该将读写地址减一， 但实际设计中并没 有直接在这个位置将地址减一。因为考虑到读写地址的减法运算反而会导 致其值的来回变化， 导致抖动的增加， 因此， 在计算标准速率比特数的时 候， 在一个子帧内， 对于 E3只取了 1431个脉冲， T3取 1863个脉冲， 比 实际的数目少了一个， 这样导致的标准频率偏差为大约 -700ppm， 远远大 与 ±20ppm 的范围， 因此， 对每一个子帧对应的时间间隔内， 如果没有负 泄漏脉冲， 读写地址再加一， 而在有负泄漏脉冲的时候， 读写地址保持不 变， 不加即可。 这种方式同样达到了对每出现一个负泄漏脉冲计数减 1的 目的， 只不过是在一个子帧内实现的， 而不一定是在负泄漏脉冲产生的位 置。 这样就解决了负频率偏差导致的比特数减少的问题。
步骤 160， 将对所述叠加信号计数得到的均匀变化的信号作为读写地 址， 将缓存的所述支路信号平滑读出并写入第二级缓存器模块； 该累加的 读写地址中包含了两个部分， 一个是标准速率的支路信号部分， 一个是泄 漏部分；
步骤 170， 将所述计数产生的均匀地址信号作为鉴相信号， 恢复出均 匀时钟， 然后用该均匀时钟读取二次缓存的支路信号， 恢复出最终需要的 均匀支路信号。 二次缓存可以使恢复出的支路信号进一步平滑。
很明显， 本发明并不局限于 E3， T3速率信号， 作为一个通用方法， 在 PDH支路信号从 SDH恢复的时候均可运用。 通过上述方法， 不仅可以 将选定时间内指针调整和映射调整后相对于标准速率信号增加或减少的 比特数全部泄漏掉， 同时也保证了比特泄漏间隔的平滑性， 因此用此方法 处理后恢复出的支路时钟信号有较小的抖动值。
在上述实施例的基础上， 本发明还可以做各种变换， 例如： 对比特数 T进行滑动平均并非本发明必须的，本发明也可以不对比特数 T进行取平 均值而直接应用为下一单位时间内要泄漏的比特数。
另外， 在使用外部处理器计算泄漏率、 比特泄漏间隔时， 从逻辑上也 可以将单位时间内可传递的最小泄漏间隔数目除以要泄漏的比特数 的 商的小数部分代替泄漏率的余数部分进行累加计算， 当累加值大于 1时取 下一次比特泄漏间隔为 M0+1并将累加的值减去 1， 该方案与上述实施例 的方案效果等同， 并且本实施例方法的计算更简单一些。
另外， 在得到均匀变化的比特泄漏间隔后， 基于该比特泄漏间隔得到 均匀变化的读写地址的泄漏实现装置和方法也可以采用其它的方案，如基 于整数泄漏率的支路信号恢复中采用的方案。

Claims

权 利 要 求
1. 一种基于非整数泄露率的支路信号恢复方法，其特征在于，包括以 下步骤：
步骤 （a): 从虚容器中解映射出支路信号并缓存；
步骤 （b): 计算出每一个选定的单位时间内， 实际解映射出的支路信 号相对于其标准速率支路信号所增加或减少的比特数 T， 并根据该 Τ值确 定下一个单位时间内要泄漏的比特数 . 步骤 （c): 根据要泄漏的比特数 和所述单位时间内包含的最小泄漏 间隔数， 得到要泄漏的比特数 Ϊ对应的泄漏率， 包括整数部分 Μ0和初始 余数部分 NO;
步骤 （d): 在每一个单位时间内， 根据泄漏率的整数部分 M0和初始 余数部分 NO 算出为最小泄漏间隔整数倍的比特泄漏间隔并使其均匀变 化， 在该单位时间内将要泄漏的比特数 T按当前的比特泄漏间隔逐一泄漏 掉；
步骤 （e): 每经过一个比特泄漏间隔产生一个与要泄漏的比特数 值 正负一致的泄漏脉冲信号，将该泄漏脉冲信号与具有所述支路信号标准速 率的均勾脉冲信号相叠加， 并对叠加信号的脉冲累加计数， 得到均匀变化 的读写地址信号， 用该读写地址信号将缓存的所述支路信号读出。
2. 根据权利要求 1所述的支路信号恢复方法，其特征在于，所述步骤 (d)中， 是以泄漏率的初始余数部分 NO为增量和初值， 每经过一个比特 泄漏间隔对余数部分累加一次， 当该累加的值 <要泄漏的比特数 T时， 以 泄漏率的整数部分 MO为下一个比特释放的比特泄漏间隔， 而在该累加的 值≥要泄漏的比特数 Ϊ时， 以 M0+1 为下一个比特释放的比特泄漏间隔并 将该累加的余数部分值减去要泄漏的比特数 。
3. 根据权利要求 1所述的支路信号恢复方法，其特征在于，所述步骤 (e) 中， 是对所述最小泄漏间隔计数， 在计数值等于所述比特泄漏间隔 值时， 产生一个正或负的泄漏脉冲信号并对最小泄漏间隔重新开始计数。
4. 根据权利要求 1、 2或 3所述的支路信号恢复方法， 其特征在于， 所述步骤 （b) 中， 是对当前单位时间和此前的连续单位时间内的所有比 特数 T取均值， 来确定所述要泄漏的比特数 。
5. 根据权利要求 1、 2或 3所述的支路信号恢复方法， 其特征在于， 所述步骤 （c) 中， 所述泄漏率是根据要泄漏的比特数 T从存储单元中直 接取出的， 该存储单元预先存储了所有可能的要泄漏的比特数 所对应的 泄漏率。
6. 根据权利要求 1或 3所述的支路信号恢复方法，其特征在于，所述 步骤 （e) 将所述泄漏脉冲信号和所述标准速率的均匀脉冲信号叠加时， 需要将两者的脉冲信号错开， 且在对该两者的叠加信号的脉冲计数时， 每 出现一个标准速率信号脉冲和正泄漏脉冲， 计数加 1， 每出现一个负泄漏 脉冲， 计数减 1。
7. 根据权利要求 6所述的支路信号恢复方法，其特征在于，在对高速 时钟分频时，使得到的所述标准速率的均匀脉冲信号在最小泄漏间隔内的 脉冲数比其标准数目少一个，如果在一个最小泄漏间隔内所述叠加信号中 没有负泄漏脉冲， 则对计数产生的读写地址再加 1 ; 如果有负泄漏脉冲， 则计数产生的读写地址保持不变。
8. 根据权利要求 1所述的支路信号恢复方法，其特征在于，所述最小 泄漏间隔是指信号流中能够重复出现的信号结构段对应的时间。
9. 根据权利要求 1所述的支路信号恢复方法，其特征在于，还包括步 骤 （f): 利用所述计数产生的均匀变化的读写地址信号将读出的支路信号 再写入另一缓存器二次缓存，并将该读写地址信号作为鉴相信号以恢复出 均匀时钟， 然后用该均匀时钟读取二次缓存的支路信号， 恢复出最终需要 的均匀支路信号。
10. 一种基于非整数泄露率的支路信号恢复装置， 包括用于缓存解映 射后不规则支路信号的第一级缓存器模块和用于提供地址信号将缓存的 支路信号读出的信号平滑模块， 其特征在于， 所述信号平滑模块进一步包 括调整影响比特计数单元、 泄漏间隔计算单元和泄漏实现单元， 其中： 所述调整影响比特计数单元用于计算选定单位时间内实际解映射出 的支路信号相对于标准速率支路信号增加或减少的比特数 τ， 并根据该 Τ 值确定并输出下一单位时间内要泄漏的比特数 τ ;
所述泄漏间隔计算单元用于在每一个单位时间内，根据泄漏率的整数 部分 Μ0和初始余数部分 NO计算比特泄漏间隔并使其均匀变化， 在该单 位时间内将要泄漏的比特数 Ϊ按当前的比特泄漏间隔逐一泄漏掉；
所述泄漏实现单元用于每经过一个比特泄漏间隔产生一个与要泄漏 的比特数 ^正负一致的泄漏脉冲信号， 将该泄漏脉冲信号与具有所述支路 信号标准速率的均匀脉冲信号相叠加， 并对叠加信号的脉冲累加计数， 得 到均匀变化的读写地址信号，用该读写地址信号将缓存的所述支路信号读 出。
11. 根据权利要求 10所述的支路信号恢复装置， 其特征在于，所述调 整影响比特计数单元还包括一个滑动平均子单元，用于对当前单位时间和 此前的连续单位时间内的所有比特数 τ取均值得到所述要泄漏的比特数
T。
12. 根据权利要求 10所述的支路信号恢复装置，其特征在于，所述泄 漏间隔计算单元包括泄漏率获取子单元、逻辑运算子单元和选择器，其中： 所述泄漏率获取子单元， 用于根据要泄漏的比特数 Ϊ得到包括整数部 分 M0和初始余数部分 NO的泄漏率；
所述逻辑运算子单元， 用于以泄露率的初始余数部分 NO为增量和初 值， 每经过一个比特泄漏间隔对余数部分累加一次， 当该累加的值 <要泄 漏的比特数 T时， 指示所述选择器选通泄漏率的整数部分 M0输出， 而在 该累加的值≥要泄漏的比特数 ^时， 指示所述选择器选通 M0+1 值输出并 将该累加的余数部分值减去要泄漏的比特数 ；
所述选择器，用于根据所述逻辑运算子单元的指示信号从 M0和 M0+1 中选择一个作为下一个比特释放的比特泄漏间隔值输出。
13. 根据权利要求 10所述的支路信号恢复装置，其特征在于，所述泄 漏实现单元包括： 最小泄漏间隔计数器， 用于对经过的最小泄漏间隔计数 并在输出泄漏脉冲信号后清零； 比较器， 用于比较所述最小泄漏间隔计数 器的计数值和所述比特泄漏间隔值，在两者相等时产生一个与要泄漏的比 特数 Ϊ正负一致的泄漏脉冲信号； 分频器， 用于对高速时钟分频得到具有 所述支路信号标准速率的均匀脉冲信号； 脉冲计数器， 用于将所述均匀脉 冲信号和泄漏脉冲信号叠加并对叠加信号的脉冲计数，计数结果作为所述 第一级缓存器模块的读写地址信号输出。
14. 根据权利要求 12所述的支路信号恢复装置，其特征在于，所述泄 漏率获取子单元包括一个存储器， 用于存放所有可能的要泄漏的比特数 Ϊ 所对应的泄漏率的整数部分 M0和初始余数部分值 NO供取出。
15. 根据权利要求 10、 11、 12或 13所述的支路信号恢复装置， 其特 征在于， 还包括一个与所述第一级缓存器模块连接的第二级缓存器模块， 用于缓存从所述第一级缓存器模块读出的支路信号，并通过地址鉴相恢复 出的均匀的支路时钟信号将其读出。
16. 根据权利要求 10、 11、 12或 13所述的支路信号恢复装置， 其特 征在于，该支路信号恢复装置的各个模块均接入了一个速率高于所述支路 信号的高速时钟作为各个模块进行支路信号平滑处理的基础时钟。
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