WO2007000111A1 - Dispositif permettant l'alignement d'une phase d'horloge entre un carte d'horloge principale et une carte d'horloge de secours et procede et carte d'horloge correspondants - Google Patents

Dispositif permettant l'alignement d'une phase d'horloge entre un carte d'horloge principale et une carte d'horloge de secours et procede et carte d'horloge correspondants Download PDF

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Publication number
WO2007000111A1
WO2007000111A1 PCT/CN2006/001474 CN2006001474W WO2007000111A1 WO 2007000111 A1 WO2007000111 A1 WO 2007000111A1 CN 2006001474 W CN2006001474 W CN 2006001474W WO 2007000111 A1 WO2007000111 A1 WO 2007000111A1
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WIPO (PCT)
Prior art keywords
phase
clock
board
clocks
standby
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PCT/CN2006/001474
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English (en)
French (fr)
Inventor
Qing Zhang
Original Assignee
Huawei Technologies Co., Ltd.
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Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2007000111A1 publication Critical patent/WO2007000111A1/zh
Priority to US11/963,052 priority Critical patent/US20080095292A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present invention relates to a clock application technology in a communication device, and in particular, to an apparatus and method for aligning clock phases of a clock of a master and a backup clock, and a clock board.
  • the clock is a key component of the communication device.
  • the performance of the clock affects the performance of the board and the entire system. Therefore, it is very important for the communication device to ensure the accuracy and stability of the performance of the communication device clock. Therefore, each communication organization, country, and operator must strictly test the performance of the device's clock before the device enters the network.
  • the performance of the clock mainly includes frequency and phase.
  • the performance of the above indicators is generally considered to include long-term stability, long-term accuracy, retention performance, phase transients, and phase discontinuities.
  • a communication device generally has two clock boards that are backed up to each other: a primary clock board and a standby clock board.
  • the main clock board provides the system clock.
  • the alternate clock board is used as a spare.
  • phase transients and phase discontinuities between the main and standby clocks are important to the system.
  • the phase transients are small and the phase continuity is maintained.
  • the phase and frequency are required to be consistent when the active and standby boards are switched. Therefore, the frequency and phase of the active and standby clock boards must be consistent during normal operation.
  • the phase is the key technology that affects the master/slave switching performance of the clock board. As the communication rate increases, the accuracy requirements of the communication equipment for the phase are getting higher and higher.
  • FIG. 1 is a schematic structural diagram of a prior art clock board, including: a reference source detection and selection module 101 for selecting a clock reference source, a phase lock module 102 for phase-locking a selected clock reference source, and a multiple The frequency converter 103, the frequency divider 104, the output control module 105, the main standby control module 106, the CPU 107, and a communication module 108 for communicating with the device main control board. among them, the output phase alignment method is as follows: the signal phase-locked by the phase-locked module 102 is output to the frequency multiplier 103 to a higher frequency, and then the frequency divider is used. 104 performs counter division.
  • the active/standby control module 106 According to the active/standby control module 106, according to the main standby state of the board and the board, when the board is in the standby state, the phase of the standby clock board is aligned with the main clock board by clearing/setting the counter of the frequency divider 104.
  • the phase of the master/slave control module 106 controls the output control module 105 to output a clock signal when the board is in the active state.
  • the output signal needs to pass multiple stages of frequency multiplication/frequency division, which increases the phase noise, increases the jitter of the output signal, affects the signal quality, occupies a large amount of logic resources, and requires high logic circuit speed; Phase alignment accuracy is low, for example using a high frequency 100MHz count clock with a phase accuracy of 10.0ns.
  • an object of the present invention is to provide an apparatus and method for aligning the clocks of the clocks of the active and standby clocks, and a clock board, so that the phase alignment accuracy of the active and standby clock boards is high.
  • the present invention provides a device for aligning the clock phases of the active and standby clock boards, the device comprising:
  • a direct digital synthesis device for adjusting the phase of the output clock of the board according to the value of its internal phase register
  • phase detecting module configured to detect a phase difference between the output clock of the board and the clock of the board
  • central processing unit configured to calculate a value of the phase register in the direct digital synthesizing device according to the phase difference detected by the phase detecting module, and send the value directly to Digital synthesis device.
  • the device may further include: a phase lock module configured to perform phase lock adjustment according to a reference clock of the clock board, and output the phase locked clock to the direct digital synthesizing device.
  • a phase lock module configured to perform phase lock adjustment according to a reference clock of the clock board, and output the phase locked clock to the direct digital synthesizing device.
  • the direct digital synthesis device includes: a phase register, a phase-amplitude converter, and Digital to analog converter;
  • the central processing unit writes the calculated value of the phase register in the direct digital synthesis device to the phase register;
  • the phase register generates a phase parameter according to the received phase-locked clock and sends it to the phase "explosive amplitude converter;
  • the amplitude parameter is generated and sent to the digital-to-analog converter; the digital-to-analog converter generates the phase-modulated clock output according to the amplitude parameter and the received phase-locked clock.
  • the central processing unit is coupled to the direct digital synthesizer via a data bus and an address bus.
  • the invention also provides a method for aligning the clocks of the clocks of the active and standby clocks, including: When the clock board is the standby clock board, the steps are as follows:
  • a direct digital synthesis device is used to adjust the phase of the clock output clock to be aligned with the output clock of the main clock board.
  • the step B described may include:
  • the direct digital synthesis device adjusts the phase of the output clock of the clock board to be phase-aligned with the output clock of the main clock board according to the value of its phase register.
  • the step A may be: detecting whether the clock outputted by the clock board is ahead or behind the clock outputted by the board;
  • the step B1 is: determining the direction of the phase adjustment according to whether the detection result is lead or lag according to the step A, and determining that the value of the phase register of the direct digital synthesizing device is the sum of the value of the original phase register and the predetermined step size.
  • the method may further comprise: determining whether it is necessary to continue to adjust the phase, and if so, returning to step A, otherwise ending the adjustment.
  • the method for determining whether it is necessary to continue to adjust the phase may be:
  • the step B 1 may further include:
  • the step size of the direction is adjusted to an integral multiple of the predetermined step size.
  • the phase detection module can be used to detect the phase difference between the clock outputted by the clock board and the clock outputted to the board, and the output clock of the clock board is delayed by the high level when the output clock lags behind the board clock, otherwise the output is low.
  • the method may further include: before the clock of the clock board is input to the direct digital synthesizing device, the clock signal of the clock board is further processed by the phase lock module.
  • the invention also provides a clock single board, comprising a central processing unit, a phase lock module, a main standby control module, and a direct digital synthesis device and a phase detection module;
  • the direct digital synthesizing device is configured to receive a phase locked clock sent by the pin phase module, adjust a phase of the clock according to a value of the internal phase register, and output the clock;
  • the phase detecting module is configured to detect a phase difference between a local clock of the direct digital synthesis device and a clock of the board;
  • the central processing unit is configured to calculate a value of a phase register in the direct digital synthesizing device according to a phase difference detected by the phase detecting module according to a phase difference detected by the phase detecting module according to a primary standby state of the pair of boards sent by the primary standby control module.
  • the clock board further includes an output control module; the output control module receives the direct digital combination
  • the board clock outputted by the device is outputted according to the control command sent by the main standby control module.
  • the board clock is output.
  • the clock board further includes a reference source detection and selection module.
  • the reference source detection and selection module detects and selects multiple input reference clocks, selects the same clock reference source as the opposite board, and outputs the same to the phase lock module.
  • the direct digital synthesizer is used to adjust the phase of the standby clock based on the detection result of the main clock, thereby achieving the purpose of alignment of the active and standby phases.
  • the accuracy of phase alignment of the active and standby clock boards can be increased to Ins or higher; the phase accuracy of aligning the active and standby clock boards is increased by 10 times or more than the existing technology. Therefore, the technical indicators of the clocks such as the phase discontinuity can be greatly improved.
  • the service equipment such as a switch, a base station controller, etc.
  • the cause of the switching between the active and standby clock boards can be eliminated according to the present invention.
  • the problem of broken links caused by misalignment of the clock phase or long alignment accuracy greatly improves the reliability of the device.
  • FIG. 1 is a schematic structural diagram of a clock board of the prior art
  • FIG. 2 is a schematic structural diagram of an embodiment of a clock board according to the present invention.
  • FIG. 3 is a functional block diagram of a DDS in the embodiment shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a phase detecting module in the embodiment shown in FIG. 2;
  • FIG. 5 is a flow chart of an embodiment of a method for phase alignment of a master and backup clock board of the present invention. MODE FOR CARRYING OUT THE INVENTION
  • Apparatus and method for aligning clock phases of main and standby clock boards provided by the present invention
  • the clock board adopts a direct digital synthesizer (DDS) to adjust the phase of the standby clock according to the detection result of the main clock, thereby achieving the purpose of alignment of the active and standby phases.
  • DDS direct digital synthesizer
  • FIG. 2 is a schematic structural diagram of an embodiment of a clock board according to the present invention.
  • the clock board includes: a reference source detection and selection module 201, a phase lock module 202 that locks the selected clock reference source, an output control module 204, a primary backup control module 208, a CPU 205, and a device master.
  • the reference source detection and selection module 201 detects and selects the input plurality of reference clocks under the control of the CPU 205, selects the same clock reference source as the pair of boards, and outputs the same to the phase lock module 202.
  • the pair of boards described herein refers to another clock board that has an active/standby relationship with the board.
  • the reference source detection and selection module 201 selects the same clock reference source as the board to ensure that the clock frequencies output by the active and standby boards are the same.
  • the phase lock module 202 receives the reference clock source output by the reference source detection and selection module 201 under the control of the CPU 205, performs phase lock processing on the reference source clock source, and outputs the phase locked clock to the DDS 203. Since the reference source detection and selection module 201 of the active and standby clock boards selects the same reference clock input, the reference clocks can be phase-locked by the respective phase-locked modules 203 to obtain the phase-locked clocks having substantially the same frequency.
  • the DDS 203 is used to adjust the phase of the clock board.
  • DDS devices such as the AD7008 and AD9852 have phase modulation.
  • the phase-locked clock outputted by the phase-locked module 202 receives the phase-locked clock according to the value of the phase register sent by the CPU 205, and outputs the phase-locked clock to the output control module 204. At the same time, the phase adjustment clock is output to the phase detecting module 206.
  • FIG. 3 is a functional block diagram of the DDS in the embodiment shown in FIG. 2.
  • the DDS 203 in this embodiment is connected to the CPU 205 through a data line and an address line by using a commonly used DDS device, and specifically includes: an accumulator 301, a phase register 302, and a phase oscillation. Amplitude converter 303 and digital to analog converter 304.
  • a DDS device is a device that can both adjust the frequency and adjust the phase.
  • 24 or 48 bits of data are stored in a frequency register (not shown in Figure 3) to determine the output frequency; 14 or 16 bits of data are stored in the phase register 302. Medium, used to determine the output phase.
  • the CPU 205 outputs fixed 24 or 48-bit data to the accumulator 301, and writes 14 or 16-bit data for determining the output phase to the phase register 302.
  • the accumulator 301 accumulates 24 or 48 bits of data and 14 or 16 bits of data to the phase register 302.
  • the phase register 302 generates a phase parameter for transmission to the phase-amplitude converter 303 based on the accumulated value and the received phase-locked clock.
  • the amplitude parameter is generated and sent to the digital-to-analog converter 304.
  • the digital-to-analog converter 304 generates a phase-modulated clock output to the output control module 204 based on the amplitude parameter and the received phase-locked clock.
  • the CPU 205 transmitting the value of the different phase register to the DDS 203, that is, 14 or 16 bits of data, to change the value of the phase register 302, the phase of the output signal of the DDS can be directly adjusted without changing the value of the DDS frequency register. Adjust the output phase directly without changing the output frequency.
  • the phase detection module 206 is used to detect whether the board is advanced or delayed compared to the phase of the board. This module can be implemented by logic devices. It receives the clock output from the DDS 202 and the clock received from the board, performs phase comparison on the two clocks, and outputs the phase detection result to the CPU system 205.
  • FIG. 4 is a schematic diagram of a phase detecting module in the embodiment shown in FIG. 2.
  • Rstn is the reset terminal
  • CLK_ME is the clock outputted by the board
  • CLK_AN is the clock outputted to the board
  • PHASE_ERR is the phase detection result
  • the phase lag can be represented by "1", and the phase is "0".
  • Advance. Phase detection module implementation principle When the rising edge of the board clock comes, monitor whether the board is high or level. If it is high, it means phase lag, if it is low, it means phase lead.
  • the output control module 204 of FIG. 2 controls the output or non-output of the clock signal received from the DDS 202 based on the control signal output by the primary standby control module 208.
  • the main standby control module 208 receives the active/standby status signal sent by the board under the control of the CPU 205, and sends a control signal for outputting the clock to the output control module 204 when the board is in the standby state, that is, when the board is in the active state; When the board is in the standby state, a control signal for stopping the output clock is sent to the output control module 204, and the main standby state of the board is sent to the CPU 205.
  • the CPU 205 controls the DDS 203 to perform phase modulation according to the main standby state of the board sent by the master/slave control module 208 when the board is in the active state, that is, when the board is in the standby state, and controls the DDS 203 when the board is in the active state. Stop phasing. Specifically, when the board is in the standby state, the CPU 205 determines the direction of the DDS phase adjustment according to the result of the phase detection module 206, that is, whether it is ahead or behind the main clock, and calculates the adjusted phase information. That is, 14 or 16 bits of data are sent to the phase register of the DDS 203.
  • the phase lock module 202, the DDS module 203, the CPU 205, and the phase detecting module 206 constitute a device for aligning the phases of the active and standby clock boards, wherein the phase lock module 202 is a preliminary adjustment of the reference clock.
  • the phase-locked module may not be included.
  • the communication module 207 in FIG. 2 is the same as the prior art. Under the control of the CPU 205, it is mainly responsible for communication with the main control board on the device where the clock board is located, including data configuration, status query, and Reporting of alarms, etc.
  • FIG. 5 and FIG. 5 a flow chart of an embodiment of a method for phase-aligning the active and standby clock boards of the present invention is shown. The process includes the following steps:
  • Step 501 The phase lock module periodically adjusts an output clock of the clock board, so that the frequency of the two standby clock boards is consistent after the pin phase is passed.
  • Step 502 Input the phase locked clock into the DDS.
  • Step 503 Determine whether the clock board is standby. If yes, go to step 504, otherwise go to step 507.
  • This step can be determined by the active/standby status of the board sent by the primary standby control board.
  • the board is in the active state, the board is in the standby state.
  • Step 504 When the clock board is a standby clock board, the phase detecting module detects a phase difference between the board and the clock (same frequency) outputted by the board, that is, detecting whether the board clock is ahead or behind the board clock. Then, step 504 is performed; when the clock board is used as the main unit, step 504 is not performed, that is, the DDS is not adjusted.
  • Step 504 Determine a direction of phase modulation according to a phase difference detected by the phase detecting module. If the phase detection module phase detection module detects that the current local clock phase leads the primary clock, it determines that the phase adjustment direction is backward; conversely, if the current local clock phase lags behind the primary clock, the phase adjustment direction is determined. It is forward.
  • Step 505 Calculate the adjusted phase information, that is, 14 or 16 bits of data according to the determined phase adjustment direction and the predetermined step size, and send the data to the phase register of the DDS.
  • phase value of the current phase register can be subtracted from the predetermined step size to obtain the adjusted phase information; if it is determined that the direction of the phase adjustment is backward, the current phase register can be used. The phase value is added to the predetermined step size to obtain the adjusted phase information.
  • the accuracy of the phase alignment of the active and standby clock boards depends on the number of bits in the device phase register of the DDS and the output clock frequency of the DDS.
  • the alignment accuracy is: l/(fout*2N), fout ⁇ shows the output frequency of the DDS, and ⁇ is the number of bits of the phase register of the DDS device; this is the theoretically the highest precision and
  • the predetermined step size can be set to the minimum step size calculated by the above method.
  • Step 506 the DDS adjusts the clock output of the board according to the value of the phase register, so that the output clock of the standby clock board is aligned with the phase of the main clock board.
  • Step 507 Determine whether the phase is to be adjusted. If yes, return to step 503; otherwise, stop adjusting the DDS.
  • the CPU can calculate the probability of outputting high or low level and the ratio of lead and lag according to the number of times of recording by counting the number of advances or lags, adjusting the step size according to the calculated probability, and predicting the lead and lag.
  • the ratio determines whether the phase needs to continue to adjust.
  • the phase register of the DDS can be adjusted in different steps according to the phase error. For example, when it is found that the lag is always, for example, when the output of the phase detecting module is detected 10 times, it is found that the level is higher than or equal to 7 times, that is, the probability that the phase detecting module outputs a high level is close to 1; or advanced, such as When the output of the phase detection module is detected 10 times, it is found that when the level is higher than or equal to 7 times, that is, when the probability that the phase detection module outputs a low level is close to 1, a larger adjustment step size, such as 10 times the minimum step size, is adopted.
  • the probability that the detection module outputs a high level is close to 0.5, it indicates that the phase is basically aligned, and the step size should be adjusted less, such as using the minimum step size; when the ratio of lead and lag is close to 50%, for example, at 43 In the range of % ⁇ 67 %, the CPU determines that the phase is aligned, and there is no need to adjust the DDS. In this case, continue to check the phase difference between the board and the board clock. When the CPU calculates that the lead and lag ratios are greater than or less than 50%, such as less than 43% or greater than 67%, the phase adjustment is continued.
  • the phase-locking process and the master-slave alignment process not only ensure that the frequency and phase of the clock of the final output of the master and backup clocks are consistent, but also that the clocks of the master and standby clock plates are phase-aligned.
  • the accuracy is increased to the order of Ins or higher; the phase accuracy of the active-standby alignment is increased by 10 times or more than the prior art. Therefore, the technical indicators of the clock, such as the phase discontinuity, can be greatly improved.
  • the active/standby clock board can be eliminated according to the present invention. When switching, the reliability of the device is greatly improved due to problems such as unaligned clock phases or long alignment accuracy.

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Description

使主备时钟单板时钟相位对齐的装置及方法和时钟单板 技术领域
本发明涉及通信设备中的时钟应用技术， 尤其涉及一种使主备时钟 单板时钟相位对齐的装置及方法和时钟单板。 发明背景
时钟是通信设备的关键部件， 时钟的各项性能会影响单板乃至整个 系统的性能。 所以保证通信设备时钟各项性能的准确性和稳定性对于通 信设备来说是非常重要的。 因此各个通信組织， 国家以及运营商在设备 入网前， 都要对设备的时钟各项性能进行严格的测试。 时钟的性能指标 主要包括频率和相位， 通常考察上述指标的性能包括长期稳定度、 长期 准确度、 保持性能、 相位瞬变和相位不连续性等。
通信设备一般有两块互相备份的时钟单板： 主用时钟板和备用时钟 板。 主用时钟板提供系统时钟。 备用时钟板用作备用。 当在主备两块时 钟板之间进行倒换时， 主备用时钟之间存在相位瞬变、 相位不连续性， 上述两个指标对系统来说很重要。 为了使主备用时钟倒换时， 相位瞬变 小， 保持相位连续性， 就要求主备单板倒换时保持相位和频率的一致， 进而要求在正常运行时保证主备时钟板频率和相位保持一致。 在主备时 钟板的频率和相位两个指标中， 相位是影响时钟板主备倒换性能的关键 技术。 随着通信速率的提高， 通信设备对相位的精度要求越来越高。
参见图 1 , 图 1为现有技术的时钟板的结构示意图， 包括： 用于选择 时钟参考源的参考源检测与选择模块 101、 对选择的时钟参考源进行锁 相的锁相模块 102、 倍频器 103、 分频器 104、 输出控制模块 105、 主备用 控制模块 106、 CPU 107和用于与设备主控板通信的通信模块 108。 其中， 为了保证主备板频率和相位保持一致， 采用的输出相位对齐的方法是： 将经过锁相模块 102锁相的信号输出给倍频器 103倍频到一个较高频率， 然后再利用分频器 104进行计数器分频。 由主备控制模块 106根据本板和 对板的主备用状态， 在本板处于备用状态时， 通过清零 /置位分频器 104 的计数器来使备用时钟板的相位对齐于主用时钟板的相位； 主备控制模 块 106在本板处于主用状态时， 控制输出控制模块 105输出时钟信号。
然而， 这种方法有如下缺点： 输出信号需要经过多级倍频 /分频， 增 加了相位噪声， 使输出信号抖动增大， 影响信号质量； 占用大量逻辑资 源， 且对逻辑电路速度要求高； 相位对齐精度较低， 例如使用高频 100MHz计数时钟， 其相位精度为 10.0ns。
发明内容 针对现有技术的上述缺陷， 本发明的目的是提供一种使主备时钟单 板时钟相位对齐的装置和方法及时钟单板， 从而使主备时钟单板相位对 齐精度较高。
为达到上述目的， 本发明提供了一种使主备时钟单板时钟相位对齐 的装置， 该装置包含：
直接数字合成器件， 用于根据其内部相位寄存器的值调整本板输出 时钟的相位；
相位检测模块， 用于检测本板输出时钟与对板时钟之间的相位差； 中央处理单元， 用于根据相位检测模块所检测的相位差计算直接数 字合成器件中的相位寄存器的值发送给直接数字合成器件。
所述的装置还可以包括： 锁相模块， 用于根据时钟板的参考时钟进 行锁相调整， 并将锁相后的时钟输出给直接数字合成器件。
所述的直接数字合成器件包含： 相位寄存器、 相位-振幅转换器和 数 /模转换器；
所述中央处理单元将计算出的直接数字合成器件中的相位寄存器 的值写入相位寄存器；
相位寄存器根据接收的锁相后时钟， 生成相位参数发送给相位" 暴 幅转换器；
相位一振幅转换器进行转换处理后 ,生成幅度参数发送给数 /模转换 器； 数 /模转换器根据幅度参数和接收的锁相后时钟， 生成调相后的时钟 输出。
所述的中央处理单元通过数据总线和地址总线与直接数字合成器 件相连。
本发明还提供了一种使主备时钟单板时钟相位对齐的方法， 包括： 当本时钟板为备用时钟板时， 执行步骤：
A、 检测本时钟板输出的时钟与对板输出的时钟的相位差；
B、 根据检测的相位差， 采用直接数字合成器件， 将本时钟板输出 时钟的相位调整为与主用时钟板输出时钟相位对齐。
所述的步骤 B可以包括：
Bl、 根据检测的相位差， 计算直接数字合成器件的相位寄存器的值 发送给直接数字合成器件；
B2、 直接数字合成器件根据其相位寄存器的值， 将本时钟板输出时 钟的相位调整为与主用时钟板输出时钟相位对齐。
所述步驟 A可以为： 检测本时钟板输出的时钟与对板输出的时钟相 比是超前还是滞后；
所述步骤 B1为： 根据步骤 A检测结果是超前还是滞后确定相位调节 的方向， 并确定直接数字合成器件的相位寄存器的值为原相位寄存器的 值与预定步长的和 /差。 该方法可以进一步包括： 判断是否需要继续调整相位， 如果是， 则 返回执行步骤 A, 否则结束调整。
所述判断是否需要继续调整相位的方法可以为：
记录向前或向后相位调整的次数， 当一个方向相对另一个方向调整 次数的比例值接近 50 %时， 例如比例值在 43 % ~ 67 %范围中时， 则不需 要继续调整相位。
所述的步骤 B 1可以进一步包括：
当一个方向相对另一个方向调整次数的比例值大于预定比例时， 则 将该方向的步长调整为预定步长的整数倍。
可以采用相位检测模块来检测本时钟板输出的时钟与对板输出的 时钟的相位差， 其在本时钟板输出时钟滞后于对板时钟时输出的高电 平， 否则输出低电平。
所述的方法还可以包括： 当本时钟板的时钟输入到直接数字合成器 件之前， 本时钟板的时钟信号还经过锁相模块进行处理。
本发明还提供了一种时钟单板， 包含中央处理单元、 锁相模块、 主 备用控制模块， 还包含直接数字合成器件和相位检测模块；
所述直接数字合成器件， 用于接收销相模块发送的锁相后时钟， 根 据其内部相位寄存器的值调整该时钟的相位并输出；
所述相位检测模块， 用于检测直接数字合成器件输出的本板时钟与 对板时钟之间的相位差；
所述中央处理单元， 用于根据主备用控制模块发送的对板的主备用 状态， 在本板处于备用状态下， 根据相位检测模块所检测的相位差计算 直接数字合成器件中的相位寄存器的值发送给直接数字合成器件； 在本 板处于主用状态下， 控制直接数字合成器件停止相位调整。
该时钟单板还包含输出控制模块； 该输出控制模块接收直接数字合 成器件输出的本板时钟， 根据主备用控制模块发送的控制命令， 在本板 处于主用状态下， 输出本板时钟。
该时钟单板还包含参考源检测与选择模块 , 该参考源检测与选择模 块对输入的多个参考时钟进行检测和选择， 选择出与对板相同的时钟参 考源， 输出给锁相模块。
本发明中， 采用直接数字合成器（DDS )根据对主用时钟的检测结 果， 来调整备用时钟的相位， 从而达到主备相位对齐的目的。 可将主备 时钟板相位对齐的精度提高到 Ins量级或更高；较现有的技术将主备时钟 板对齐的相位精度提高了 10倍或 100倍以上。 因此， 可以大大改善相位 不连续性等时钟的各项技术指标； 另外， 在需要高精度时钟的业务设备 (如交换机、 基站控制器等） 中， 根据本发明可消除主备时钟板倒换时 因时钟相位不对齐或对齐精度较长带来的断链等问题， 从而大大提高了 设备的可靠性。 附图简要说明
图 1为现有技术的时钟单板的结构示意图；
图 2为本发明的时钟单板的实施例的结构示意图；
图 3为图 2所示实施例中 DDS的功能框图；
图 4为图 2所示实施例中相位检测模块的示意图；
图 5本发明的主备时钟板相位对齐的方法的实施例流程图。 实施本发明的方式 为了便于本领域一般技术人员理解和实现本发明， 现结合附图描绘 本发明的实施例。
本发明提供的这种使主备时钟单板的时钟相位对齐的装置及方法 和时钟单板， 采用直接数字合成器（DDS ) , 根据对主用时钟的检测结 果来调整备用时钟的相位， 从而达到主备相位对齐的目的。
参见图 2， 图 2为本发明的时钟单板的实施例的结构示意图。 该时钟 单板， 除了包含： 参考源检测与选择模块 201、 对选择的时钟参考源进 行锁相的锁相模块 202、输出控制模块 204、主备用控制模块 208、 CPU 205 和用于与设备主控板通信的通信模块 207。还包含了： DDS 203和相位检 测模块 206。
参考源检测与选择模块 201， 在 CPU 205的控制下， 对输入的多个参 考时钟进行检测和选择， 选择出与对板相同的时钟参考源， 输出给锁相 模块 202。 这里所述的对板， 是指与本板有主备关系的另一个时钟单板。
参考源检测与选择模块 201选择与对板相同的时钟参考源 , 是为了 保证主备板输出的时钟频率一致。
锁相模块 202,在 CPU 205的控制下，接收参考源检测与选择模块 201 输出的参考时钟源， 对参考源时钟源进行锁相处理， 并将锁相后的时钟 输出给 DDS 203。由于主备时钟板的参考源检测与选择模块 201选择了相 同的参考时钟输入， 因此参考时钟经过各自的锁相模块 203锁相后， 能 够获得频率基本相同的锁相后的时钟。
DDS 203用于调整时钟板的相位， 诸如 AD7008、 AD9852等的 DDS 器件具有相位调制功能。 其接收锁相模块 202输出的锁相后的时钟， 根 据 CPU 205发送的相位寄存器的值， 对锁相后的时钟进行相位调整， 输 出给输出控制模块 204。 同时， 该经过相位调整^时钟输出给相位检测 模块 206。
DDS 203的结构具体参见图 3， 图 3为图 2所示实施例中 DDS的功能框 图。 本实施例中的 DDS 203采用了常用的 DDS器件通过数据线和地址线 与 CPU 205相连， 其具体包含： 累加器 301、 相位寄存器 302、 相位一振 幅转换器 303和数 /模转换器 304。
DDS器件是既能调节频率也能调节相位的器件， 其中 24或 48位数据 保存在频率寄存器（图 3中未示出） 中， 用来确定输出频率； 14或 16位 数据保存在相位寄存器 302中， 用来确定输出相位。
CPU 205将固定的 24或 48位数据输出给累加器 301 ,将用于确定输出 相位的 14或 16位数据写入相位寄存器 302。 累加器 301对 24或 48位数据和 14或 16位数据进行累加输出给相位寄存器 302。 相位寄存器 302根据累加 值和接收的锁相后时钟， 生成相位参数发送给相位一振幅转换器 303。 相位一振幅转换器 303进行转换处理后， 生成幅度参数发送给数 /模转换 器 304。数 /模转换器 304根据幅度参数和接收的锁相后时钟， 生成调相后 的时钟输出给输出控制模块 204。
这样， 通过 CPU205向 DDS203发送不同的相位寄存器的值， 也就是 14或 16位数据， 来改变相位寄存器 302的值， 可以直接调节 DDS的输出 信号相位， 而不用改变 DDS频率寄存器的值， 即可以在不改变输出频率 的情况下直接调整输出相位。
相位检测模块 206用来检测本板与对板的相位相比是超前还是滞 后。 该模块可通过逻辑器件实现。 其接收 DDS 202输出的时钟和从对板 接收的时钟，对两个时钟进行相位比较，将相位检测结果输出给 CPU 系 统 205。
具体参见图 4, 图 4为图 2所示实施例中相位检测模块的示意图。 其 中， Rstn为复位端， CLK— ME为本板输出的时钟， CLK— AN为对板输出 的时钟， PHASE— ERR为相位检测结果， 可以用 "1 "表示相位滞后， "0" 表示是相位超前。相位检测模块的实现原理： 当本板时钟的上升沿来时， 监测对板是高电平还是电平。 如果是高电平表示相位滞后， 如果是低电 平表示是相位超前。 图 2中的输出控制模块 204， 根据主备用控制模块 208输出的控制信 号 , 控制从 DDS 202接收的时钟信号输出或不输出。
主备用控制模块 208在 CPU 205控制下，接收对板发送的主备状态信 号， 在对板处于备用状态， 也就是本板处于主用状态时， 向输出控制模 块 204发送输出时钟的控制信号； 在本板处于备用状态时， 向输出控制 模块 204发送停止输出时钟的控制信号， 并将对板的主备用状态发送给 CPU205,
CPU 205根据主备控制模块 208发送的对板的主备用状态 ,在对板处 于主用状态， 也就是本板处于备用状态时控制 DDS203进行调相， 在本 板处于主用状态时， 控制 DDS203停止调相。 具体来说， CPU205在本板 处于备板状态时， 根据相位检测模块 206检测的结果， 也就是相对与主 用时钟是超前还是滞后， 决定 DDS相位调整的方向， 计算出调整后的相 位信息， 也就是 14或 16位数据， 并发送给 DDS203的相位寄存器。
可见， 本实施例中， 锁相模块 202、 DDS模块 203、 CPU 205和相位 检测模块 206就构成了使主备时钟单板相位对齐的装置， 其中锁相模块 202是对参考时钟的初步调整， 在实现相位对齐时， 也可以不包含锁相 模块。
图 2中的通信模块 207与现有技术相同， 其在 CPU 205的控制下， 主 要负责和该时钟单板所在设备上的主控板之间的相互通信， 包括数据的 配置、 状态的查询和告警的上报等等。
下面介绍本发明的使主备时钟板时钟相位对齐的方法。
参见图 5 , 图 5本发明的主备时钟板相位对齐的方法的实施例流程 图。 该流程包括以下步骤：
步骤 501， 锁相模块对时钟板的输出时钟进行初步调整， 以便主备 用时钟板经过销相后， 使两者的频率保持一致。 步骤 502, 将经锁相后的时钟输入到 DDS中。
步骤 503 , 判断本时钟板是否为备用， 如果是， 则执行步骤 504, 否 则执行步骤 507。
本步骤可以通过主备用控制板发送来的对板的主备状态来确定， 当 对板处于主用状态时， 本板处于备用状态。
步驟 504， 当本时钟板为备用时钟板时， 相位检测模块检测本板与 对板输出的时钟（同频率） 的相位差， 也就是检测本板时钟与对板时钟 相比是超前还是滞后， 然后执行步骤 504; 当本时钟板为主用时， 不执 行步骤 504, 即不调节 DDS。
步骤 504, 根据相位检测模块所检测的相位差， 确定调相的方向。 如果相位检测模块相位检测模块检测到当前本板时钟相位超前于 主用时钟， 则确定调相的方向是向后； 反之， 如果当前本板时钟相位滞 后于主用时钟， 则确定调相的方向是向前。
步驟 505 , 按照确定的相位调整方向和预定步长计算出调整后的相 位信息， 也就是 14或 16位数据， 并将该数据发送给 DDS的相位寄存器。
如果确定相位调整的方向是向前， 则可以用当前相位寄存器的相位 值减去预定步长， 得出调整后的相位信息； 如果确定相位调整的方向是 向后， 则可以用当前相位寄存器的相位值加上预定步长， 得出调整后的 相位信息。
主备时钟板相位对齐的精度取决于 DDS的器件相位寄存器的位数 和 DDS的输出时钟频率。 其对齐精度为： l/(fout*2N), fout^示的是 DDS 的输出频率 ,Ν为 DDS器件的相位寄存器的位数； 这是相位对齐的精度在 理论上所能达到最高的精度和最小的调节步长。 例如： DDS输出的时钟 为 16.384MHz, DDS的相位寄存器的位数为 14, 那么调整最小步长可达： 1/(16.384* 106)/(214) =0.0038ns。 当输出频率为 2.048MHz,调整的最小步 长为 0.03ns。 通常， 预定步长可以设置为通过上述方法计算出的最小步 长。
步骤 506, DDS根据相位寄存器的值调节本板的时钟输出， 使得备 用时钟板的输出时钟和主用时钟板的相位对齐。
步骤 507, 判断相位是否还要调整， 如果是， 则返回执行步骤 503; 否则停止调整 DDS。
CPU可以通过记录超前或滞后的次数， 根据记录的次数， 计算出输 出高电平或低电平的概率以及超前和滞后的比例， 根据计算出的概率调 整步长， 并^^据超前和滞后的比例判断相位是否需要继续调整。
实际应用中， 为了快速和高精度的对齐主备时钟板的相位， 可根据 读取相位误差的情况， 采用不同的步长对 DDS的相位寄存器进行调节。 例如， 当发现一直是滞后， 如对相位检测模块的输出检测 10次时， 发现 大于等于 7次为高电平时，即，相位检测模块输出高电平的概率接近 1时； 或超前， 如对相位检测模块的输出检测 10次时， 发现大于等于 7次为低 电平时， 即， 相位检测模块输出低电平的概率接近 1时， 采用较大的调 整步长， 如最小步长的 10倍向前或向后调整； 当存在一会儿超前、 一会 儿滞后的情况， 即， 对相位检测模块的输出检测 10次时， 发现大约 6次 为高电平或大约 4次为高电平时， 即， 相位检测模块输出高电平的概率 接近 0.5时， 此时表明相位已经基本对齐了， 应该较少调整的步长， 如釆 用最小步长； 当超前和滞后的比例接近 50 %时 , 例如在 43 % ~ 67 %范围 时， CPU确定相位对齐了， 就不需要调整 DDS了。 这种情况下， 继续检 测本板和对板时钟的相位差， 当 CPU计算出超前和滞后的比例超过或小 于 50 %较大时， 例如小于 43 %或大于 67 %时， 继续进行相位调整。
根据本发明， 通过锁相处理和主备对齐处理， 不仅保证主备时钟的 最终输出的时钟的频率和相位保持一致， 而且使主备时钟板相位对齐的 精度提高到 Ins量级或更高；较现有的技术将主备对齐的相位精度提高了 10倍或 100倍以上。 因此， 可以大大改善相位不连续性等等时钟的各项 技术指标； 另夕卜， 在需要高精度时钟的业务设备， 如交换机、 基站控制 器等设备中， 根据本发明可消除主备时钟板倒换时因时钟相位不对齐或 对齐精度较长带来的断链等问题， 从而大大提高了设备的可靠性。
虽然通过实施例描绘了本发明， 但本领域普通技术人员知道， 在不 脱离本发明的精神和实质的情况下， 就可使本发明有许多变形和变化， 本发明的范围由所附的权利要求来限定。

Claims

权利要求书
1、 一种使主备时钟单板时钟相位对齐的装置， 其特征在于， 包括： 直接数字合成器件， 用于根据其内部相位寄存器的值调整本板输出 时钟的相位；
相位检测模块， 用于检测本板输出时钟与对板时钟之间的相位差； 中央处理单元 , 用于根据相位检测模块所检测的相位差计算直接数 字合成器件中的相位寄存器的值发送给直接数字合成器件。
2、 根据权利要求 1所述的使主备时钟单板时钟相位对齐的装置， 其 特征在于， 所述的装置还包括： 锁相模块， 用于根据时钟板的参考时钟 进行锁相调整， 并将锁相后的时钟输出给直接数字合成器件。
3、 根据权利要求 2所述的使主备时钟单板时钟相位对齐的装置， 其 特征在于， 所述的直接数字合成器件包含： 相位寄存器、 相位-振幅转 换器和数 /模转换器；
所述中央处理单元将计算出的直接数字合成器件中的相位寄存器 的值写入相位寄存器；
相位寄存器根据接收的锁相后时钟， 生成相位参数发送给相位一 4展 幅转换器；
相位一振幅转换器进行转换处理后，生成幅度参数发送给数 /模转换 器； 数 /模转换器根据幅度参数和接收的锁相后时钟， 生成调相后的时钟 输出。
4、 根据权利要求 1 ~ 3任一权利要求所述的使主备时钟单板时钟相 位对齐的装置， 其特征在于， 所述的中央处理单元通过数据总线和地址 总线与直接数字合成器件相连。
5、 一种使主备时钟单板时钟相位对齐的方法， 其特征在于， 包括： 当本时钟板为备用时钟板时， 执行步驟：
A、 检测本时钟板输出的时钟与对板输出的时钟的相位差；
B、 根据检测的相位差， 采用直接数字合成器件， 将本时钟板输出 时钟的相位调整为与主用时钟板输出时钟相位对齐。
6、 根据权利要求 5所述的使主备时钟单板时钟相位对齐的方法， 其 特征在于， 所述的步骤 B包括：
Bl、 根据检测的相位差， 计算直接数字合成器件的相位寄存器的值 发送给直接数字合成器件；
B2、 直接数字合成器件^ ^据其相位寄存器的值， 将本时钟板输出时 钟的相位调整为与主用时钟板输出时钟相位对齐。
7、 居权利要求 6所述的使主备时钟单板时钟相位对齐的方法， 其 特征在于， 所述步骤 A为： 检测本时钟板输出的时钟与对板输出的时钟 相比是超前还是滞后；
所述步骤 B1为： 根据步骤 A检测结果是超前还是滞后确定相位调节 的方向， 并确定直接数字合成器件的相位寄存器的值为原相位寄存器的 值与预定步长的和 /差。
8、 根据权利要求 7所述的使主备时钟单板时钟相位对齐的方法， 其特征在于， 该方法进一步包括： 判断是否需要继续调整相位， 如果是， 则返回执行步驟 A, 否则结束调整。
9、 才艮据权利要求 8所述的使主备时钟单板时钟相位对齐的方法， 其 特征在于， 所述判断是否需要继续调整相位的方法为：
记录向前或向后相位调整的次数， 当一个方向相对另一个方向调整 次数的比例值接近 50 %时， 则不需要继续调整相位。
10、 根据权利要求 9所述的使主备时钟单板时钟相位对齐的方法， 其特征在于， 所述判断是否需要继续调整相位的方法为： 记录向前或向后相位调整的次数， 当一个方向相对另一个方向调整 次数的比例值在 43 % ~ 67 %范围中时， 则不需要继续调整相位。
11、 根据权利要求 8、 9或 10所述的使主备时钟单板时钟相位对齐的 方法， 其特征在于， 所述的步骤 B1进一步包括：
当一个方向相对另一个方向调整次数的比例值大于预定比例时， 则 将该方向的步长调整为预定步长的整数倍。
12、 根据权利要求 5至 10其中之一所述的使主备时钟单板时钟相位 对齐的方法， 其特征在于， 采用相位检测模块来检测本时钟板输出的时 钟与对板输出的时钟的相位差， 其在本时钟板输出时钟滞后于对板时钟 时输出的高电平， 否则输出低电平。
13、 根据权利要求 5所述的使主备时钟单板时钟相位对齐的方法， 其特征在于， 所述的方法还包括： 当本时钟板的时钟输入到直接数字合 成器件之前， 本时钟板的时钟信号还经过锁相模块进行处理。
14、 一种时钟单板， 包含中央处理单元、 锁相模块、 主备用控制模 块， 其特征在于： 还包含直接数字合成器件和相位检测模块；
所述直接数字合成器件， 用于接收锁相模块发送的锁相后时钟， 根 据其内部相位寄存器的值调整该时钟的相位并输出；
所述相位检测模块， 用于检测直接数字合成器件输出的本板时钟与 对板时钟之间的相位差；
所述中央处理单元， 用于根据主备用控制模块发送的对板的主备用 状态， 在本板处于备用状态下， 根据相位检测模块所检测的相位差计算 直接数字合成器件中的相位寄存器的值发送给直接数字合成器件； 在本 板处于主用状态下， 控制直接数字合成器件停止相位调整。
15、 根据权利要求 14所述的时钟单板， 其特征在于： 该时钟单板还 包含输出控制模块； 该输出控制模块接收直接数字合成器件输出的本板 时钟， 根据主备用控制模块发送的控制命令， 在本板处于主用状态下， 输出本板时钟。
16、 根据权利要求 14所述的时钟单板， 其特征在于： 该时钟单板还 包含参考源检测与选择模块， 该参考源检测与选择模块对输入的多个参 考时钟进行检测和选择， 选择出与对板相同的时钟参考源， 输出给锁相 模块。
PCT/CN2006/001474 2005-06-27 2006-06-27 Dispositif permettant l'alignement d'une phase d'horloge entre un carte d'horloge principale et une carte d'horloge de secours et procede et carte d'horloge correspondants WO2007000111A1 (fr)

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