WO2006134216A2 - Circuit board structure and method for manufacturing a circuit board structure - Google Patents

Circuit board structure and method for manufacturing a circuit board structure Download PDF

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Publication number
WO2006134216A2
WO2006134216A2 PCT/FI2006/000207 FI2006000207W WO2006134216A2 WO 2006134216 A2 WO2006134216 A2 WO 2006134216A2 FI 2006000207 W FI2006000207 W FI 2006000207W WO 2006134216 A2 WO2006134216 A2 WO 2006134216A2
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WO
WIPO (PCT)
Prior art keywords
conductor
component
conductor layer
layer
circuit
Prior art date
Application number
PCT/FI2006/000207
Other languages
French (fr)
Other versions
WO2006134216A3 (en
Inventor
Risto Tuominen
Antti Iihola
Petteri Palm
Original Assignee
Imbera Electronics Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Priority to KR1020087000597A priority Critical patent/KR101090423B1/en
Priority to EP06764433.6A priority patent/EP1891845B1/en
Priority to JP2008516355A priority patent/JP5025644B2/en
Priority to US11/917,737 priority patent/US8581109B2/en
Priority to CN200680021055A priority patent/CN100596258C/en
Publication of WO2006134216A2 publication Critical patent/WO2006134216A2/en
Publication of WO2006134216A3 publication Critical patent/WO2006134216A3/en
Priority to US14/076,292 priority patent/US9622354B2/en
Priority to US15/355,096 priority patent/US11134572B2/en
Priority to US17/460,458 priority patent/US11792941B2/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/064Photoresists
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    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H05K1/187Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
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    • H05K1/188Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

  • the present invention relates to a method for manufacturing a circuit-board structure and a circuit-board structure.
  • the circuit-board structure manufactured can form, for example, part of a circuit board, a multilayer circuit board, a component packet, or an electronic module.
  • the circuit-board structure comprises at least one layer of conductor patterns and at least one component, which is connected electrically to the conductor patterns.
  • the invention also relates to methods, in which at least one component connected to a conductor pattern is surrounded by an insulation-material layer.
  • Such solutions can be alternatively also referred to as circuit-board or module structures, which contain buried, embedded, or built-in components.
  • the insulation-material layer surrounding the component is typically part of the basic structure of a circuit-board or module structure, which forms a support for the innermost conductor layers of the circuit board or module.
  • Application publication US 2005/0001331 discloses a circuit-board structure manufacturing method, in which first of all a circuit board is manufactured, which comprises an insulator layer and a conductor pattern on top of it. After this, a semiconductor component is connected to the conductor patterns by means of a suitable flip-chip method. The connection takes place through contact bumps on the surface of the semiconductor component.
  • a patterned and unpatterned insulation-material layer is laminated on top of the circuit board and a conductor-pattern layer is further laminated on their surface.
  • Patent publications US 6,038,133 and US 6,489,685 as well as application publication US 2002/0117743 disclose a method, in which a conductor pattern is manufactured on the surface of a detachable membrane, and a semiconductor component is connected to the conductor pattern by means of a flip-chip attachment method. After this, the component is surrounded with a layer of insulation material and the detachable membrane is removed.
  • the component is glued to the surface of a conductor layer and, after the gluing of the component, an insulating-material layer, which surrounds the component attached to the conductor layer, is formed of attached to the conductor layer. After the gluing of the component, vias are also made, through which electrical contacts are formed between the conductor layer and the contact areas of the component. After this, conductor patterns are formed from the conductor layer, to the surface of which the component is glued.
  • the invention is intended to develop a new method for manufacturing a circuit-board structure.
  • a method is implemented, in which a conductor layer is made, which comprises both a conductor pattern and a conductor foil.
  • the component is attached to the conductor layer comprising the conductor pattern and conductor foil and, after the attaching of the component, the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.
  • the invention has several embodiments, a few of which are presented briefly in the following.
  • the manufacture of the conductor layer can be performed in several different ways:
  • the conductor layer is manufactured by growing a conductor pattern on top of a conductor foil, using a growing method.
  • the conductor foil is grown directly into its correct shape.
  • the conductor layer is manufactured by thinning areas of a thicker conductor foil, in such a way that a thinner conductor foil and a conductor pattern on top of this remain.
  • the thinning of the areas can be implemented, for example, using a photo- lithographic method, or a laser-ablation method.
  • the attachment of the component can also be performed using several techniques and in one or more stages.
  • the attachment of the component is concerned with achieving a mechanical attachment between the component and the conductor pattern, in such a way that the component and the conductor pattern will remain in place in the circuit-board structure.
  • the attachment of the component is also concerned with making an electrical contact between the component and the conductor pattern, in such a way that, through the conductor pattern, the desired voltages and currents can be led to the component and away from the component.
  • the mechanical attachment and the electrical contact can be made simultaneously using a single connection method, or proceed in such a way that the mechanical attachment is made first and the electrical contact in some suitable later process stage. It is also possible to proceed in such a way that the electrical contact is made first along with a preliminary mechanical attachment, in which case the final mechanical attachment is made in some suitable later process stage.
  • the electrical contact of the component can be made using several techniques:
  • the component is connected to the conductor layer using an ultrasonic bonding method.
  • the component is connected to the conductor layer by soldering.
  • the component is connected to the conductor layer by a conductive adhesive.
  • the component is connected to the conductor layer using a via method.
  • contact openings need not necessarily be made in the conductor layer at the locations of the contact areas of the component. If, on the other hand, a via method is used, contact openings, the position of which corresponds to the locations of the contact areas of the component, are made hi the conductor layer, or at least hi the conductor-pattern part of it.
  • the making of the contact openings too can also be performed according to several different embodiments:
  • the contact openings are made before the attachment of the component and through the entire conductor layer, i.e. the openings extend through both the conductor layer and the conductor pattern.
  • the component can then be aligned with the contact openings.
  • the contact openings are made partly before the attachment of the component, in such a way that the partly made contact openings extend into the conductor layer, without extending through it.
  • the contact openings are opened later to extend through the conductor pattern, or they are opened in connection with the thinning of the conductor layer.
  • the contact openings are made after the attachment of the component, but before the thinning of the conductor pattern.
  • the contact openings are made in such a way that they extend through the entire conductor layer, or so that they partly penetrate it, in such a way that they open at the latest in connection with the thinning of the conductor layer.
  • the contact openings are made after the attachment of the component and the thinning of the conductor pattern, hi such an embodiment, the contact openings extend through the conductor layer.
  • the contact openings are made in the conductor pattern in connection with the making of the conductor pattern.
  • the contact openings are filled, in a suitable stage of the method, with a conductor material, for example, a metal, metal alloy, a conductive paste or conductive polymer, for example, a conductive adhesive.
  • a conductor material for example, a metal, metal alloy, a conductive paste or conductive polymer, for example, a conductive adhesive.
  • the edges of the contact openings are surfaced with a conductor material.
  • the best electrical contact is achieved using an embodiment, in which the contact openings are filled by growing metal into the openings and on top of the contact areas of the component, for example, using a chemical and/or electrochemical surfacing method. It will then be possible to create in the contact openings a via structure that is of essentially pure metal. It will then also be possible to create in the contact openings a via structure, which is in metallurgical contact with the conductor material of the contact areas.
  • the mechanical attachment of the component can be made using several techniques:
  • the component is attached to the conductor layer by soldering or using an ultrasonic bonding method.
  • the mechanical attachment created is later reinforced with the aid of an insulating material, for example, by filling the gap between the component and the conductor layer with a hardening polymer, or by surrounding the component tightly with an insulating material that adheres to the surface of both the component and the conductor pattern.
  • the component is attached to the conductor layer using a conductive adhesive.
  • the adhesive can already at the same time form itself a sufficient mechanical attachment.
  • the mechanical attachment can also be reinforced in the manner described in connection with the previous embodiment.
  • the adhesive can be an isotropically conductive adhesive, or an anisotropically conductive adhesive.
  • the component is attached to the conductor layer by an insulating adhesive.
  • An electrical contact can be made later through the insulating adhesive.
  • the thinning of the conductor layer can also be performed in several different ways. The thinning of the conductor layer is intended to removed conductor material from between the conductor patterns.
  • the conductor layer is thinned throughout, in such a way that the thickness of the conductor layer diminishes both at the locations of the conductor patterns and in the areas remaining between the conductor patterns.
  • the thinning can be performed, for example, by wet-etching.
  • the conductor layer is thinned in areas, in such a way that the thickness of the conductor layer diminishes in the areas remaining between the conductor patterns, but remains essentially unchanged at the locations of the conductor patterns.
  • This can be achieved, for example, by wet-etching, in which a suitable etching mask is used on the surface of the conductor patterns.
  • an insulating-material layer is made around the component and on the surface of the conductor pattern.
  • the insulating-material layer can be made from one or more insulating-material sheets, or from an insulating material spread in a fluid form.
  • the insulating-material layer can be made, for example, according to the following embodiments:
  • the insulating-material layer is taken and a conductor layer is made on its surface. Before this or after this a suitable opening for the component is made in the insulating-material layer.
  • an insulating-material layer is made on the surface of the conductor layer. After this, an opening for the component is opened in the insulating-material layer.
  • the component is first attached to the conductor layer (mechanical attachment or electrical contact and at least a preliminary mechanical attachment), and after this an insulating-material layer is made on the surface of the conductor layer and around the component.
  • the conductor foil of the conductor layer is typically a unified, or at least a substantially unified conductor foil.
  • the conductor layer can, however, be handled as a single piece.
  • the thickness of the conductor foil is typically such that it will withstand the treatment required by the process without breaking or being damaged, also without support, hi the embodiments, it is of course possible to use a thinner conductor foil, in which case the conductor foil will be supported with the aid of a support layer.
  • the conductor pattern of the conductor layer includes conductors of the conductor-pattern layer being made in the circuit-board structure, or patterns corresponding to these conductors.
  • the conductors can thus be connected to each other, or separate, according to the desired circuit-board design.
  • References to the contact areas of the component mean conductor areas on the surface of the component, through which an electrical contact can be formed to the component.
  • the contact area can be formed by, for example, a contact bump or a conductor area on the surface of the component.
  • Figures 1 - 8 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a first embodiment.
  • Figures 9 - 16 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a second embodiment.
  • Figures 17 - 22 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a third embodiment.
  • Figures 23 - 26 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a fourth embodiment.
  • Figures 27 - 32 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a fifth embodiment.
  • the circuit-board blank shown in Figure 1 is manufactured first of all.
  • the circuit-board blank of Figure 1 comprises an insulating-material layer 1, a conductor foil 3 on the first surface of this, and a conductor foil 2 on the second surface.
  • the circuit-board blank also comprises a recess 4.
  • the circuit-board blank comprises a thinner insulating-material layer 11 between the insulating-material layer 1 and the conductor foil 2.
  • the insulating-material layer 11 can be of material differing from that of the insulating-material layer 1, or it can be part of the insulating-material layer 1.
  • the circuit-board blank of Figure 1 may have been formed, for example, by laminating together or otherwise combining with each other the insulating-material layer 1, the conductor foil 2, the conductor foil 3, and the insulating- material layer 11.
  • the circuit-board blank of Figure 1 may have been formed, for example, in such a way that a recess 4 has been made in the blank formed by the insulating-material 1, the conductor foil 2, and the conductor foil 3.
  • the recess 4 will not extent completely through the insulating-material layer 1, but instead a corresponding part of the insulating- material layer 11 has been left on the 'bottom' of the recess.
  • the method of the example can, of course, be modified in such a way that the recess 4 extends to the conductor foil 2, in which case there will not be an insulating-material layer 11 in the circuit-board blank, at least at the location of the recess.
  • the reliability of the circuit-board structure can be improved by using an insulating-material layer 11. This is due to the fact that the use of an insulating- material layer 11 for its part ensures that unnecessary openings will not remain hi the insulating material between the component and the conductor foil 2.
  • Manufacture is continued by electrolytically growing a conductor material, typically copper, in the areas from which the photoresist was removed.
  • the desired conductor patterns 6 and 7 are then formed on the surfaces of the conductor foils 2 and 3, which is shown in Figure 4.
  • the thickness of the conductor pattern can be, for example, 20 micrometres while the width of the line of the conductor patterns being made can be less than 20 micrometres. The method can thus also be used to manufacture small and precise conductor patterns.
  • the method can be modified in such a way that a layer of some other metal or metal alloy, for example tin, can be made on the surface of the conductor patterns 6 and 7, or on the interface between the conductor foils 2 and 3 and the conductor patterns 6 and 7. This layer can be used as an etching stop.
  • a layer of some other metal or metal alloy for example tin
  • the method can also be modified in such a way that the recess 4 is made only after the spreading of the photoresist layer 5, or at an even later process stage.
  • contact openings 8 are made in the conductor pattern 6 of the circuit-board blank, at the locations of the contact areas of the component.
  • the contact openings 8 can be made in such a way that they essentially extend through the conductor pattern 8, or in such a way that they essentially extend through both the conductor pattern 8 and the conductor foil 2, (i.e. through the entire conductor layer). It is also possible to make the contact openings from the other direction, in such a way that they extend through only the insulating-material layer 11 and the conductor foil 2. In the example, the contact openings 8 are made in such a way that they extend through the conductor pattern 6, the conductor foil 2, and the insulating-material layer 11.
  • Figure 4 shows the circuit-board blank after this intermediate stage.
  • the contact openings 8 can be made, for example, by drilling with a laser.
  • the contact openings 8 are aligned correctly in position relative to the conductor pattern 6.
  • the mutual position of the contact openings 8 corresponds to the mutual position of the contact areas of the component.
  • at least one contact opening 8 is made for each contact area participating in the creation of an electrical contact.
  • the surface area of the contact openings 8 being made can be more or less as large as the surface area of the corresponding contact areas.
  • the surface area of a contact opening 8 can, of cour.se, also be selected to be smaller, or in some embodiments slightly larger, than the surface area of the corresponding contact area.
  • the component 9 is attached to the circuit-board blank with the aid of an adhesive 10.
  • an adhesive layer 10 is spread on the surface of the insulating-material layer 11, on the 'bottom' of the recess 4.
  • Figure 5 shows this intermediate stage.
  • the adhesive layer can be spread on the attachment surface of the component 9, or on both the attachment surface of the component 9 and on the surface of the insulating-material layer 11.
  • the adhesive 10 can also be spread in stages and in layers.
  • the components 9 can be aligned in the positions designed for the components 9, with the aid of alignment marks.
  • the contact openings 8, or the conductor patterns 6 or 7, or separate alignment marks can act as alignment marks.
  • Figure 6 shows the circuit-board blank after the gluing of the component 9.
  • attachment surface of the component 9 refers to that surface of the component 9 that will face the conductor pattern 6.
  • the attachment surface of the component 9 comprises contact areas, by means of which an electrical contact can be made to the component.
  • the contact areas can be, for example, flat areas on the surface of the component 9, or more usually contact protrusions, such as contact bumps, on the surface of the component 9. There are usually at least two contact areas or contact protrusions in the component 9. In complex microcircuits there can well be many contact areas.
  • the term adhesive refers to a material, by means of which a component can be attached to the circuit-board blank.
  • One property of an adhesive is that the adhesive can be spread on the surface of the circuit-board blank and/or of the component in a relatively fluid form, or otherwise in a form that conforms to surface shapes, for example, in the form of a film.
  • Another property of an adhesive is that after spreading the adhesive hardens or can be hardened, at least partly, so that the adhesive will be able to hold the component in place at least until the component is attached to the structure in some other way.
  • the third property of the adhesive is its adhesive ability, i.e. its ability to bond to the surface being glued.
  • gluing refers to attaching the component and the circuit-board to each other with the aid of an adhesive.
  • adhesive is thus brought between the component and the circuit-board blank and the component is set in a suitable position relative to the circuit-board blank, in which the adhesive is in contact with the component and the circuit-board blank and at least partly fills the space between the component and the circuit-board blank.
  • the adhesive is allowed to (at least partly) harden or the adhesive is (at least partly) actively hardened, so that the component attaches to the circuit-board blank with the aid of the adhesive.
  • the contact protrusions of the component may, during gluing, extend through the adhesive layer to come in contact with the rest of the structure of the circuit-board blank.
  • the adhesive used in the embodiments is, for example, a thermally cured epoxy.
  • the adhesive is selected in such a way that the adhesive used has sufficient adhesion with the circuit-board blank and the component.
  • One advantageous property of the adhesive is a suitable coefficient of thermal expansion, so that the thermal expansion of the adhesive will not differ too much from the thermal expansion of the surrounding material during the process.
  • the adhesive selected should also preferably have a short hardening time, preferably of a few seconds at most. In this time the adhesive should harden at least partly in such a way that it is able to hold the component in place. The final hardening can take clearly more time and the final hardening can indeed be designed to take place in connection with later process stages.
  • the electrical conductivity of the adhesive is preferably in the order of the electrical conductivity of insulating materials.
  • the component 9 to be attached can be, for example, an integrated circuit, such as a memory chip, a processor, or an ASIC.
  • the component to be attached can also be, for example, a MEMS, LED, or a passive component.
  • the component to be attached can be cased or uncased, and it can comprise contact bumps in the contact areas or be without bumps. There can also be a conductor surfacing thinner than a contact bump on the surface of the contact areas of the component.
  • the outer surface of the contact areas of the component can thus be on the level of the outer surface of the component, on the bottom of recesses on the surface of the component, or on the surface of protrusions extending from the surface of the component.
  • the recess is filled with a filler material 12.
  • the example can also be modified in such a way that manufacture is started from a circuit- board blank (the situation in Figure 1), which comprises only a conductor foil 2 and possibly an insulating-material layer 11. After this, process stages that are otherwise the same as those described above, except that naturally the method stages relating to the conductor foil 3, the conductor pattern 7, and the resist layer 5 relating to them are omitted.
  • the circuit-board blank comprises, after the gluing of the component (refer to Figure 6):
  • an insulator layer 1 which surrounds the component 9 and supports the conductor layers 2 and 6, is made on the surface with the component 9 of the circuit-board blank.
  • the insulator layer 1 can be formed, for example, by putting an insulating-material sheet, in which openings have been made at the location of the components 9, on top on the circuit-board blank.
  • a unified insulating-material sheet can be put on top of the insulating-material sheet 9. Both sheets can be similar, or sheets than differ from each other can also be used, at least one of which is prehardened or unhardened.
  • Examples of materials suitable for the insulator layer 1 are PI (polyimide), FR4, FR5, aramid, polytetrafluoroethylene, Teflon®, LCP (liquid crystal polymer), and a prehardened binder layer, i.e. prepreg.
  • PI polyimide
  • FR4 FR5
  • aramid polytetrafluoroethylene
  • Teflon® Teflon®
  • LCP liquid crystal polymer
  • a prehardened binder layer i.e. prepreg.
  • the insulating-material sheets put on top of the circuit-board blank are pressed, with the aid of heat and pressure, to form a unified insulator layer 1.
  • the insulating-material sheets on the upper surface of one can also be a ready conductor-pattern layer, so that after pressing the circuit-board blank comprises at least two conductor-pattern layers, as shown by the series of figures.
  • conductor patterns 7 can, however, also be designed at the location of the
  • vias 13 Both in the example shown in the figure series and in the above described modification, it is next possible to make vias 13, with the aid of which electrical contacts are made between the contact areas of the components 9 and the conductor patterns 6.
  • the contact openings 8 are cleaned of adhesive and other materials that may have been pushed into them.
  • the cleaning can be performed using, for example, a plasma technique, chemically, or with the aid of a laser. If the contact openings 4 and the contact areas are already sufficiently clean, the cleaning can naturally be omitted.
  • the contact openings 8 were made to only partly penetrate, the contact openings 8 are opened in this stage. It is also possible to proceed in such a way that the contact openings 8 are made entirely in this stage.
  • a conductor material is introduced to the contact openings 8, in such a way that it forms an electrical contact between the component 9 and the conductor pattern 6.
  • the conductor material of the vias 13 can be made, for example, by filling the contact openings 8 with an electrically conductive paste.
  • the conductor material can also be made using one of several growing methods known in the circuit-board industry. High- quality electrical contacts can be made, for example, by forming a metallurgical connection by growing a conductor material using a surfacing method, for example, a chemical or electrochemical method. One good alternative is the growing of a thin layer using a chemical method and continuing the growing using a more economical electrochemical method.
  • the term filling refers to the fact that the contact openings are at least substantially filled with the conductor material. Instead of filling, surfacing can also be performed in such a way that only the edges of the contact openings are surfaced. In addition to these methods, it is of course possible to also use some other method, which will be beneficial in terms of the end result.
  • the contact openings 8, the contact areas of the component 9, and the conductor patterns 6 are surfaced first of all with a thin conductor layer and then afterwards the thickness of the conductor layer is increased electrolytically until the contact openings 8 are filled with conductor material.
  • Figure 7 shows the structure after the growing. After this, the circuit-board blank is etched, to remove the excess conductor material. If a protective membrane is used on the surface of the conductor patterns 6 and 7, the conductor material is removed essentially only from those parts of the conductor foils 2 and 3 that remain outside the conductor patterns 6 and 7. Alternatively, it is possible to etch the entire conductor layer, so that the material of the conductor foils 2 and 3 is removed from outside the conductor patterns 6 and 7. In that case, material of the conductor patterns 6 and 7 too will be removed, but the conductor patterns 6 and 7 will be copied into the material of the conductor foils 2 and 3.
  • a circuit-board blank is made, which comprises an insulator layer 1, a recess 4, and conductor foils 2 and 3 ( Figure 9).
  • Photoresists 5 are spread and exposure takes place through the masks ( Figure 10). The exposed areas 5' are shown darkened in the figure.
  • Conductor material is grown using an electrolytic method. The conductor material then grows in the openings of the resist 5 and the contact openings 8 are filled, thus forming both conductor patterns 6 and 7 and vias 13 ( Figure 15).
  • the conductor foils 2 and 3 are preferably thin relative to the conductor patterns 6 and 7 to be grown on their surfaces.
  • the conductor foils 2 and 3 are thus intended to conduct the current required by the electrolytic growing to the growing areas. If the conductor foils 2 and 3 are thin relative to the conductor patterns 6 and 7, the etching of the conductor foils 2 and 3 away from outside the conductor patterns 6 and 7 will not substantially affect the relative dimensions of the conductor patterns 6 and 7.
  • a circuit-board blank is made, which comprises a conductor foil 2 and a conductor pattern 6 ( Figure 17).
  • This can be made, for example, in such a way that a resist "5, which is exposed and developed, is spread on top of the conductor foil 2.
  • metal is grown in the openings formed in the resist 5, for example, using an electrochemical method.
  • contact openings are also defined in the exposure mask of the resist, so that the resist will remain at the locations of the contact openings 8'.
  • contact openings 8 are also formed in the conductor patterns 6, and are thus aligned directly and in a self-aligning manner in the correct places relative to the conductor pattern 6. - The resist is removed and the contact openings 8 are opened to also extend through the conductor foil 2 ( Figure 18).
  • the component 9 is glued onto the surface of the conductor pattern 6 with the aid of an adhesive 10 ( Figure 19). The component is aligned in the correct position relative to the conductor pattern 6 and the contact openings 8.
  • the contact openings 8 are cleaned and vias 13 are made in the contact openings from a conductor material (Figure 21).
  • the vias 13 are made using a surfacing method. In that case, the vias are surfaced in such a way that the necessary electrical contact arises, i.e. generally a conductor layer is made at least on the edges of the contact openings 8.
  • the contact openings 8 are grown full of the conductor material. The more conductor material is put into a via 13, the better will be the conductivity of the via 13.
  • the vias 13 are indeed preferably made to be at least substantially filled with conductor material.
  • the conductor foil 2 is removed, for example, by etching ( Figure 22).
  • a circuit-board blank is made, which comprises a conductor foil 2 and a conductor pattern 6 ( Figure 23). This can be made, for example, in such a way that a resist 5, which is exposed and developed, is spread on top of the conductor foil 2. After this, metal is grown in the openings formed in the resist 5, for example, using an electrochemical method.
  • a component 9 is glued on top of the conductor pattern 6, with the aid of an anisotropically conductive adhesive 20 ( Figure 24).
  • the anisotropically conductive adhesive 20 forms an electrical contact in the direction between the contact areas of the component and the conductor pattern 6.
  • the adhesive 20 is, however, electrically insulating in the transverse direction, so that an electrical contact is not formed between the contact areas of the component, nor between the separate conductors of the conductor pattern 6.
  • An insulating-material layer 1 is made on top of the circuit-board blank and on the surface of that a conductor foil 3 ( Figure 25).
  • the conductor foil 2 is removed, for example, by etching.
  • the conductor foil 3 is patterned to form a conductor pattern 7 ( Figure 26).
  • a circuit-board blank is made, which comprises a conductor foil 2 and a conductor pattern 6 ( Figure 27). This can be made, for example, in such a way that a resist 5, which is exposed and developed, is spread onto top of the conductor foil 2. After this, metal is grown in the openings formed in the resist 5, for example, using an electrochemical method.
  • a conductor material is made in the opening formed in the resist 15, for example, using an electrochemical method.
  • the made conductor areas form contact bumps 17 on the surface of the conductor pattern 6 ( Figure 28).
  • - A component 9 is attached on top of the conductor pattern 6 and against the contact bumps 17, using a suitable method ( Figure 30).
  • the joint is made by an ultrasonic bonding method or alternatively by a thermo- compression bonding method.
  • a component 9 is used, which does not itself contain contact bumps.
  • An insulating-material layer 1 is made on top of the circuit-board blank, and a conductor foil 3 of top of that ( Figure 31).
  • the conductor foil 2 is removed, for example, by etching.
  • the conductor foil 3 is patterned to form a conductor pattern 7 ( Figure 32).
  • a suitable intermediate layer which will not dissolve in the etching agent used, or will dissolve in it extremely slowly, can also be used between the conductor foil and the conductor pattern, or on the surface of either of them.
  • the etching stops at the intermediate layer and the desired surface can be defined precisely.
  • An intermediate layer of this kind can be made, for example, from some other metal, such as tin. If necessary, the intermediate layer can be removed, for example, chemically with some other etching agent.
  • the sensitivity of the method to alignment errors can be reduced by dimensioning the diameter of the contact openings 8 to be greater than the width of the conductors of the conductor pattern 6.
  • thermal vias can also be made, which are intended to conduct heat more efficiently away from the component 9.
  • the increase in the efficiency of heat conducting is based on the thermal conductivity of the thermal via being greater than that of the insulating material surrounding the component.
  • electrical conductors are typically also good thermal conductors, the thermal vias can in most cases be made using the same technique and even in the same process stage as the electrical contacts to the components 9.
  • the method can also be used for manufacturing many different kinds of three-dimensional circuit structures.
  • the method can be used, for example, in such a way that several components, for example, semiconductor chips, are placed on top of each other, thus forming a packet containing several components, in which the components are connected to each other to form a single functional totality.
  • Such a packet can be termed a three-dimensional multi-chip module.
  • Such packets can also contain several components, which are connected electrically to each other.
  • the method can also be used to manufacture entire electrical modules.
  • the module can also be a circuit board, to the outer surface of which components can be attached, in the same way as to a conventional circuit board.

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Abstract

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil (2) and a conductor pattern (6) on the surface of the conductor foil. A component (9) is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern (6).

Description

CIRCUIT BOARD STRUCTURE AND METHOD FOR MANUFACTURING A
CIRCUIT BOARD STRUCTURE
The present invention relates to a method for manufacturing a circuit-board structure and a circuit-board structure.
The circuit-board structure manufactured can form, for example, part of a circuit board, a multilayer circuit board, a component packet, or an electronic module.
The circuit-board structure comprises at least one layer of conductor patterns and at least one component, which is connected electrically to the conductor patterns.
The invention also relates to methods, in which at least one component connected to a conductor pattern is surrounded by an insulation-material layer. Such solutions can be alternatively also referred to as circuit-board or module structures, which contain buried, embedded, or built-in components. The insulation-material layer surrounding the component is typically part of the basic structure of a circuit-board or module structure, which forms a support for the innermost conductor layers of the circuit board or module.
Application publication US 2005/0001331 discloses a circuit-board structure manufacturing method, in which first of all a circuit board is manufactured, which comprises an insulator layer and a conductor pattern on top of it. After this, a semiconductor component is connected to the conductor patterns by means of a suitable flip-chip method. The connection takes place through contact bumps on the surface of the semiconductor component. In the method of the US publication, after the connection of the component a patterned and unpatterned insulation-material layer is laminated on top of the circuit board and a conductor-pattern layer is further laminated on their surface.
Patent publications US 6,038,133 and US 6,489,685 as well as application publication US 2002/0117743 disclose a method, in which a conductor pattern is manufactured on the surface of a detachable membrane, and a semiconductor component is connected to the conductor pattern by means of a flip-chip attachment method. After this, the component is surrounded with a layer of insulation material and the detachable membrane is removed.
The aforementioned publication US 6,038,133 and US 2002//0117743 also disclose methods, in which a component is connected by a flip-chip method not to conductor patterns but to a unified conductor foil, from which conductors patterns are formed in a later stage of the process. Corresponding method are also disclosed, for example, in the publications US 5,042,145; WO 2004/077902; WO 2004/077903; and WO 2005/020651.
In addition to the aforementioned types of method, many other methods are known, which can be used to manufacture circuit-board structures containing components. The components can, for example, first of all be placed inside an insulating-material layer and connected electrically to the conductor layer only after this, as is disclosed in application publication WO 2004/089048. In the method of application publication WO
2004/089048, the component is glued to the surface of a conductor layer and, after the gluing of the component, an insulating-material layer, which surrounds the component attached to the conductor layer, is formed of attached to the conductor layer. After the gluing of the component, vias are also made, through which electrical contacts are formed between the conductor layer and the contact areas of the component. After this, conductor patterns are formed from the conductor layer, to the surface of which the component is glued.
The invention is intended to develop a new method for manufacturing a circuit-board structure.
According to the invention, a method is implemented, in which a conductor layer is made, which comprises both a conductor pattern and a conductor foil. The component is attached to the conductor layer comprising the conductor pattern and conductor foil and, after the attaching of the component, the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.
In this way, a new method for manufacturing a circuit-board structure is created. The invention has several embodiments, a few of which are presented briefly in the following.
The manufacture of the conductor layer can be performed in several different ways:
- According to one embodiment, the conductor layer is manufactured by growing a conductor pattern on top of a conductor foil, using a growing method. Thus the conductor foil is grown directly into its correct shape.
- According to a second embodiment, the conductor layer is manufactured by thinning areas of a thicker conductor foil, in such a way that a thinner conductor foil and a conductor pattern on top of this remain. The thinning of the areas can be implemented, for example, using a photo- lithographic method, or a laser-ablation method.
The attachment of the component can also be performed using several techniques and in one or more stages. The attachment of the component is concerned with achieving a mechanical attachment between the component and the conductor pattern, in such a way that the component and the conductor pattern will remain in place in the circuit-board structure. The attachment of the component is also concerned with making an electrical contact between the component and the conductor pattern, in such a way that, through the conductor pattern, the desired voltages and currents can be led to the component and away from the component. The mechanical attachment and the electrical contact can be made simultaneously using a single connection method, or proceed in such a way that the mechanical attachment is made first and the electrical contact in some suitable later process stage. It is also possible to proceed in such a way that the electrical contact is made first along with a preliminary mechanical attachment, in which case the final mechanical attachment is made in some suitable later process stage.
The electrical contact of the component can be made using several techniques:
- hi one embodiment, the component is connected to the conductor layer using an ultrasonic bonding method.
- hi a second embodiment, the component is connected to the conductor layer by soldering. - In a third embodiment, the component is connected to the conductor layer by a conductive adhesive.
- In a fourth embodiment, the component is connected to the conductor layer using a via method.
In the first, second, and third connection techniques for the component, contact openings need not necessarily be made in the conductor layer at the locations of the contact areas of the component. If, on the other hand, a via method is used, contact openings, the position of which corresponds to the locations of the contact areas of the component, are made hi the conductor layer, or at least hi the conductor-pattern part of it. The making of the contact openings too can also be performed according to several different embodiments:
- In a first embodiment, the contact openings are made before the attachment of the component and through the entire conductor layer, i.e. the openings extend through both the conductor layer and the conductor pattern. The component can then be aligned with the contact openings.
- In a second embodiment, the contact openings are made partly before the attachment of the component, in such a way that the partly made contact openings extend into the conductor layer, without extending through it. In such an embodiment, the contact openings are opened later to extend through the conductor pattern, or they are opened in connection with the thinning of the conductor layer.
- In a third embodiment, the contact openings are made after the attachment of the component, but before the thinning of the conductor pattern. In such an embodiment, the contact openings are made in such a way that they extend through the entire conductor layer, or so that they partly penetrate it, in such a way that they open at the latest in connection with the thinning of the conductor layer.
- In a fourth embodiment, the contact openings are made after the attachment of the component and the thinning of the conductor pattern, hi such an embodiment, the contact openings extend through the conductor layer. - In a fifth embodiment, the contact openings are made in the conductor pattern in connection with the making of the conductor pattern.
When using a via method, the contact openings are filled, in a suitable stage of the method, with a conductor material, for example, a metal, metal alloy, a conductive paste or conductive polymer, for example, a conductive adhesive. Alternatively, the edges of the contact openings are surfaced with a conductor material. The best electrical contact is achieved using an embodiment, in which the contact openings are filled by growing metal into the openings and on top of the contact areas of the component, for example, using a chemical and/or electrochemical surfacing method. It will then be possible to create in the contact openings a via structure that is of essentially pure metal. It will then also be possible to create in the contact openings a via structure, which is in metallurgical contact with the conductor material of the contact areas.
The mechanical attachment of the component can be made using several techniques:
- In one embodiment, the component is attached to the conductor layer by soldering or using an ultrasonic bonding method. The mechanical attachment created is later reinforced with the aid of an insulating material, for example, by filling the gap between the component and the conductor layer with a hardening polymer, or by surrounding the component tightly with an insulating material that adheres to the surface of both the component and the conductor pattern.
- In a second embodiment, the component is attached to the conductor layer using a conductive adhesive. The adhesive can already at the same time form itself a sufficient mechanical attachment. The mechanical attachment can also be reinforced in the manner described in connection with the previous embodiment. The adhesive can be an isotropically conductive adhesive, or an anisotropically conductive adhesive.
- In a third embodiment, the component is attached to the conductor layer by an insulating adhesive. An electrical contact can be made later through the insulating adhesive. The thinning of the conductor layer can also be performed in several different ways. The thinning of the conductor layer is intended to removed conductor material from between the conductor patterns.
- According to one embodiment, the conductor layer is thinned throughout, in such a way that the thickness of the conductor layer diminishes both at the locations of the conductor patterns and in the areas remaining between the conductor patterns. The thinning can be performed, for example, by wet-etching.
- According to a second embodiment, the conductor layer is thinned in areas, in such a way that the thickness of the conductor layer diminishes in the areas remaining between the conductor patterns, but remains essentially unchanged at the locations of the conductor patterns. This can be achieved, for example, by wet-etching, in which a suitable etching mask is used on the surface of the conductor patterns.
In several embodiments, an insulating-material layer is made around the component and on the surface of the conductor pattern. The insulating-material layer can be made from one or more insulating-material sheets, or from an insulating material spread in a fluid form. The insulating-material layer can be made, for example, according to the following embodiments:
- Li one embodiment, the insulating-material layer is taken and a conductor layer is made on its surface. Before this or after this a suitable opening for the component is made in the insulating-material layer.
- hi a second embodiment, an insulating-material layer is made on the surface of the conductor layer. After this, an opening for the component is opened in the insulating-material layer.
- In a third embodiment, the component is first attached to the conductor layer (mechanical attachment or electrical contact and at least a preliminary mechanical attachment), and after this an insulating-material layer is made on the surface of the conductor layer and around the component.
hi the embodiments, the conductor foil of the conductor layer is typically a unified, or at least a substantially unified conductor foil. Thus, there can be, for example, small holes in the conductor layer, for example, for alignment purposes. The conductor layer can, however, be handled as a single piece. The thickness of the conductor foil is typically such that it will withstand the treatment required by the process without breaking or being damaged, also without support, hi the embodiments, it is of course possible to use a thinner conductor foil, in which case the conductor foil will be supported with the aid of a support layer.
hi the embodiments, the conductor pattern of the conductor layer includes conductors of the conductor-pattern layer being made in the circuit-board structure, or patterns corresponding to these conductors. The conductors can thus be connected to each other, or separate, according to the desired circuit-board design.
References to the contact areas of the component mean conductor areas on the surface of the component, through which an electrical contact can be formed to the component. In this meaning, the contact area can be formed by, for example, a contact bump or a conductor area on the surface of the component.
In the following, the invention is examined with the aid of examples and with reference to the accompanying drawings.
Figures 1 - 8 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a first embodiment.
Figures 9 - 16 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a second embodiment.
Figures 17 - 22 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a third embodiment.
Figures 23 - 26 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a fourth embodiment.
Figures 27 - 32 show a series of cross-sections of the intermediate stages of the circuit- board structures, in a manufacturing process according to a fifth embodiment.
In the first example, the circuit-board blank shown in Figure 1 is manufactured first of all. The circuit-board blank of Figure 1 comprises an insulating-material layer 1, a conductor foil 3 on the first surface of this, and a conductor foil 2 on the second surface. The circuit-board blank also comprises a recess 4. In addition, the circuit-board blank comprises a thinner insulating-material layer 11 between the insulating-material layer 1 and the conductor foil 2. The insulating-material layer 11 can be of material differing from that of the insulating-material layer 1, or it can be part of the insulating-material layer 1. In the former case, the circuit-board blank of Figure 1 may have been formed, for example, by laminating together or otherwise combining with each other the insulating-material layer 1, the conductor foil 2, the conductor foil 3, and the insulating- material layer 11. hi the latter case, the circuit-board blank of Figure 1 may have been formed, for example, in such a way that a recess 4 has been made in the blank formed by the insulating-material 1, the conductor foil 2, and the conductor foil 3. hi that case, the recess 4 will not extent completely through the insulating-material layer 1, but instead a corresponding part of the insulating- material layer 11 has been left on the 'bottom' of the recess.
The method of the example can, of course, be modified in such a way that the recess 4 extends to the conductor foil 2, in which case there will not be an insulating-material layer 11 in the circuit-board blank, at least at the location of the recess. However, at least in some embodiments the reliability of the circuit-board structure can be improved by using an insulating-material layer 11. This is due to the fact that the use of an insulating- material layer 11 for its part ensures that unnecessary openings will not remain hi the insulating material between the component and the conductor foil 2.
Manufacture continues from the situation shown in Figure 1, by spreading resist layers 5, typically photoresist layers, on the surfaces of the conductor foils 2 and 3. This stage is shown in Figure 2. The photoresist layers 5 are exposed through a patterned mask and after this the blank is developed. After developing, the exposed photoresist layers 5 are patterned in the desired manner to form conductor-pattern masks, which is shown in Figure 3.
Manufacture is continued by electrolytically growing a conductor material, typically copper, in the areas from which the photoresist was removed. The desired conductor patterns 6 and 7 are then formed on the surfaces of the conductor foils 2 and 3, which is shown in Figure 4. The thickness of the conductor pattern can be, for example, 20 micrometres while the width of the line of the conductor patterns being made can be less than 20 micrometres. The method can thus also be used to manufacture small and precise conductor patterns.
The method can be modified in such a way that a layer of some other metal or metal alloy, for example tin, can be made on the surface of the conductor patterns 6 and 7, or on the interface between the conductor foils 2 and 3 and the conductor patterns 6 and 7. This layer can be used as an etching stop.
The method can also be modified in such a way that the recess 4 is made only after the spreading of the photoresist layer 5, or at an even later process stage.
After the manufacture of the conductor patterns 6 and 7, the resist layers 5 can be removed. In addition, contact openings 8 are made in the conductor pattern 6 of the circuit-board blank, at the locations of the contact areas of the component. The contact openings 8 can be made in such a way that they essentially extend through the conductor pattern 8, or in such a way that they essentially extend through both the conductor pattern 8 and the conductor foil 2, (i.e. through the entire conductor layer). It is also possible to make the contact openings from the other direction, in such a way that they extend through only the insulating-material layer 11 and the conductor foil 2. In the example, the contact openings 8 are made in such a way that they extend through the conductor pattern 6, the conductor foil 2, and the insulating-material layer 11. Figure 4 shows the circuit-board blank after this intermediate stage.
The contact openings 8 can be made, for example, by drilling with a laser. The contact openings 8 are aligned correctly in position relative to the conductor pattern 6. The mutual position of the contact openings 8 corresponds to the mutual position of the contact areas of the component. Thus, at least one contact opening 8 is made for each contact area participating in the creation of an electrical contact. The surface area of the contact openings 8 being made can be more or less as large as the surface area of the corresponding contact areas. The surface area of a contact opening 8 can, of cour.se, also be selected to be smaller, or in some embodiments slightly larger, than the surface area of the corresponding contact area.
In the example, the component 9 is attached to the circuit-board blank with the aid of an adhesive 10. For the gluing, an adhesive layer 10 is spread on the surface of the insulating-material layer 11, on the 'bottom' of the recess 4. Figure 5 shows this intermediate stage. Alternatively, the adhesive layer can be spread on the attachment surface of the component 9, or on both the attachment surface of the component 9 and on the surface of the insulating-material layer 11. The adhesive 10 can also be spread in stages and in layers. After this, the components 9 can be aligned in the positions designed for the components 9, with the aid of alignment marks. For example, the contact openings 8, or the conductor patterns 6 or 7, or separate alignment marks (not shown in the figures) can act as alignment marks. Figure 6 shows the circuit-board blank after the gluing of the component 9.
The term attachment surface of the component 9 refers to that surface of the component 9 that will face the conductor pattern 6. The attachment surface of the component 9 comprises contact areas, by means of which an electrical contact can be made to the component. The contact areas can be, for example, flat areas on the surface of the component 9, or more usually contact protrusions, such as contact bumps, on the surface of the component 9. There are usually at least two contact areas or contact protrusions in the component 9. In complex microcircuits there can well be many contact areas.
In many embodiments, it is advantageous to spread so much adhesive on the attachment surface or attachment surfaces that the adhesive completely fills the space between the component 9 and the structure coming against the component. A separate filler agent will then not be required. Good filling will reinforce the mechanical connection between the component 9 and the circuit-board blank, so that a mechanically more durable construction will be achieved. A comprehensive adhesive layer 10 without gaps will also support the conductor pattern and protect the structure in later process stages. During gluing, adhesive also usually gets into the contact openings 8, if these open towards the attachment surface.
The term adhesive refers to a material, by means of which a component can be attached to the circuit-board blank. One property of an adhesive is that the adhesive can be spread on the surface of the circuit-board blank and/or of the component in a relatively fluid form, or otherwise in a form that conforms to surface shapes, for example, in the form of a film. Another property of an adhesive is that after spreading the adhesive hardens or can be hardened, at least partly, so that the adhesive will be able to hold the component in place at least until the component is attached to the structure in some other way. The third property of the adhesive is its adhesive ability, i.e. its ability to bond to the surface being glued.
The term gluing refers to attaching the component and the circuit-board to each other with the aid of an adhesive. In gluing, adhesive is thus brought between the component and the circuit-board blank and the component is set in a suitable position relative to the circuit-board blank, in which the adhesive is in contact with the component and the circuit-board blank and at least partly fills the space between the component and the circuit-board blank. After this, the adhesive is allowed to (at least partly) harden or the adhesive is (at least partly) actively hardened, so that the component attaches to the circuit-board blank with the aid of the adhesive. In some embodiments, the contact protrusions of the component may, during gluing, extend through the adhesive layer to come in contact with the rest of the structure of the circuit-board blank.
The adhesive used in the embodiments is, for example, a thermally cured epoxy. The adhesive is selected in such a way that the adhesive used has sufficient adhesion with the circuit-board blank and the component. One advantageous property of the adhesive is a suitable coefficient of thermal expansion, so that the thermal expansion of the adhesive will not differ too much from the thermal expansion of the surrounding material during the process. The adhesive selected should also preferably have a short hardening time, preferably of a few seconds at most. In this time the adhesive should harden at least partly in such a way that it is able to hold the component in place. The final hardening can take clearly more time and the final hardening can indeed be designed to take place in connection with later process stages. The electrical conductivity of the adhesive is preferably in the order of the electrical conductivity of insulating materials.
The component 9 to be attached can be, for example, an integrated circuit, such as a memory chip, a processor, or an ASIC. The component to be attached can also be, for example, a MEMS, LED, or a passive component. The component to be attached can be cased or uncased, and it can comprise contact bumps in the contact areas or be without bumps. There can also be a conductor surfacing thinner than a contact bump on the surface of the contact areas of the component. The outer surface of the contact areas of the component can thus be on the level of the outer surface of the component, on the bottom of recesses on the surface of the component, or on the surface of protrusions extending from the surface of the component.
After the gluing of the component 9, the recess is filled with a filler material 12. The example can also be modified in such a way that manufacture is started from a circuit- board blank (the situation in Figure 1), which comprises only a conductor foil 2 and possibly an insulating-material layer 11. After this, process stages that are otherwise the same as those described above, except that naturally the method stages relating to the conductor foil 3, the conductor pattern 7, and the resist layer 5 relating to them are omitted. In this embodiment, the circuit-board blank comprises, after the gluing of the component (refer to Figure 6):
— a conductor layer formed by a conductor foil 2 and a conductor pattern 6,
— an adhesive layer 10,
- optionally an insulating-material layer 11 between the conductor layer and the adhesive layer 10,
- contact openings 8, and
- at least one component 9.
In this modified embodiment, there is not recess 4 to be filled, instead in this stage an insulator layer 1, which surrounds the component 9 and supports the conductor layers 2 and 6, is made on the surface with the component 9 of the circuit-board blank. The insulator layer 1 can be formed, for example, by putting an insulating-material sheet, in which openings have been made at the location of the components 9, on top on the circuit-board blank. In addition, a unified insulating-material sheet can be put on top of the insulating-material sheet 9. Both sheets can be similar, or sheets than differ from each other can also be used, at least one of which is prehardened or unhardened. Examples of materials suitable for the insulator layer 1 are PI (polyimide), FR4, FR5, aramid, polytetrafluoroethylene, Teflon®, LCP (liquid crystal polymer), and a prehardened binder layer, i.e. prepreg. The insulating-material sheets put on top of the circuit-board blank are pressed, with the aid of heat and pressure, to form a unified insulator layer 1. In the insulating-material sheets, on the upper surface of one can also be a ready conductor-pattern layer, so that after pressing the circuit-board blank comprises at least two conductor-pattern layers, as shown by the series of figures. In this embodiment, conductor patterns 7 can, however, also be designed at the location of the components 9.
Both in the example shown in the figure series and in the above described modification, it is next possible to make vias 13, with the aid of which electrical contacts are made between the contact areas of the components 9 and the conductor patterns 6. For the making of vias, the contact openings 8 are cleaned of adhesive and other materials that may have been pushed into them. In connection with the cleaning of the contact openings 8, it is also possible to clean the contact areas of the components 9, thus further improving the preconditions for making a high-quality electrical contact. The cleaning can be performed using, for example, a plasma technique, chemically, or with the aid of a laser. If the contact openings 4 and the contact areas are already sufficiently clean, the cleaning can naturally be omitted.
If the contact openings 8 were made to only partly penetrate, the contact openings 8 are opened in this stage. It is also possible to proceed in such a way that the contact openings 8 are made entirely in this stage.
After cleaning, it is also possible to examine the success of the alignment of the component 9, as the contact areas of a correctly aligned component will be visible through the contact openings 8, when viewed from the direction of the conductor pattern.
After this, a conductor material is introduced to the contact openings 8, in such a way that it forms an electrical contact between the component 9 and the conductor pattern 6. The conductor material of the vias 13 can be made, for example, by filling the contact openings 8 with an electrically conductive paste. The conductor material can also be made using one of several growing methods known in the circuit-board industry. High- quality electrical contacts can be made, for example, by forming a metallurgical connection by growing a conductor material using a surfacing method, for example, a chemical or electrochemical method. One good alternative is the growing of a thin layer using a chemical method and continuing the growing using a more economical electrochemical method. The term filling refers to the fact that the contact openings are at least substantially filled with the conductor material. Instead of filling, surfacing can also be performed in such a way that only the edges of the contact openings are surfaced. In addition to these methods, it is of course possible to also use some other method, which will be beneficial in terms of the end result.
In the example of the figure series, the contact openings 8, the contact areas of the component 9, and the conductor patterns 6 are surfaced first of all with a thin conductor layer and then afterwards the thickness of the conductor layer is increased electrolytically until the contact openings 8 are filled with conductor material. Figure 7 shows the structure after the growing. After this, the circuit-board blank is etched, to remove the excess conductor material. If a protective membrane is used on the surface of the conductor patterns 6 and 7, the conductor material is removed essentially only from those parts of the conductor foils 2 and 3 that remain outside the conductor patterns 6 and 7. Alternatively, it is possible to etch the entire conductor layer, so that the material of the conductor foils 2 and 3 is removed from outside the conductor patterns 6 and 7. In that case, material of the conductor patterns 6 and 7 too will be removed, but the conductor patterns 6 and 7 will be copied into the material of the conductor foils 2 and 3.
The series of Figures 9 - 16 shows one variation of the examples described above. In the variation, the suitable parts of the method stages described above are utilized and the procedure is as follows:
- A circuit-board blank is made, which comprises an insulator layer 1, a recess 4, and conductor foils 2 and 3 (Figure 9).
- Photoresists 5 are spread and exposure takes place through the masks (Figure 10). The exposed areas 5' are shown darkened in the figure.
- Contact openings 8 are made (Figure 11).
- Adhesive 10 is spread (Figure 12).
- The component 9 is attached to the circuit-board blank with the aid of an adhesive layer 10 (Figure 13) and the recess 4 is filled with a filler agent 12. - The resist is developed, so that all that remains are the unexposed areas of the resist
5. The contact openings 8 are cleaned. The circuit-board blank after these stages is shown in Figure 14.
- Conductor material is grown using an electrolytic method. The conductor material then grows in the openings of the resist 5 and the contact openings 8 are filled, thus forming both conductor patterns 6 and 7 and vias 13 (Figure 15).
- The resist 5 is removed and the conductor material is etched, so that the desired conductor pattern is separated from the conductor layer when the conductor material is removed from the areas between the conductor patterns (Figure 16).
In the embodiment shown in the series of Figures 9 - 16 the conductor foils 2 and 3 are preferably thin relative to the conductor patterns 6 and 7 to be grown on their surfaces. The conductor foils 2 and 3 are thus intended to conduct the current required by the electrolytic growing to the growing areas. If the conductor foils 2 and 3 are thin relative to the conductor patterns 6 and 7, the etching of the conductor foils 2 and 3 away from outside the conductor patterns 6 and 7 will not substantially affect the relative dimensions of the conductor patterns 6 and 7.
The series of Figures 17 - 22 shows a third variation of the examples described above. In the variation, suitable parts of the method stages described above are utilized and the procedure is as follows:
- A circuit-board blank is made, which comprises a conductor foil 2 and a conductor pattern 6 (Figure 17). This can be made, for example, in such a way that a resist "5, which is exposed and developed, is spread on top of the conductor foil 2. After this, metal is grown in the openings formed in the resist 5, for example, using an electrochemical method. In this variation, contact openings are also defined in the exposure mask of the resist, so that the resist will remain at the locations of the contact openings 8'. Thus, in connection with the growing of the conductor pattern
6, contact openings 8 are also formed in the conductor patterns 6, and are thus aligned directly and in a self-aligning manner in the correct places relative to the conductor pattern 6. - The resist is removed and the contact openings 8 are opened to also extend through the conductor foil 2 (Figure 18).
- The component 9 is glued onto the surface of the conductor pattern 6 with the aid of an adhesive 10 (Figure 19). The component is aligned in the correct position relative to the conductor pattern 6 and the contact openings 8.
- An insulating-material layer 1 is made on top of the circuit-board blank (Figure 20).
- The contact openings 8 are cleaned and vias 13 are made in the contact openings from a conductor material (Figure 21). hi the example of the figure, the vias 13 are made using a surfacing method. In that case, the vias are surfaced in such a way that the necessary electrical contact arises, i.e. generally a conductor layer is made at least on the edges of the contact openings 8. In the example of the figure, the contact openings 8 are grown full of the conductor material. The more conductor material is put into a via 13, the better will be the conductivity of the via 13. The vias 13 are indeed preferably made to be at least substantially filled with conductor material.
- The conductor foil 2 is removed, for example, by etching (Figure 22).
The series of Figures 23 - 26 shown a fourth variation of the examples described above. In the variation, suitable parts of the method stages described above are utilized and the procedure is as follows:
- A circuit-board blank is made, which comprises a conductor foil 2 and a conductor pattern 6 (Figure 23). This can be made, for example, in such a way that a resist 5, which is exposed and developed, is spread on top of the conductor foil 2. After this, metal is grown in the openings formed in the resist 5, for example, using an electrochemical method.
- A component 9 is glued on top of the conductor pattern 6, with the aid of an anisotropically conductive adhesive 20 (Figure 24). The anisotropically conductive adhesive 20 forms an electrical contact in the direction between the contact areas of the component and the conductor pattern 6. The adhesive 20 is, however, electrically insulating in the transverse direction, so that an electrical contact is not formed between the contact areas of the component, nor between the separate conductors of the conductor pattern 6.
- An insulating-material layer 1 is made on top of the circuit-board blank and on the surface of that a conductor foil 3 (Figure 25).
- The conductor foil 2 is removed, for example, by etching. The conductor foil 3 is patterned to form a conductor pattern 7 (Figure 26).
The series of Figures 27 - 32 shows a fifth variation of the examples described above. In the method, suitable parts of the method stages described above are utilized, and the procedure is as follows:
- A circuit-board blank is made, which comprises a conductor foil 2 and a conductor pattern 6 (Figure 27). This can be made, for example, in such a way that a resist 5, which is exposed and developed, is spread onto top of the conductor foil 2. After this, metal is grown in the openings formed in the resist 5, for example, using an electrochemical method.
- A second resist 15, which is exposed and developed, is spread on top of the resist 5 and conductor pattern 6. A conductor material is made in the opening formed in the resist 15, for example, using an electrochemical method. The made conductor areas form contact bumps 17 on the surface of the conductor pattern 6 (Figure 28).
- The resists 5 and 15 are removed (Figure 29).
- A component 9 is attached on top of the conductor pattern 6 and against the contact bumps 17, using a suitable method (Figure 30). In the example of the figure, the joint is made by an ultrasonic bonding method or alternatively by a thermo- compression bonding method. Ih the example of the figure, a component 9 is used, which does not itself contain contact bumps.
- An insulating-material layer 1 is made on top of the circuit-board blank, and a conductor foil 3 of top of that (Figure 31).
- The conductor foil 2 is removed, for example, by etching. The conductor foil 3 is patterned to form a conductor pattern 7 (Figure 32). In the embodiments, it is possible to also use a separate support layer to support the conductor foil, or the conductor layer formed by the conductor foil and the conductor pattern.
A suitable intermediate layer, which will not dissolve in the etching agent used, or will dissolve in it extremely slowly, can also be used between the conductor foil and the conductor pattern, or on the surface of either of them. Thus the etching stops at the intermediate layer and the desired surface can be defined precisely. An intermediate layer of this kind can be made, for example, from some other metal, such as tin. If necessary, the intermediate layer can be removed, for example, chemically with some other etching agent.
When using a manufacturing method, in which the contact openings 8 are aligned and made after the manufacture of the conductor pattern 6, the sensitivity of the method to alignment errors can be reduced by dimensioning the diameter of the contact openings 8 to be greater than the width of the conductors of the conductor pattern 6.
There are numerous variations of the methods according to the examples presented above while the methods depicted by the examples can also be combined with each other. The variations can relate to individual process stages, or to the mutual sequence of the process stages.
Many features, which do not appear in the previous examples, can also be manufactured into the circuit-board structure. For example, in addition to vias that participate in the creation of electrical contacts, thermal vias can also be made, which are intended to conduct heat more efficiently away from the component 9. The increase in the efficiency of heat conducting is based on the thermal conductivity of the thermal via being greater than that of the insulating material surrounding the component. As electrical conductors are typically also good thermal conductors, the thermal vias can in most cases be made using the same technique and even in the same process stage as the electrical contacts to the components 9.
On the basis of the previous examples, it is obvious that the method can also be used for manufacturing many different kinds of three-dimensional circuit structures. The method can be used, for example, in such a way that several components, for example, semiconductor chips, are placed on top of each other, thus forming a packet containing several components, in which the components are connected to each other to form a single functional totality. Such a packet can be termed a three-dimensional multi-chip module.
The examples of the figures depict some possible processes, with the aid of which our invention can be exploited. However, our invention is not restricted to only the processes described above, but instead the invention covers various other processes too and their end products, within the full scope of the Claims and taking equivalence interpretation into account. The invention is also not restricted to only the structures and methods described by the examples, but instead it will be obvious to one versed in the art that various applications of our invention can be used to manufacture very many different kinds of electronic modules and circuit boards, which may even differ greatly from the examples presented. Thus the components and circuits of the figures are presented only with the intention of illustrating the manufacturing process. Many alterations can be made to the processes of the examples described above, while nevertheless not deviating from the basic idea according to the invention. The alterations can related, for example, to the manufacturing techniques depicted in the various stages, or to the mutual sequence of the process stages.
With the aid of the invention, it is also possible to manufacture component packets for attachment to a circuit board. Such packets can also contain several components, which are connected electrically to each other.
The method can also be used to manufacture entire electrical modules. The module can also be a circuit board, to the outer surface of which components can be attached, in the same way as to a conventional circuit board.

Claims

Claims:
1. Method for manufacturing a circuit-board structure, the method comprising
- making a conductor layer, which comprises a conductor foil (2) and a conductor pattern (6) on the surface of the conductor foil,
- attaching a component (9) to the conductor layer,
- thinning the conductor layer, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern (6).
2. Method according to Claim 1, characterized in that the thickness of the conductor layer made is greater at the location of the conductor pattern (6) than outside the conductor pattern.
3. Method according to Claim 1 or 2, characterized in that the conductor layer is thinned selectively, in such a way that conductor material is removed from outside the conductor pattern (6), but the thickness of the conductor layer at the location of the conductor pattern remains essentially the same during thinning.
4. Method according to Claim Ior2, characterized in that the conductor layer is thinned throughout, in such a way that the thickness of the conductor layer diminishes both at the location of the conductor pattern (6) and outside the conductor pattern.
5. Method according to any of Claims 1 - 4, ch aracteri zed in that the component (9) is attached to the conductor layer on the side of the conductor pattern (6) and the conductor layer is thinned from the direction of the conductor foil (2).
6. Method according to any of Claims 1 - 4, ch ar act eri z e d in that the component (9) is attached to the conductor foil (2) side of the conductor layer and the conductor layer is thinned from the direction of the conductor pattern (6).
7. Method according to any of Claims 1 - 6, ch aracteri ze d in that the component (9) is attached to the conductor layer, in such a way that electrical contacts arise between the contact areas of the component and the conductor layer.
8. Method according Claim 7, characterized in that the electrical contacts are formed before the thinning of the conductor layer.
9. Method according to Claim 7 or 8, characterized in that openings (8) or recesses are made in the conductor layer for the electrical contacts (13) to be formed between the contact areas of the component (9) and the conductor layer.
10. Method according to Claim 9, characterized in that the openings (8) or recesses are made before the component (9) is attached.
11. Method according to Claim 9 or 10, characterized in that when the electrical contacts are being formed, the openings (8) or recesses are filled or surfaced with a conductor material, for example, by growing the conductor material in the openings or recesses, by a surfacing method, or by filling the openings or recesses with a conductive paste or adhesive.
12. Method according to any of Claims 7 - 11, characterized in that, before the creation of an electrical contact, the component (9) is glued onto the conductor layer.
13. Method according to any of Claims 1 - 12, characterized in that a via method is used in the attachment of the component (9), in order to make an electrical contact to the component (9).
14. Method according to Claim 7 or 8, characterized in that contact bumps (17) are made on the surface of the conductor layer, for the electrical contacts to be created between the contact areas of the component (9) and the conductor layer.
15. Method according to Claim 7, 8, or 14, characterized in that the electrical contacts are created using a thermo-compression method, an ultrasonic bonding method, soldering, or by means of a conductive adhesive.
16. Method according to any of Claims 1- 15, characterized in that after the attachment of the component (9), and before the thinning of the conductor layer, an insulator layer (1), which surrounds the component, is made on top of the conductor layer.
17. Method according to any of Claims 1 - 15, characterized in that the conductor layer is made or, or attached to the surface of the insulator layer (1) and the component (9) is attached to a hole (4) or recess, which is made in the insulator layer for the component.
18. Method according to any of Claims 1 - 17, characterized in that, in addition to the electrical contacts, at least one thermal contact, which is intended to conduct thermal energy away from the component (9) more efficiently, is made in the circuit-board structure.
19. Method according to any of Claims 1 - 18, characterized in that a patterned mask layer (5), which contains openings defining the conductor patterns (6), is formed on the surface of the conductor layer for making the conductor pattern (6), and the conductor pattern (6) is made in these openings by electrolytically growing.
20. Circuit-board structure, which is manufactured using a method according to any of Claims 1 - 19.
PCT/FI2006/000207 2005-06-16 2006-06-15 Circuit board structure and method for manufacturing a circuit board structure WO2006134216A2 (en)

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KR1020087000597A KR101090423B1 (en) 2005-06-16 2006-06-15 Circuit board structure and method for manufacturing a circuit board structure
EP06764433.6A EP1891845B1 (en) 2005-06-16 2006-06-15 Method for manufacturing a circuit board structure
JP2008516355A JP5025644B2 (en) 2005-06-16 2006-06-15 Circuit board structure and method for manufacturing circuit board structure
US11/917,737 US8581109B2 (en) 2005-06-16 2006-06-15 Method for manufacturing a circuit board structure
CN200680021055A CN100596258C (en) 2005-06-16 2006-06-15 Method for manufacturing a circuit board structure, and a circuit board structure
US14/076,292 US9622354B2 (en) 2005-06-16 2013-11-11 Method for manufacturing a circuit board structure
US15/355,096 US11134572B2 (en) 2005-06-16 2016-11-18 Circuit board structure and method for manufacturing a circuit board structure
US17/460,458 US11792941B2 (en) 2005-06-16 2021-08-30 Circuit board structure and method for manufacturing a circuit board structure

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FI20050646 2005-06-16
FI20050646A FI119714B (en) 2005-06-16 2005-06-16 Circuit board structure and method for manufacturing a circuit board structure

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US14/076,292 Continuation US9622354B2 (en) 2005-06-16 2013-11-11 Method for manufacturing a circuit board structure

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008199011A (en) * 2007-02-15 2008-08-28 Samsung Electro Mech Co Ltd Package board and method for manufacturing thereof
GB2451921A (en) * 2007-08-17 2009-02-18 Wolfson Microelectronics Plc MEMS package
GB2451908A (en) * 2007-08-17 2009-02-18 Wolfson Microelectronics Plc MEMS microphone package
WO2009098033A1 (en) * 2008-02-06 2009-08-13 Würth Elektronik Rot am See GmbH & Co. KG Method for producing a printed circuit board
WO2010048653A2 (en) 2008-10-30 2010-05-06 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Method for integrating an electronic component into a printed circuit board
US8124449B2 (en) 2008-12-02 2012-02-28 Infineon Technologies Ag Device including a semiconductor chip and metal foils
US8264085B2 (en) 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
US9287206B2 (en) 2008-08-04 2016-03-15 Infineon Technologies Ag Method of fabricating a semiconductor device with encapsulant
EP3352212A1 (en) * 2017-01-24 2018-07-25 General Electric Company Power electronics package and method of manufacturing thereof
US10332832B2 (en) 2017-08-07 2019-06-25 General Electric Company Method of manufacturing an electronics package using device-last or device-almost last placement

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI20031341A (en) 2003-09-18 2005-03-19 Imbera Electronics Oy Method for manufacturing an electronic module
FI117814B (en) * 2004-06-15 2007-02-28 Imbera Electronics Oy A method for manufacturing an electronic module
FI122128B (en) * 2005-06-16 2011-08-31 Imbera Electronics Oy Process for manufacturing circuit board design
GB2441265B (en) * 2005-06-16 2012-01-11 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
FI119714B (en) 2005-06-16 2009-02-13 Imbera Electronics Oy Circuit board structure and method for manufacturing a circuit board structure
JP2009239247A (en) * 2008-03-27 2009-10-15 Ibiden Co Ltd Method of manufacturing multilayer printed circuit board
WO2009118950A1 (en) 2008-03-27 2009-10-01 イビデン株式会社 Method for manufacturing multilayer printed wiring board
US8664750B2 (en) * 2008-11-17 2014-03-04 Advanpack Solutions Pte. Ltd. Semiconductor substrate, package and device
TWI456715B (en) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng Chip package structure and manufacturing method thereof
US8390083B2 (en) 2009-09-04 2013-03-05 Analog Devices, Inc. System with recessed sensing or processing elements
US8735735B2 (en) 2010-07-23 2014-05-27 Ge Embedded Electronics Oy Electronic module with embedded jumper conductor
CN102404936A (en) * 2010-09-07 2012-04-04 深南电路有限公司 Circuit board capable of embedding discrete part and manufacturing method thereof
WO2012051340A1 (en) 2010-10-12 2012-04-19 Analog Devices, Inc. Microphone package with embedded asic
KR101109356B1 (en) * 2010-10-20 2012-01-31 삼성전기주식회사 Method for manufacturing the embedded printed circuit board
TWI446495B (en) * 2011-01-19 2014-07-21 Subtron Technology Co Ltd Package carrier and manufacturing method thereof
WO2012164720A1 (en) * 2011-06-02 2012-12-06 株式会社メイコー Substrate with built-in component, and method for producing said substrate
JPWO2013027718A1 (en) * 2011-08-23 2015-03-19 株式会社フジクラ Component mounting printed circuit board and manufacturing method thereof
JP5955023B2 (en) * 2012-02-23 2016-07-20 京セラ株式会社 Printed wiring board with built-in component and manufacturing method thereof
FI20125725L (en) * 2012-06-26 2013-12-27 Tellabs Oy Circuit board arrangement with mechanical protection
EP2704536B1 (en) * 2012-08-31 2015-12-16 Harman Becker Automotive Systems GmbH Method for producing a circuit board system
US9451696B2 (en) * 2012-09-29 2016-09-20 Intel Corporation Embedded architecture using resin coated copper
KR101420526B1 (en) * 2012-11-29 2014-07-17 삼성전기주식회사 Substrate embedding electronic component and manufacturing mehtod thereof
CN104619118A (en) * 2013-10-18 2015-05-13 技嘉科技股份有限公司 Circuit layout structure and layout method thereof
CN104576883B (en) 2013-10-29 2018-11-16 普因特工程有限公司 Chip installation array substrate and its manufacturing method
US10219384B2 (en) 2013-11-27 2019-02-26 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Circuit board structure
AT515101B1 (en) 2013-12-12 2015-06-15 Austria Tech & System Tech Method for embedding a component in a printed circuit board
US11523520B2 (en) * 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
CN105226155B (en) * 2014-05-30 2018-02-23 无锡极目科技有限公司 Direct epitaxy growth LED method and application on laminated circuit board
CN105280563A (en) * 2014-06-10 2016-01-27 台湾应用模组股份有限公司 Thickness-reduced wafer card packaging device
US9999136B2 (en) 2014-12-15 2018-06-12 Ge Embedded Electronics Oy Method for fabrication of an electronic module and electronic module
US10141251B2 (en) * 2014-12-23 2018-11-27 General Electric Company Electronic packages with pre-defined via patterns and methods of making and using the same
US9666558B2 (en) 2015-06-29 2017-05-30 Point Engineering Co., Ltd. Substrate for mounting a chip and chip package using the substrate
CN106793555B (en) * 2015-11-23 2019-02-12 健鼎(无锡)电子有限公司 Circuit board package structure and its manufacturing method
US10453786B2 (en) * 2016-01-19 2019-10-22 General Electric Company Power electronics package and method of manufacturing thereof
KR102019351B1 (en) * 2016-03-14 2019-09-09 삼성전자주식회사 Electronic component package and manufactruing method of the same
CN109346415B (en) * 2018-09-20 2020-04-28 江苏长电科技股份有限公司 Packaging method and packaging equipment for selectively packaging structure
CN112470553A (en) * 2018-10-11 2021-03-09 深圳市修颐投资发展合伙企业(有限合伙) Composite process fan-out packaging method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040097086A1 (en) * 2002-09-26 2004-05-20 Yusuke Igarashi Method for manufacturing circuit devices
WO2005020651A1 (en) * 2003-08-26 2005-03-03 Imbera Electronics Oy Method for manufacturing an electronic module, and an electronic module
EP1542519A1 (en) * 2002-07-31 2005-06-15 Sony Corporation Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board

Family Cites Families (139)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4246595A (en) * 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
FR2527036A1 (en) * 1982-05-14 1983-11-18 Radiotechnique Compelec METHOD FOR CONNECTING A SEMICONDUCTOR TO ELEMENTS OF A SUPPORT, PARTICULARLY A PORTABLE CARD
US4541893A (en) * 1984-05-15 1985-09-17 Advanced Micro Devices, Inc. Process for fabricating pedestal interconnections between conductive layers in an integrated circuit
FR2599893B1 (en) * 1986-05-23 1996-08-02 Ricoh Kk METHOD FOR MOUNTING AN ELECTRONIC MODULE ON A SUBSTRATE AND INTEGRATED CIRCUIT CARD
US4993148A (en) * 1987-05-19 1991-02-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a circuit board
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
BE1002529A6 (en) * 1988-09-27 1991-03-12 Bell Telephone Mfg Method for an electronic component assembly and memory card in which it is applied.
JPH0744320B2 (en) * 1989-10-20 1995-05-15 松下電器産業株式会社 Resin circuit board and manufacturing method thereof
US5355102A (en) * 1990-04-05 1994-10-11 General Electric Company HDI impedance matched microwave circuit assembly
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5073814A (en) 1990-07-02 1991-12-17 General Electric Company Multi-sublayer dielectric layers
JPH0745938Y2 (en) 1991-01-21 1995-10-18 太陽誘電株式会社 Transformer cover
JP3094481B2 (en) 1991-03-13 2000-10-03 松下電器産業株式会社 Electronic circuit device and manufacturing method thereof
US5616520A (en) 1992-03-30 1997-04-01 Hitachi, Ltd. Semiconductor integrated circuit device and fabrication method thereof
US5985693A (en) * 1994-09-30 1999-11-16 Elm Technology Corporation High density three-dimensional IC interconnection
KR950012658B1 (en) * 1992-07-24 1995-10-19 삼성전자주식회사 Semiconductor chip mounting method and substrate structure
US5216806A (en) * 1992-09-01 1993-06-08 Atmel Corporation Method of forming a chip package and package interconnects
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5306670A (en) * 1993-02-09 1994-04-26 Texas Instruments Incorporated Multi-chip integrated circuit module and method for fabrication thereof
US5353195A (en) * 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
DE69405832T2 (en) * 1993-07-28 1998-02-05 Whitaker Corp Peripheral-independent precise position element for a semiconductor chip and manufacturing method therefor
JP2757748B2 (en) 1993-07-30 1998-05-25 日立エーアイシー株式会社 Printed wiring board
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5510580A (en) * 1993-12-07 1996-04-23 International Business Machines Corporation Printed circuit board with landless blind hole for connecting an upper wiring pattern to a lower wiring pattern
JPH08167630A (en) * 1994-12-15 1996-06-25 Hitachi Ltd Chip connection structure
JP3243956B2 (en) 1995-02-03 2002-01-07 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JPH08335653A (en) 1995-04-07 1996-12-17 Nitto Denko Corp Semiconductor device, its production and tape carrier for semiconductor device used for production of the semiconductor device
US5552633A (en) * 1995-06-06 1996-09-03 Martin Marietta Corporation Three-dimensional multimodule HDI arrays with heat spreading
JPH0913567A (en) 1995-06-30 1997-01-14 Mikio Yoshimatsu Floor slab and molding method therefor and executing method for floor slab
JPH09139567A (en) 1995-11-15 1997-05-27 Fujitsu Ltd Surface mounting component mounting pad in printed board and connection structure of through hole for interplayer connection use
CN1094717C (en) 1995-11-16 2002-11-20 松下电器产业株式会社 PC board and fixing body thereof
US5729049A (en) * 1996-03-19 1998-03-17 Micron Technology, Inc. Tape under frame for conventional-type IC package assembly
US5936847A (en) * 1996-05-02 1999-08-10 Hei, Inc. Low profile electronic circuit modules
US5838545A (en) * 1996-10-17 1998-11-17 International Business Machines Corporation High performance, low cost multi-chip modle package
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
JP3176307B2 (en) * 1997-03-03 2001-06-18 日本電気株式会社 Mounting structure of integrated circuit device and method of manufacturing the same
US6710614B1 (en) * 1997-03-04 2004-03-23 Micron Technology, Inc. Methods for using an interposer/converter to allow single-sided contact to circuit modules
JP3173410B2 (en) * 1997-03-14 2001-06-04 松下電器産業株式会社 Package substrate and method of manufacturing the same
US5882957A (en) * 1997-06-09 1999-03-16 Compeq Manufacturing Company Limited Ball grid array packaging method for an integrated circuit and structure realized by the method
JPH1126631A (en) * 1997-07-02 1999-01-29 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP3623639B2 (en) 1997-09-29 2005-02-23 京セラ株式会社 Manufacturing method of multilayer wiring board
US6038133A (en) * 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
GB2342995B (en) 1998-10-21 2003-02-19 Federal Ind Ind Group Inc Improvements in pulse-echo measurement systems
US6232666B1 (en) 1998-12-04 2001-05-15 Mciron Technology, Inc. Interconnect for packaging semiconductor dice and fabricating BGA packages
US6455354B1 (en) 1998-12-30 2002-09-24 Micron Technology, Inc. Method of fabricating tape attachment chip-on-board assemblies
JP3207174B2 (en) 1999-02-01 2001-09-10 京セラ株式会社 Wiring board mounted with electric element and method of manufacturing the same
JP3619421B2 (en) 1999-03-30 2005-02-09 京セラ株式会社 Manufacturing method of multilayer wiring board
US6288905B1 (en) 1999-04-15 2001-09-11 Amerasia International Technology Inc. Contact module, as for a smart card, and method for making same
JP3659167B2 (en) * 1999-04-16 2005-06-15 松下電器産業株式会社 Module parts and manufacturing method thereof
JP2000311229A (en) 1999-04-27 2000-11-07 Hitachi Ltd Ic card and its production
JP3575001B2 (en) * 1999-05-07 2004-10-06 アムコー テクノロジー コリア インコーポレーティド Semiconductor package and manufacturing method thereof
JP3213292B2 (en) 1999-07-12 2001-10-02 ソニーケミカル株式会社 Multilayer board and module
KR100298828B1 (en) * 1999-07-12 2001-11-01 윤종용 Method For Manufacturing Wafer Level Chip Scale Packages Using Rerouting Metallized Film And Soldering
JP2001053447A (en) 1999-08-05 2001-02-23 Iwaki Denshi Kk Multilayer wiring board with built-in part and manufacturing method thereof
DE60045566D1 (en) * 1999-08-06 2011-03-03 Ibiden Co Ltd Multi-layer printed circuit board
JP4526651B2 (en) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 Semiconductor device
DE19940480C2 (en) * 1999-08-26 2001-06-13 Orga Kartensysteme Gmbh Conductor carrier layer for lamination into a chip card, chip card with a conductor carrier carrier layer and method for producing a chip card
US6284564B1 (en) 1999-09-20 2001-09-04 Lockheed Martin Corp. HDI chip attachment method for reduced processing
US6297551B1 (en) 1999-09-22 2001-10-02 Agere Systems Guardian Corp. Integrated circuit packages with improved EMI characteristics
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
TW512653B (en) 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
JP2001156457A (en) 1999-11-30 2001-06-08 Taiyo Yuden Co Ltd Manufacturing method for electronic circuit device
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6475877B1 (en) * 1999-12-22 2002-11-05 General Electric Company Method for aligning die to interconnect metal on flex substrate
JP3809053B2 (en) 2000-01-20 2006-08-16 新光電気工業株式会社 Electronic component package
JP4685251B2 (en) 2000-02-09 2011-05-18 日本特殊陶業株式会社 Wiring board manufacturing method
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
EP1259103B1 (en) 2000-02-25 2007-05-30 Ibiden Co., Ltd. Multilayer printed wiring board and method for producing multilayer printed wiring board
JP4854845B2 (en) 2000-02-25 2012-01-18 イビデン株式会社 Multilayer printed circuit board
US6562660B1 (en) * 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
JP3537400B2 (en) * 2000-03-17 2004-06-14 松下電器産業株式会社 Semiconductor built-in module and method of manufacturing the same
JP2002016327A (en) 2000-04-24 2002-01-18 Ngk Spark Plug Co Ltd Wiring board and its manufacturing method
US6841740B2 (en) * 2000-06-14 2005-01-11 Ngk Spark Plug Co., Ltd. Printed-wiring substrate and method for fabricating the same
US6292366B1 (en) 2000-06-26 2001-09-18 Intel Corporation Printed circuit board with embedded integrated circuit
JP4230680B2 (en) 2000-06-29 2009-02-25 イビデン株式会社 Multilayer circuit board
JP2002289768A (en) 2000-07-17 2002-10-04 Rohm Co Ltd Semiconductor device and its manufacturing method
US6402970B1 (en) * 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6551861B1 (en) * 2000-08-22 2003-04-22 Charles W. C. Lin Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive
US6495406B1 (en) * 2000-08-31 2002-12-17 Micron Technology, Inc. Method of forming lightly doped drain MOS transistor including forming spacers on gate electrode pattern before exposing gate insulator
JP2002093811A (en) * 2000-09-11 2002-03-29 Sony Corp Manufacturing method of electrode and semiconductor device
US6489185B1 (en) * 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6713859B1 (en) * 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
JP2002094200A (en) * 2000-09-18 2002-03-29 Matsushita Electric Ind Co Ltd Circuit board, electric insulating material therefor and method of manufacturing the same
JP3554533B2 (en) * 2000-10-13 2004-08-18 シャープ株式会社 Chip-on-film tape and semiconductor device
US6876072B1 (en) * 2000-10-13 2005-04-05 Bridge Semiconductor Corporation Semiconductor chip assembly with chip in substrate cavity
US6576493B1 (en) * 2000-10-13 2003-06-10 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
JP4283987B2 (en) 2000-11-20 2009-06-24 富士フイルム株式会社 Photosensitive thermosetting resin composition, photosensitive thermosetting resin layer transfer material using the same, and image forming method
JP2002158307A (en) 2000-11-22 2002-05-31 Toshiba Corp Semiconductor device and its manufacturing method
JP3407737B2 (en) * 2000-12-14 2003-05-19 株式会社デンソー Multilayer substrate manufacturing method and multilayer substrate formed by the manufacturing method
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
TW511415B (en) * 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
US6512182B2 (en) * 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
JP4863563B2 (en) 2001-03-13 2012-01-25 イビデン株式会社 Printed wiring board and printed wiring board manufacturing method
TW579581B (en) * 2001-03-21 2004-03-11 Ultratera Corp Semiconductor device with chip separated from substrate and its manufacturing method
JP3609737B2 (en) * 2001-03-22 2005-01-12 三洋電機株式会社 Circuit device manufacturing method
US6734435B2 (en) * 2001-05-29 2004-05-11 Rae Systems, Inc. Photo-ionization detector and method for continuous operation and real-time self-cleaning
US6537848B2 (en) * 2001-05-30 2003-03-25 St. Assembly Test Services Ltd. Super thin/super thermal ball grid array package
JP2003037205A (en) 2001-07-23 2003-02-07 Sony Corp Multilayer substrate with built-in ic-chip, and method of manufacturing the same
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6774486B2 (en) * 2001-10-10 2004-08-10 Micron Technology, Inc. Circuit boards containing vias and methods for producing same
JP2003229513A (en) * 2001-11-29 2003-08-15 Sony Corp Substrate incorporating element and method of manufacturing the same
JP3870778B2 (en) 2001-12-20 2007-01-24 ソニー株式会社 Manufacturing method of element-embedded substrate and element-embedded substrate
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
FI115285B (en) 2002-01-31 2005-03-31 Imbera Electronics Oy Method of immersing a component in a base material and forming a contact
US8455994B2 (en) * 2002-01-31 2013-06-04 Imbera Electronics Oy Electronic module with feed through conductor between wiring patterns
FI119215B (en) * 2002-01-31 2008-08-29 Imbera Electronics Oy A method for immersing a component in a substrate and an electronic module
US6701614B2 (en) 2002-02-15 2004-03-09 Advanced Semiconductor Engineering Inc. Method for making a build-up package of a semiconductor
JP2003249763A (en) * 2002-02-25 2003-09-05 Fujitsu Ltd Multilayer interconnection board and manufacturing method thereof
TW533521B (en) * 2002-02-27 2003-05-21 Advanced Semiconductor Eng Solder ball process
JP3608559B2 (en) * 2002-03-26 2005-01-12 ソニー株式会社 Method for manufacturing element-embedded substrate
TW557536B (en) * 2002-05-27 2003-10-11 Via Tech Inc High density integrated circuit packages and method for the same
JP2004031651A (en) * 2002-06-26 2004-01-29 Sony Corp Element mounting substrate and its manufacturing method
US20040068852A1 (en) * 2002-10-15 2004-04-15 Enos Nolan Wheel helper
JP2004146634A (en) 2002-10-25 2004-05-20 Murata Mfg Co Ltd Resin board fabricating process and resin multilayer board fabricating process
FI119583B (en) 2003-02-26 2008-12-31 Imbera Electronics Oy Procedure for manufacturing an electronics module
FI20030293A (en) 2003-02-26 2004-08-27 Imbera Electronics Oy Method for manufacturing an electronic module and an electronic module
CN100405881C (en) * 2003-03-18 2008-07-23 日本特殊陶业株式会社 Wiring board
FI115601B (en) * 2003-04-01 2005-05-31 Imbera Electronics Oy Method for manufacturing an electronic module and an electronic module
JP2004327612A (en) * 2003-04-23 2004-11-18 Tdk Corp Substrate having conductor line, its manufacturing method and electronic component
JP4070659B2 (en) 2003-04-23 2008-04-02 シャープ株式会社 Method for manufacturing field effect transistor
TW200507131A (en) * 2003-07-02 2005-02-16 North Corp Multi-layer circuit board for electronic device
US7141884B2 (en) * 2003-07-03 2006-11-28 Matsushita Electric Industrial Co., Ltd. Module with a built-in semiconductor and method for producing the same
FI20031341A (en) 2003-09-18 2005-03-19 Imbera Electronics Oy Method for manufacturing an electronic module
CN100485913C (en) * 2004-02-24 2009-05-06 揖斐电株式会社 Substrate for mounting semiconductor
FI20041680A (en) 2004-04-27 2005-10-28 Imbera Electronics Oy Electronics module and method for its manufacture
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
US7404680B2 (en) * 2004-05-31 2008-07-29 Ngk Spark Plug Co., Ltd. Optical module, optical module substrate and optical coupling structure
TWI251910B (en) * 2004-06-29 2006-03-21 Phoenix Prec Technology Corp Semiconductor device buried in a carrier and a method for fabricating the same
US8487194B2 (en) * 2004-08-05 2013-07-16 Imbera Electronics Oy Circuit board including an embedded component
FI117812B (en) * 2004-08-05 2007-02-28 Imbera Electronics Oy Manufacture of a layer containing a component
JP2006100666A (en) * 2004-09-30 2006-04-13 Toshiba Corp Semiconductor device and manufacturing method thereof
FI117369B (en) * 2004-11-26 2006-09-15 Imbera Electronics Oy Procedure for manufacturing an electronics module
FI119714B (en) 2005-06-16 2009-02-13 Imbera Electronics Oy Circuit board structure and method for manufacturing a circuit board structure
JP4826248B2 (en) 2005-12-19 2011-11-30 Tdk株式会社 IC built-in substrate manufacturing method
SG139594A1 (en) 2006-08-04 2008-02-29 Micron Technology Inc Microelectronic devices and methods for manufacturing microelectronic devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1542519A1 (en) * 2002-07-31 2005-06-15 Sony Corporation Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board
US20040097086A1 (en) * 2002-09-26 2004-05-20 Yusuke Igarashi Method for manufacturing circuit devices
WO2005020651A1 (en) * 2003-08-26 2005-03-03 Imbera Electronics Oy Method for manufacturing an electronic module, and an electronic module

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008199011A (en) * 2007-02-15 2008-08-28 Samsung Electro Mech Co Ltd Package board and method for manufacturing thereof
GB2451921A (en) * 2007-08-17 2009-02-18 Wolfson Microelectronics Plc MEMS package
GB2451908A (en) * 2007-08-17 2009-02-18 Wolfson Microelectronics Plc MEMS microphone package
GB2451908B (en) * 2007-08-17 2009-12-02 Wolfson Microelectronics Plc Mems package
WO2009098033A1 (en) * 2008-02-06 2009-08-13 Würth Elektronik Rot am See GmbH & Co. KG Method for producing a printed circuit board
US8264085B2 (en) 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
US8669175B2 (en) 2008-05-05 2014-03-11 Infineon Technologies Ag Semiconductor device and manufacturing of the semiconductor device
US9287206B2 (en) 2008-08-04 2016-03-15 Infineon Technologies Ag Method of fabricating a semiconductor device with encapsulant
US8914974B2 (en) 2008-10-30 2014-12-23 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Method for integrating an electronic component into a printed circuit board
WO2010048653A2 (en) 2008-10-30 2010-05-06 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Method for integrating an electronic component into a printed circuit board
US8124449B2 (en) 2008-12-02 2012-02-28 Infineon Technologies Ag Device including a semiconductor chip and metal foils
US8680668B2 (en) 2008-12-02 2014-03-25 Infineon Technologies Ag Device including a semiconductor chip and metal foils
EP3352212A1 (en) * 2017-01-24 2018-07-25 General Electric Company Power electronics package and method of manufacturing thereof
US10332832B2 (en) 2017-08-07 2019-06-25 General Electric Company Method of manufacturing an electronics package using device-last or device-almost last placement

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US20210392752A1 (en) 2021-12-16
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WO2006134216A3 (en) 2007-07-05
US8581109B2 (en) 2013-11-12

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